1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx |
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5 | * |
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6 | * @brief System clocks. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008 |
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11 | * Embedded Brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be found in the file |
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18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <bsp.h> |
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22 | #include <bsp/utility.h> |
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23 | #include <bsp/lpc24xx.h> |
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24 | #include <bsp/system-clocks.h> |
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25 | |
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26 | /** |
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27 | * @brief Internal RC oscillator frequency in [Hz]. |
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28 | */ |
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29 | #define LPC24XX_OSCILLATOR_INTERNAL 4000000U |
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30 | |
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31 | #ifndef LPC24XX_OSCILLATOR_MAIN |
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32 | #error "unknown main oscillator frequency" |
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33 | #endif |
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34 | |
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35 | #ifndef LPC24XX_OSCILLATOR_RTC |
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36 | #error "unknown RTC oscillator frequency" |
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37 | #endif |
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38 | |
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39 | /** |
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40 | * @brief Delay for @a us micro seconds. |
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41 | * |
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42 | * @note Uses Timer 1. |
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43 | */ |
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44 | void lpc24xx_micro_seconds_delay( unsigned us) |
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45 | { |
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46 | /* Stop and reset timer */ |
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47 | T1TCR = 0x02; |
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48 | |
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49 | /* Set prescaler to zero */ |
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50 | T1PR = 0x00; |
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51 | |
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52 | /* Set match value */ |
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53 | T1MR0 = (uint32_t) ((uint64_t) 4000000 * (uint64_t) us / (uint64_t) lpc24xx_cclk()) + 1; |
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54 | |
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55 | /* Reset all interrupt flags */ |
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56 | T1IR = 0xff; |
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57 | |
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58 | /* Stop timer on match */ |
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59 | T1MCR = 0x04; |
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60 | |
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61 | /* Start timer */ |
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62 | T1TCR = 0x01; |
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63 | |
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64 | /* Wait until delay time has elapsed */ |
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65 | while ((T1TCR & 0x01) != 0) { |
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66 | /* Wait */ |
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67 | } |
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68 | } |
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69 | |
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70 | /** |
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71 | * @brief Returns the PLL output clock frequency in [Hz]. |
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72 | * |
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73 | * Returns zero in case of an unexpected PLL input frequency. |
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74 | */ |
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75 | unsigned lpc24xx_pllclk( void) |
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76 | { |
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77 | unsigned clksrc = GET_CLKSRCSEL_CLKSRC( CLKSRCSEL); |
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78 | unsigned pllinclk = 0; |
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79 | unsigned pllclk = 0; |
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80 | |
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81 | /* Get PLL input frequency */ |
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82 | switch (clksrc) { |
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83 | case 0: |
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84 | pllinclk = LPC24XX_OSCILLATOR_INTERNAL; |
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85 | break; |
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86 | case 1: |
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87 | pllinclk = LPC24XX_OSCILLATOR_MAIN; |
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88 | break; |
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89 | case 2: |
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90 | pllinclk = LPC24XX_OSCILLATOR_RTC; |
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91 | break; |
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92 | default: |
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93 | return 0; |
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94 | } |
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95 | |
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96 | /* Get PLL output frequency */ |
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97 | if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) { |
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98 | uint32_t pllcfg = PLLCFG; |
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99 | unsigned n = GET_PLLCFG_NSEL( pllcfg) + 1; |
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100 | unsigned m = GET_PLLCFG_MSEL( pllcfg) + 1; |
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101 | |
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102 | pllclk = (pllinclk / n) * 2 * m; |
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103 | } else { |
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104 | pllclk = pllinclk; |
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105 | } |
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106 | |
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107 | return pllclk; |
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108 | } |
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109 | |
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110 | /** |
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111 | * @brief Returns the CPU clock frequency in [Hz]. |
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112 | * |
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113 | * Returns zero in case of an unexpected PLL input frequency. |
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114 | */ |
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115 | unsigned lpc24xx_cclk( void) |
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116 | { |
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117 | /* Get PLL output frequency */ |
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118 | unsigned pllclk = lpc24xx_pllclk(); |
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119 | |
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120 | /* Get CPU frequency */ |
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121 | unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL( CCLKCFG) + 1); |
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122 | |
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123 | return cclk; |
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124 | } |
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125 | |
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126 | static void lpc24xx_pll_config( uint32_t val) |
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127 | { |
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128 | PLLCON = val; |
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129 | PLLFEED = 0xaa; |
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130 | PLLFEED = 0x55; |
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131 | } |
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132 | |
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133 | /** |
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134 | * @brief Sets the Phase Locked Loop (PLL). |
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135 | * |
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136 | * @param clksrc Selects the clock source for the PLL. |
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137 | * |
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138 | * @param nsel Selects PLL pre-divider value (sometimes named psel). |
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139 | * |
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140 | * @param msel Selects PLL multiplier value. |
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141 | * |
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142 | * @param cclksel Selects the divide value for creating the CPU clock (CCLK) |
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143 | * from the PLL output. |
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144 | * |
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145 | * @note All parameter values are the actual register field values. |
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146 | */ |
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147 | void lpc24xx_set_pll( unsigned clksrc, unsigned nsel, unsigned msel, unsigned cclksel) |
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148 | { |
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149 | bool pll_enabled = IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLE); |
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150 | |
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151 | /* Disconnect PLL if necessary */ |
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152 | if (IS_FLAG_SET( PLLSTAT, PLLSTAT_PLLC)) { |
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153 | if (pll_enabled) { |
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154 | lpc24xx_pll_config( PLLCON_PLLE); |
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155 | } else { |
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156 | lpc24xx_pll_config( 0); |
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157 | } |
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158 | } |
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159 | |
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160 | /* Set CPU clock divider to a reasonable save value */ |
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161 | CCLKCFG = 0; |
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162 | |
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163 | /* Disable PLL if necessary */ |
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164 | if (pll_enabled) { |
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165 | lpc24xx_pll_config( 0); |
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166 | } |
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167 | |
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168 | /* Select clock source */ |
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169 | CLKSRCSEL = SET_CLKSRCSEL_CLKSRC( 0, clksrc); |
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170 | |
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171 | /* Set PLL Configuration Register */ |
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172 | PLLCFG = SET_PLLCFG_NSEL( 0, nsel) | SET_PLLCFG_MSEL( 0, msel); |
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173 | |
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174 | /* Enable PLL */ |
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175 | lpc24xx_pll_config( PLLCON_PLLE); |
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176 | |
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177 | /* Wait for lock */ |
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178 | while (IS_FLAG_CLEARED( PLLSTAT, PLLSTAT_PLOCK)) { |
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179 | /* Wait */ |
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180 | } |
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181 | |
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182 | /* Set CPU clock divider and ensure that we have an odd value */ |
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183 | CCLKCFG = SET_CCLKCFG_CCLKSEL( 0, cclksel | 1); |
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184 | |
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185 | /* Connect PLL */ |
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186 | lpc24xx_pll_config( PLLCON_PLLE | PLLCON_PLLC); |
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187 | } |
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