1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_interrupt |
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5 | * |
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6 | * @brief LPC24XX interrupt support. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <rtems/score/armv4.h> |
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24 | #include <rtems/score/armv7m.h> |
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25 | |
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26 | #include <bsp.h> |
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27 | #include <bsp/irq.h> |
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28 | #include <bsp/irq-generic.h> |
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29 | #include <bsp/lpc24xx.h> |
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30 | #include <bsp/linker-symbols.h> |
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31 | |
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32 | static inline bool lpc24xx_irq_is_valid(rtems_vector_number vector) |
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33 | { |
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34 | return vector <= BSP_INTERRUPT_VECTOR_MAX; |
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35 | } |
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36 | |
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37 | void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority) |
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38 | { |
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39 | if (lpc24xx_irq_is_valid(vector)) { |
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40 | if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) { |
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41 | priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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42 | } |
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43 | |
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44 | #ifdef ARM_MULTILIB_ARCH_V4 |
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45 | VICVectPriorityBase [vector] = priority; |
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46 | #else |
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47 | _ARMV7M_NVIC_Set_priority((int) vector, (int) (priority << 3)); |
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48 | #endif |
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49 | } |
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50 | } |
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51 | |
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52 | unsigned lpc24xx_irq_get_priority(rtems_vector_number vector) |
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53 | { |
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54 | if (lpc24xx_irq_is_valid(vector)) { |
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55 | #ifdef ARM_MULTILIB_ARCH_V4 |
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56 | return VICVectPriorityBase [vector]; |
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57 | #else |
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58 | return (unsigned) (_ARMV7M_NVIC_Get_priority((int) vector) >> 3); |
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59 | #endif |
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60 | } else { |
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61 | return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1U; |
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62 | } |
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63 | } |
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64 | |
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65 | #ifdef ARM_MULTILIB_ARCH_V4 |
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66 | |
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67 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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68 | { |
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69 | VICIntEnable = 1U << vector; |
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70 | |
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71 | return RTEMS_SUCCESSFUL; |
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72 | } |
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73 | |
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74 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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75 | { |
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76 | VICIntEnClear = 1U << vector; |
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77 | |
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78 | return RTEMS_SUCCESSFUL; |
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79 | } |
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80 | |
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81 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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82 | { |
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83 | volatile uint32_t *addr = VICVectAddrBase; |
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84 | volatile uint32_t *prio = VICVectPriorityBase; |
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85 | rtems_vector_number i = 0; |
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86 | |
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87 | /* Disable all interrupts */ |
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88 | VICIntEnClear = 0xffffffff; |
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89 | |
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90 | /* Clear all software interrupts */ |
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91 | VICSoftIntClear = 0xffffffff; |
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92 | |
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93 | /* Use IRQ category */ |
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94 | VICIntSelect = 0; |
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95 | |
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96 | for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) { |
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97 | /* Use the vector address register to store the vector number */ |
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98 | addr [i] = i; |
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99 | |
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100 | /* Give vector lowest priority */ |
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101 | prio [i] = 15; |
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102 | } |
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103 | |
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104 | /* Reset priority mask register */ |
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105 | VICSWPrioMask = 0xffff; |
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106 | |
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107 | /* Acknowledge interrupts for all priorities */ |
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108 | for ( |
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109 | i = LPC24XX_IRQ_PRIORITY_VALUE_MIN; |
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110 | i <= LPC24XX_IRQ_PRIORITY_VALUE_MAX; |
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111 | ++i |
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112 | ) { |
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113 | VICVectAddr = 0; |
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114 | } |
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115 | |
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116 | /* Install the IRQ exception handler */ |
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117 | _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL); |
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118 | |
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119 | return RTEMS_SUCCESSFUL; |
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120 | } |
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121 | |
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122 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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