source:
rtems/c/src/lib/libbsp/arm/lpc24xx/irq/irq-dispatch.c
@
df40cc9
Last change on this file since df40cc9 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47 | |
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File size: 1.0 KB |
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[2a514e80] | 1 | /** |
2 | * @file | |
3 | * | |
4 | * @ingroup bsp_interrupt | |
5 | * | |
6 | * @brief LPC24XX interrupt support. | |
7 | */ | |
8 | ||
9 | /* | |
[14ee5a1e] | 10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
[2a514e80] | 11 | * |
12 | * embedded brains GmbH | |
13 | * Obere Lagerstr. 30 | |
14 | * 82178 Puchheim | |
15 | * Germany | |
16 | * <rtems@embedded-brains.de> | |
17 | * | |
18 | * The license and distribution terms for this file may be | |
19 | * found in the file LICENSE in this distribution or at | |
[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
[2a514e80] | 21 | */ |
22 | ||
[8df0e91] | 23 | #include <rtems/score/armv4.h> |
24 | ||
[2a514e80] | 25 | #include <bsp.h> |
[4a6cc2a] | 26 | #include <bsp/irq.h> |
[2a514e80] | 27 | #include <bsp/irq-generic.h> |
28 | #include <bsp/lpc24xx.h> | |
29 | ||
[bd0fb473] | 30 | #ifdef ARM_MULTILIB_ARCH_V4 |
31 | ||
[2a514e80] | 32 | void bsp_interrupt_dispatch(void) |
33 | { | |
[bd0fb473] | 34 | /* Read current vector number */ |
35 | rtems_vector_number vector = VICVectAddr; | |
[2a514e80] | 36 | |
[bd0fb473] | 37 | /* Enable interrupts in program status register */ |
[0f7abd99] | 38 | uint32_t psr = _ARMV4_Status_irq_enable(); |
[2a514e80] | 39 | |
[bd0fb473] | 40 | /* Dispatch interrupt handlers */ |
41 | bsp_interrupt_handler_dispatch(vector); | |
[2a514e80] | 42 | |
[bd0fb473] | 43 | /* Restore program status register */ |
[0f7abd99] | 44 | _ARMV4_Status_restore(psr); |
[2a514e80] | 45 | |
[bd0fb473] | 46 | /* Acknowledge interrupt */ |
47 | VICVectAddr = 0; | |
[2a514e80] | 48 | } |
[bd0fb473] | 49 | |
50 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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