source: rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h @ 991fdb33

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Last change on this file since 991fdb33 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

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1/**
2 * @file
3 *
4 * @ingroup lpc24xx_regs
5 *
6 * @brief Register definitions.
7 */
8
9/*
10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
24#define LIBBSP_ARM_LPC24XX_LPC24XX_H
25
26#include <rtems/score/cpu.h>
27#include <bsp/utility.h>
28#include <bsp/lpc-i2s.h>
29
30#ifdef ARM_MULTILIB_ARCH_V7M
31  #include <bsp/lpc17xx.h>
32#endif
33
34/**
35 * @defgroup lpc24xx_regs Register Definitions
36 *
37 * @ingroup lpc24xx
38 *
39 * @brief Register definitions.
40 *
41 * @{
42 */
43
44#ifdef ARM_MULTILIB_ARCH_V4
45
46/* Vectored Interrupt Controller (VIC) */
47#define VIC_BASE_ADDR   0xFFFFF000
48#define VICIRQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
49#define VICFIQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004))
50#define VICRawIntr     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008))
51#define VICIntSelect   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C))
52#define VICIntEnable   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010))
53#define VICIntEnClear  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014))
54#define VICSoftInt     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018))
55#define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C))
56#define VICProtection  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020))
57#define VICSWPrioMask  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
58
59#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
60#define VICVectAddr0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
61#define VICVectAddr1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
62#define VICVectAddr2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108))
63#define VICVectAddr3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C))
64#define VICVectAddr4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110))
65#define VICVectAddr5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114))
66#define VICVectAddr6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118))
67#define VICVectAddr7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C))
68#define VICVectAddr8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120))
69#define VICVectAddr9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124))
70#define VICVectAddr10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128))
71#define VICVectAddr11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C))
72#define VICVectAddr12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130))
73#define VICVectAddr13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134))
74#define VICVectAddr14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138))
75#define VICVectAddr15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C))
76#define VICVectAddr16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140))
77#define VICVectAddr17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144))
78#define VICVectAddr18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148))
79#define VICVectAddr19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C))
80#define VICVectAddr20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150))
81#define VICVectAddr21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154))
82#define VICVectAddr22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158))
83#define VICVectAddr23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C))
84#define VICVectAddr24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160))
85#define VICVectAddr25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164))
86#define VICVectAddr26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168))
87#define VICVectAddr27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C))
88#define VICVectAddr28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170))
89#define VICVectAddr29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174))
90#define VICVectAddr30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178))
91#define VICVectAddr31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
92
93#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
94#define VICVectPriority0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
95#define VICVectPriority1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
96#define VICVectPriority2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208))
97#define VICVectPriority3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C))
98#define VICVectPriority4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210))
99#define VICVectPriority5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214))
100#define VICVectPriority6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218))
101#define VICVectPriority7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C))
102#define VICVectPriority8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220))
103#define VICVectPriority9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224))
104#define VICVectPriority10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228))
105#define VICVectPriority11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C))
106#define VICVectPriority12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230))
107#define VICVectPriority13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234))
108#define VICVectPriority14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238))
109#define VICVectPriority15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C))
110#define VICVectPriority16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240))
111#define VICVectPriority17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244))
112#define VICVectPriority18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248))
113#define VICVectPriority19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C))
114#define VICVectPriority20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250))
115#define VICVectPriority21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254))
116#define VICVectPriority22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258))
117#define VICVectPriority23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C))
118#define VICVectPriority24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260))
119#define VICVectPriority25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264))
120#define VICVectPriority26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268))
121#define VICVectPriority27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C))
122#define VICVectPriority28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270))
123#define VICVectPriority29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274))
124#define VICVectPriority30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278))
125#define VICVectPriority31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C))
126
127#define VICVectAddr    (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
128
129#endif /* ARM_MULTILIB_ARCH_V4 */
130
131/* Pin Connect Block */
132#ifdef ARM_MULTILIB_ARCH_V4
133  #define PINSEL_BASE_ADDR      0xE002C000
134#else
135  #define PINSEL_BASE_ADDR      0x4002C000
136#endif
137
138#ifdef ARM_MULTILIB_ARCH_V4
139
140#define PINSEL0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
141#define PINSEL1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
142#define PINSEL2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
143#define PINSEL3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C))
144#define PINSEL4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10))
145#define PINSEL5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14))
146#define PINSEL6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18))
147#define PINSEL7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C))
148#define PINSEL8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20))
149#define PINSEL9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
150#define PINSEL10       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
151#define PINSEL11       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C))
152
153#define PINMODE0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
154#define PINMODE1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44))
155#define PINMODE2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48))
156#define PINMODE3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C))
157#define PINMODE4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50))
158#define PINMODE5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54))
159#define PINMODE6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58))
160#define PINMODE7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C))
161#define PINMODE8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
162#define PINMODE9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
163
164#endif /* ARM_MULTILIB_ARCH_V4 */
165
166/* General Purpose Input/Output (GPIO) */
167#ifdef ARM_MULTILIB_ARCH_V4
168  #define GPIO_BASE_ADDR                0xE0028000
169#else
170  #define GPIO_BASE_ADDR                0x40028000
171#endif
172#define IOPIN0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
173#define IOSET0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
174#define IODIR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
175#define IOCLR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C))
176#define IOPIN1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10))
177#define IOSET1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14))
178#define IODIR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18))
179#define IOCLR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
180
181/* GPIO Interrupt Registers */
182#define IO0_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
183#define IO0_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
184#define IO0_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
185#define IO0_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
186#define IO0_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
187
188#define IO2_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
189#define IO2_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
190#define IO2_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
191#define IO2_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
192#define IO2_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC))
193
194#define IO_INT_STAT     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
195
196#ifdef ARM_MULTILIB_ARCH_V4
197
198#define PARTCFG_BASE_ADDR               0x3FFF8000
199#define PARTCFG        (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
200
201#endif /* ARM_MULTILIB_ARCH_V4 */
202
203/* Fast I/O setup */
204#ifdef ARM_MULTILIB_ARCH_V4
205  #define FIO_BASE_ADDR         0x3FFFC000
206#else
207  #define FIO_BASE_ADDR         0x20098000
208#endif
209#define FIO0DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
210#define FIO0MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
211#define FIO0PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
212#define FIO0SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
213#define FIO0CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
214
215#define FIO1DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
216#define FIO1MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
217#define FIO1PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
218#define FIO1SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
219#define FIO1CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
220
221#define FIO2DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
222#define FIO2MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
223#define FIO2PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
224#define FIO2SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
225#define FIO2CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
226
227#define FIO3DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
228#define FIO3MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
229#define FIO3PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
230#define FIO3SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
231#define FIO3CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
232
233#define FIO4DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
234#define FIO4MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
235#define FIO4PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
236#define FIO4SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
237#define FIO4CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
238
239#ifdef ARM_MULTILIB_ARCH_V7M
240
241#define FIO5DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0))
242#define FIO5MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0))
243#define FIO5PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4))
244#define FIO5SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8))
245#define FIO5CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC))
246
247#endif /* ARM_MULTILIB_ARCH_V7M */
248
249/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
250#define FIO0DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
251#define FIO1DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
252#define FIO2DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40))
253#define FIO3DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60))
254#define FIO4DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80))
255
256#define FIO0DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
257#define FIO1DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
258#define FIO2DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
259#define FIO3DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
260#define FIO4DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
261
262#define FIO0DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
263#define FIO1DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
264#define FIO2DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
265#define FIO3DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
266#define FIO4DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
267
268#define FIO0DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
269#define FIO1DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
270#define FIO2DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
271#define FIO3DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
272#define FIO4DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
273
274#define FIO0DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
275#define FIO1DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
276#define FIO2DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
277#define FIO3DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
278#define FIO4DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
279
280#define FIO0DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
281#define FIO1DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
282#define FIO2DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
283#define FIO3DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
284#define FIO4DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
285
286#define FIO0MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
287#define FIO1MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
288#define FIO2MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
289#define FIO3MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
290#define FIO4MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
291
292#define FIO0MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
293#define FIO1MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
294#define FIO2MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
295#define FIO3MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
296#define FIO4MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
297
298#define FIO0MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
299#define FIO1MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
300#define FIO2MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
301#define FIO3MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
302#define FIO4MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
303
304#define FIO0MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
305#define FIO1MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
306#define FIO2MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
307#define FIO3MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
308#define FIO4MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
309
310#define FIO0MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
311#define FIO1MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
312#define FIO2MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
313#define FIO3MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
314#define FIO4MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
315
316#define FIO0MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
317#define FIO1MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
318#define FIO2MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
319#define FIO3MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
320#define FIO4MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
321
322#define FIO0PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
323#define FIO1PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
324#define FIO2PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
325#define FIO3PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
326#define FIO4PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
327
328#define FIO0PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
329#define FIO1PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
330#define FIO2PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
331#define FIO3PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
332#define FIO4PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
333
334#define FIO0PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
335#define FIO1PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
336#define FIO2PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
337#define FIO3PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
338#define FIO4PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
339
340#define FIO0PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
341#define FIO1PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
342#define FIO2PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
343#define FIO3PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
344#define FIO4PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
345
346#define FIO0PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
347#define FIO1PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
348#define FIO2PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
349#define FIO3PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
350#define FIO4PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
351
352#define FIO0PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
353#define FIO1PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
354#define FIO2PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
355#define FIO3PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
356#define FIO4PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
357
358#define FIO0SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
359#define FIO1SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
360#define FIO2SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
361#define FIO3SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
362#define FIO4SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
363
364#define FIO0SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
365#define FIO1SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
366#define FIO2SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
367#define FIO3SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
368#define FIO4SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
369
370#define FIO0SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
371#define FIO1SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
372#define FIO2SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
373#define FIO3SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
374#define FIO4SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
375
376#define FIO0SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
377#define FIO1SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
378#define FIO2SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
379#define FIO3SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
380#define FIO4SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
381
382#define FIO0SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
383#define FIO1SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
384#define FIO2SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
385#define FIO3SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
386#define FIO4SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
387
388#define FIO0SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
389#define FIO1SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
390#define FIO2SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
391#define FIO3SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
392#define FIO4SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
393
394#define FIO0CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
395#define FIO1CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
396#define FIO2CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
397#define FIO3CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
398#define FIO4CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
399
400#define FIO0CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
401#define FIO1CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
402#define FIO2CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
403#define FIO3CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
404#define FIO4CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
405
406#define FIO0CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
407#define FIO1CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
408#define FIO2CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
409#define FIO3CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
410#define FIO4CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
411
412#define FIO0CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
413#define FIO1CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
414#define FIO2CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
415#define FIO3CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
416#define FIO4CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
417
418#define FIO0CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
419#define FIO1CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
420#define FIO2CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
421#define FIO3CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
422#define FIO4CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
423
424#define FIO0CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
425#define FIO1CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
426#define FIO2CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
427#define FIO3CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
428#define FIO4CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
429
430#ifdef ARM_MULTILIB_ARCH_V4
431
432/* System Control Block(SCB) modules include Memory Accelerator Module,
433Phase Locked Loop, VPB divider, Power Control, External Interrupt,
434Reset, and Code Security/Debugging */
435#define SCB_BASE_ADDR   0xE01FC000
436
437/* Memory Accelerator Module (MAM) */
438#define MAMCR          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000))
439#define MAMTIM         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004))
440#define MEMMAP         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040))
441
442/* Phase Locked Loop (PLL) */
443#define PLLCON         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080))
444#define PLLCFG         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084))
445#define PLLSTAT        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088))
446#define PLLFEED        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C))
447
448/* Power Control */
449#define PCON           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0))
450#define PCONP          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4))
451
452/* Clock Divider */
453// #define APBDIV         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100))
454#define CCLKCFG        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104))
455#define USBCLKCFG      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108))
456#define CLKSRCSEL      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
457#define PCLKSEL0       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
458#define PCLKSEL1       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
459
460/* External Interrupts */
461#define EXTINT         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
462#define INTWAKE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
463#define EXTMODE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148))
464#define EXTPOLAR       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C))
465
466/* Reset, reset source identification */
467#define RSIR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180))
468
469/* RSID, code security protection */
470#define CSPR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184))
471
472/* AHB configuration */
473#define AHBCFG1        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188))
474#define AHBCFG2        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
475
476/* System Controls and Status */
477#define SCS            (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
478
479#endif /* ARM_MULTILIB_ARCH_V4 */
480
481/* External Memory Controller (EMC) */
482#ifdef ARM_MULTILIB_ARCH_V4
483  #define EMC_BASE_ADDR         0xFFE08000
484#else
485  #define EMC_BASE_ADDR         0x2009c000
486#endif
487#define EMC_CTRL       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
488#define EMC_STAT       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
489#define EMC_CONFIG     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
490
491/* Dynamic RAM access registers */
492#define EMC_DYN_CTRL     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020))
493#define EMC_DYN_RFSH     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024))
494#define EMC_DYN_RD_CFG   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028))
495#define EMC_DYN_RP       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030))
496#define EMC_DYN_RAS      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034))
497#define EMC_DYN_SREX     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038))
498#define EMC_DYN_APR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C))
499#define EMC_DYN_DAL      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040))
500#define EMC_DYN_WR       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044))
501#define EMC_DYN_RC       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048))
502#define EMC_DYN_RFC      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C))
503#define EMC_DYN_XSR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050))
504#define EMC_DYN_RRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054))
505#define EMC_DYN_MRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058))
506
507#define EMC_DYN_CFG0     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100))
508#define EMC_DYN_RASCAS0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104))
509#define EMC_DYN_CFG1     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140))
510#define EMC_DYN_RASCAS1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144))
511#define EMC_DYN_CFG2     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160))
512#define EMC_DYN_RASCAS2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164))
513#define EMC_DYN_CFG3     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180))
514#define EMC_DYN_RASCAS3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184))
515
516/* static RAM access registers */
517#define EMC_STA_BASE_0    ((uint32_t *) (EMC_BASE_ADDR + 0x200))
518#define EMC_STA_CFG0      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
519#define EMC_STA_WAITWEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
520#define EMC_STA_WAITOEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208))
521#define EMC_STA_WAITRD0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C))
522#define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210))
523#define EMC_STA_WAITWR0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214))
524#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
525
526#define EMC_STA_BASE_1    ((uint32_t *) (EMC_BASE_ADDR + 0x220))
527#define EMC_STA_CFG1      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
528#define EMC_STA_WAITWEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
529#define EMC_STA_WAITOEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228))
530#define EMC_STA_WAITRD1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C))
531#define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230))
532#define EMC_STA_WAITWR1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234))
533#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
534
535#define EMC_STA_BASE_2    ((uint32_t *) (EMC_BASE_ADDR + 0x240))
536#define EMC_STA_CFG2      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
537#define EMC_STA_WAITWEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
538#define EMC_STA_WAITOEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248))
539#define EMC_STA_WAITRD2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C))
540#define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250))
541#define EMC_STA_WAITWR2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254))
542#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
543
544#define EMC_STA_BASE_3    ((uint32_t *) (EMC_BASE_ADDR + 0x260))
545#define EMC_STA_CFG3      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
546#define EMC_STA_WAITWEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
547#define EMC_STA_WAITOEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268))
548#define EMC_STA_WAITRD3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C))
549#define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270))
550#define EMC_STA_WAITWR3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274))
551#define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278))
552
553#define EMC_STA_EXT_WAIT  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
554
555
556/* Timer 0 */
557#ifdef ARM_MULTILIB_ARCH_V4
558  #define TMR0_BASE_ADDR                0xE0004000
559#else
560  #define TMR0_BASE_ADDR                0x40004000
561#endif
562#define T0IR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
563#define T0TCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
564#define T0TC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
565#define T0PR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C))
566#define T0PC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10))
567#define T0MCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14))
568#define T0MR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18))
569#define T0MR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C))
570#define T0MR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20))
571#define T0MR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24))
572#define T0CCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28))
573#define T0CR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C))
574#define T0CR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30))
575#define T0CR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34))
576#define T0CR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38))
577#define T0EMR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C))
578#define T0CTCR         (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
579
580/* Timer 1 */
581#ifdef ARM_MULTILIB_ARCH_V4
582  #define TMR1_BASE_ADDR                0xE0008000
583#else
584  #define TMR1_BASE_ADDR                0x40008000
585#endif
586#define T1IR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
587#define T1TCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
588#define T1TC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
589#define T1PR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C))
590#define T1PC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10))
591#define T1MCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14))
592#define T1MR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18))
593#define T1MR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C))
594#define T1MR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20))
595#define T1MR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24))
596#define T1CCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28))
597#define T1CR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C))
598#define T1CR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30))
599#define T1CR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34))
600#define T1CR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38))
601#define T1EMR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C))
602#define T1CTCR         (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
603
604/* Timer 2 */
605#ifdef ARM_MULTILIB_ARCH_V4
606  #define TMR2_BASE_ADDR                0xE0070000
607#else
608  #define TMR2_BASE_ADDR                0x40090000
609#endif
610#define T2IR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
611#define T2TCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
612#define T2TC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
613#define T2PR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C))
614#define T2PC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10))
615#define T2MCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14))
616#define T2MR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18))
617#define T2MR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C))
618#define T2MR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20))
619#define T2MR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24))
620#define T2CCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28))
621#define T2CR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C))
622#define T2CR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30))
623#define T2CR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34))
624#define T2CR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38))
625#define T2EMR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C))
626#define T2CTCR         (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
627
628/* Timer 3 */
629#ifdef ARM_MULTILIB_ARCH_V4
630  #define TMR3_BASE_ADDR                0xE0074000
631#else
632  #define TMR3_BASE_ADDR                0x40094000
633#endif
634#define T3IR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
635#define T3TCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
636#define T3TC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
637#define T3PR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C))
638#define T3PC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10))
639#define T3MCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14))
640#define T3MR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18))
641#define T3MR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C))
642#define T3MR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20))
643#define T3MR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24))
644#define T3CCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28))
645#define T3CR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C))
646#define T3CR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30))
647#define T3CR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34))
648#define T3CR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38))
649#define T3EMR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C))
650#define T3CTCR         (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70))
651
652
653/* Pulse Width Modulator (PWM) */
654#ifdef ARM_MULTILIB_ARCH_V4
655  #define PWM0_BASE_ADDR                0xE0014000
656#else
657  #define PWM0_BASE_ADDR                0x40014000
658#endif
659#define PWM0IR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
660#define PWM0TCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
661#define PWM0TC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
662#define PWM0PR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C))
663#define PWM0PC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10))
664#define PWM0MCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14))
665#define PWM0MR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18))
666#define PWM0MR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C))
667#define PWM0MR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20))
668#define PWM0MR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24))
669#define PWM0CCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28))
670#define PWM0CR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C))
671#define PWM0CR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30))
672#define PWM0CR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34))
673#define PWM0CR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38))
674#define PWM0EMR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C))
675#define PWM0MR4         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40))
676#define PWM0MR5         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44))
677#define PWM0MR6         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48))
678#define PWM0PCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C))
679#define PWM0LER         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
680#define PWM0CTCR        (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
681
682#ifdef ARM_MULTILIB_ARCH_V4
683  #define PWM1_BASE_ADDR                0xE0018000
684#else
685  #define PWM1_BASE_ADDR                0x40018000
686#endif
687#define PWM1IR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
688#define PWM1TCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
689#define PWM1TC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
690#define PWM1PR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C))
691#define PWM1PC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10))
692#define PWM1MCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14))
693#define PWM1MR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18))
694#define PWM1MR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C))
695#define PWM1MR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20))
696#define PWM1MR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24))
697#define PWM1CCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28))
698#define PWM1CR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C))
699#define PWM1CR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30))
700#define PWM1CR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34))
701#define PWM1CR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38))
702#define PWM1EMR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C))
703#define PWM1MR4         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40))
704#define PWM1MR5         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44))
705#define PWM1MR6         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48))
706#define PWM1PCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C))
707#define PWM1LER         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50))
708#define PWM1CTCR        (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70))
709
710
711/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
712#ifdef ARM_MULTILIB_ARCH_V4
713  #define UART0_BASE_ADDR               0xE000C000
714#else
715  #define UART0_BASE_ADDR               0x4000C000
716#endif
717#define U0RBR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
718#define U0THR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
719#define U0DLL          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
720#define U0DLM          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
721#define U0IER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
722#define U0IIR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
723#define U0FCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
724#define U0LCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C))
725#define U0LSR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14))
726#define U0SCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C))
727#define U0ACR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20))
728#define U0ICR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24))
729#define U0FDR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28))
730#define U0TER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
731
732/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
733#ifdef ARM_MULTILIB_ARCH_V4
734  #define UART1_BASE_ADDR               0xE0010000
735#else
736  #define UART1_BASE_ADDR               0x40010000
737#endif
738#define U1RBR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
739#define U1THR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
740#define U1DLL          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
741#define U1DLM          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
742#define U1IER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
743#define U1IIR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
744#define U1FCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
745#define U1LCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C))
746#define U1MCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10))
747#define U1LSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14))
748#define U1MSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18))
749#define U1SCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C))
750#define U1ACR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20))
751#define U1FDR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28))
752#define U1TER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
753
754/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
755#ifdef ARM_MULTILIB_ARCH_V4
756  #define UART2_BASE_ADDR               0xE0078000
757#else
758  #define UART2_BASE_ADDR               0x40098000
759#endif
760#define U2RBR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
761#define U2THR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
762#define U2DLL          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
763#define U2DLM          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
764#define U2IER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
765#define U2IIR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
766#define U2FCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
767#define U2LCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C))
768#define U2LSR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14))
769#define U2SCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C))
770#define U2ACR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20))
771#define U2ICR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24))
772#define U2FDR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28))
773#define U2TER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
774
775/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
776#ifdef ARM_MULTILIB_ARCH_V4
777  #define UART3_BASE_ADDR               0xE007C000
778#else
779  #define UART3_BASE_ADDR               0x4009C000
780#endif
781#define U3RBR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
782#define U3THR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
783#define U3DLL          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
784#define U3DLM          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
785#define U3IER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
786#define U3IIR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
787#define U3FCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
788#define U3LCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C))
789#define U3LSR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14))
790#define U3SCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C))
791#define U3ACR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20))
792#define U3ICR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24))
793#define U3FDR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28))
794#define U3TER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
795
796/* I2C Interface 0 */
797#ifdef ARM_MULTILIB_ARCH_V4
798  #define I2C0_BASE_ADDR                0xE001C000
799#else
800  #define I2C0_BASE_ADDR                0x4001C000
801#endif
802#define I20CONSET      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
803#define I20STAT        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
804#define I20DAT         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
805#define I20ADR         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C))
806#define I20SCLH        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10))
807#define I20SCLL        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14))
808#define I20CONCLR      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
809
810/* I2C Interface 1 */
811#ifdef ARM_MULTILIB_ARCH_V4
812  #define I2C1_BASE_ADDR                0xE005C000
813#else
814  #define I2C1_BASE_ADDR                0x4005C000
815#endif
816#define I21CONSET      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
817#define I21STAT        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
818#define I21DAT         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
819#define I21ADR         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C))
820#define I21SCLH        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10))
821#define I21SCLL        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14))
822#define I21CONCLR      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
823
824/* I2C Interface 2 */
825#ifdef ARM_MULTILIB_ARCH_V4
826  #define I2C2_BASE_ADDR                0xE0080000
827#else
828  #define I2C2_BASE_ADDR                0x400a0000
829#endif
830#define I22CONSET      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
831#define I22STAT        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
832#define I22DAT         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
833#define I22ADR         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C))
834#define I22SCLH        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10))
835#define I22SCLL        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14))
836#define I22CONCLR      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18))
837
838/* SPI0 (Serial Peripheral Interface 0) */
839#define SPI0_BASE_ADDR          0xE0020000
840#define S0SPCR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00))
841#define S0SPSR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04))
842#define S0SPDR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08))
843#define S0SPCCR        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C))
844#define S0SPINT        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
845
846/* SSP0 Controller */
847#ifdef ARM_MULTILIB_ARCH_V4
848  #define SSP0_BASE_ADDR                0xE0068000
849#else
850  #define SSP0_BASE_ADDR                0x40088000
851#endif
852#define SSP0CR0        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
853#define SSP0CR1        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
854#define SSP0DR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
855#define SSP0SR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C))
856#define SSP0CPSR       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10))
857#define SSP0IMSC       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14))
858#define SSP0RIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18))
859#define SSP0MIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C))
860#define SSP0ICR        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20))
861#define SSP0DMACR      (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
862
863/* SSP1 Controller */
864#ifdef ARM_MULTILIB_ARCH_V4
865  #define SSP1_BASE_ADDR                0xE0030000
866#else
867  #define SSP1_BASE_ADDR                0x40030000
868#endif
869#define SSP1CR0        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
870#define SSP1CR1        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
871#define SSP1DR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
872#define SSP1SR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C))
873#define SSP1CPSR       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10))
874#define SSP1IMSC       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14))
875#define SSP1RIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18))
876#define SSP1MIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C))
877#define SSP1ICR        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
878#define SSP1DMACR      (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
879
880#ifdef ARM_MULTILIB_ARCH_V7M
881
882/* SSP2 Controller */
883#define SSP2_BASE_ADDR          0x400ac000
884#define SSP2CR0        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00))
885#define SSP2CR1        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04))
886#define SSP2DR         (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08))
887#define SSP2SR         (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C))
888#define SSP2CPSR       (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10))
889#define SSP2IMSC       (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14))
890#define SSP2RIS        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18))
891#define SSP2MIS        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C))
892#define SSP2ICR        (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20))
893#define SSP2DMACR      (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24))
894
895#endif /* ARM_MULTILIB_ARCH_V4 */
896
897/* Real Time Clock */
898#ifdef ARM_MULTILIB_ARCH_V4
899  #define RTC_BASE_ADDR         0xE0024000
900#else
901  #define RTC_BASE_ADDR         0x40024000
902#endif
903#define RTC_ILR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
904#define RTC_CTC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
905#define RTC_CCR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
906#define RTC_CIIR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C))
907#define RTC_AMR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10))
908#define RTC_CTIME0      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14))
909#define RTC_CTIME1      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18))
910#define RTC_CTIME2      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C))
911#define RTC_SEC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20))
912#define RTC_MIN         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24))
913#define RTC_HOUR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28))
914#define RTC_DOM         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C))
915#define RTC_DOW         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30))
916#define RTC_DOY         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34))
917#define RTC_MONTH       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38))
918#define RTC_YEAR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C))
919#define RTC_CISS        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40))
920#define RTC_ALSEC       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60))
921#define RTC_ALMIN       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64))
922#define RTC_ALHOUR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68))
923#define RTC_ALDOM       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C))
924#define RTC_ALDOW       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70))
925#define RTC_ALDOY       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74))
926#define RTC_ALMON       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78))
927#define RTC_ALYEAR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C))
928#define RTC_PREINT      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80))
929#define RTC_PREFRAC     (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84))
930
931
932/* A/D Converter 0 (AD0) */
933#ifdef ARM_MULTILIB_ARCH_V4
934  #define AD0_BASE_ADDR         0xE0034000
935#else
936  #define AD0_BASE_ADDR         0x40034000
937#endif
938#define AD0CR          (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
939#define AD0GDR         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
940#define AD0INTEN       (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
941#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
942#define AD0DR0         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
943#define AD0DR1         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
944#define AD0DR2         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18))
945#define AD0DR3         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C))
946#define AD0DR4         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20))
947#define AD0DR5         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24))
948#define AD0DR6         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28))
949#define AD0DR7         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C))
950#define AD0STAT        (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30))
951
952
953/* D/A Converter */
954#ifdef ARM_MULTILIB_ARCH_V4
955  #define DAC_BASE_ADDR         0xE006C000
956#else
957  #define DAC_BASE_ADDR         0x4008C000
958#endif
959#define DACR           (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
960
961
962/* Watchdog */
963#ifdef ARM_MULTILIB_ARCH_V4
964  #define WDG_BASE_ADDR         0xE0000000
965#else
966  #define WDG_BASE_ADDR         0x40000000
967#endif
968#define WDMOD          (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
969#define WDTC           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
970#define WDFEED         (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
971#define WDTV           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C))
972#define WDCLKSEL       (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
973
974/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
975#ifdef ARM_MULTILIB_ARCH_V4
976  #define CAN_ACCEPT_BASE_ADDR          0xE003C000
977#else
978  #define CAN_ACCEPT_BASE_ADDR          0x4003C000
979#endif
980#define CAN_AFMR                (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
981#define CAN_SFF_SA              (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
982#define CAN_SFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
983#define CAN_EFF_SA              (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
984#define CAN_EFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
985#define CAN_EOT                 (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
986#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
987#define CAN_LUT_ERR     (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
988
989#ifdef ARM_MULTILIB_ARCH_V4
990  #define CAN_CENTRAL_BASE_ADDR         0xE0040000
991#else
992  #define CAN_CENTRAL_BASE_ADDR         0x40040000
993#endif
994#define CAN_TX_SR       (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
995#define CAN_RX_SR       (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
996#define CAN_MSR         (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
997
998#ifdef ARM_MULTILIB_ARCH_V4
999  #define CAN1_BASE_ADDR                0xE0044000
1000#else
1001  #define CAN1_BASE_ADDR                0x40044000
1002#endif
1003#define CAN1MOD         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
1004#define CAN1CMR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
1005#define CAN1GSR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
1006#define CAN1ICR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
1007#define CAN1IER         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
1008#define CAN1BTR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
1009#define CAN1EWL         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
1010#define CAN1SR          (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
1011#define CAN1RFS         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
1012#define CAN1RID         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
1013#define CAN1RDA         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
1014#define CAN1RDB         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
1015
1016#define CAN1TFI1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
1017#define CAN1TID1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
1018#define CAN1TDA1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
1019#define CAN1TDB1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
1020#define CAN1TFI2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
1021#define CAN1TID2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
1022#define CAN1TDA2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
1023#define CAN1TDB2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
1024#define CAN1TFI3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
1025#define CAN1TID3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
1026#define CAN1TDA3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
1027#define CAN1TDB3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
1028
1029#ifdef ARM_MULTILIB_ARCH_V4
1030  #define CAN2_BASE_ADDR                0xE0048000
1031#else
1032  #define CAN2_BASE_ADDR                0x40048000
1033#endif
1034#define CAN2MOD         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
1035#define CAN2CMR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
1036#define CAN2GSR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
1037#define CAN2ICR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
1038#define CAN2IER         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
1039#define CAN2BTR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
1040#define CAN2EWL         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
1041#define CAN2SR          (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
1042#define CAN2RFS         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
1043#define CAN2RID         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
1044#define CAN2RDA         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
1045#define CAN2RDB         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
1046
1047#define CAN2TFI1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
1048#define CAN2TID1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
1049#define CAN2TDA1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
1050#define CAN2TDB1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
1051#define CAN2TFI2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
1052#define CAN2TID2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
1053#define CAN2TDA2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
1054#define CAN2TDB2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
1055#define CAN2TFI3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
1056#define CAN2TID3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
1057#define CAN2TDA3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
1058#define CAN2TDB3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
1059
1060
1061/* MultiMedia Card Interface(MCI) Controller */
1062#ifdef ARM_MULTILIB_ARCH_V4
1063  #define MCI_BASE_ADDR         0xE008C000
1064#else
1065  #define MCI_BASE_ADDR         0x400c0000
1066#endif
1067#define MCI_POWER      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
1068#define MCI_CLOCK      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
1069#define MCI_ARGUMENT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
1070#define MCI_COMMAND    (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C))
1071#define MCI_RESP_CMD   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10))
1072#define MCI_RESP0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14))
1073#define MCI_RESP1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18))
1074#define MCI_RESP2      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C))
1075#define MCI_RESP3      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20))
1076#define MCI_DATA_TMR   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24))
1077#define MCI_DATA_LEN   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28))
1078#define MCI_DATA_CTRL  (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C))
1079#define MCI_DATA_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30))
1080#define MCI_STATUS     (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34))
1081#define MCI_CLEAR      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38))
1082#define MCI_MASK0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C))
1083#define MCI_MASK1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40))
1084#define MCI_FIFO_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48))
1085#define MCI_FIFO       (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80))
1086
1087
1088/* I2S Interface Controller (I2S) */
1089#ifdef ARM_MULTILIB_ARCH_V4
1090  #define I2S_BASE_ADDR         0xE0088000
1091#else
1092  #define I2S_BASE_ADDR         0x400a8000
1093#endif
1094#define I2S_DAO        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
1095#define I2S_DAI        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
1096#define I2S_TX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
1097#define I2S_RX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C))
1098#define I2S_STATE      (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10))
1099#define I2S_DMA1       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14))
1100#define I2S_DMA2       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18))
1101#define I2S_IRQ        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C))
1102#define I2S_TXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20))
1103#define I2S_RXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24))
1104
1105
1106/* General-purpose DMA Controller */
1107#ifdef ARM_MULTILIB_ARCH_V4
1108  #define DMA_BASE_ADDR         0xFFE04000
1109#else
1110  #define DMA_BASE_ADDR         0x20080000
1111#endif
1112#define GPDMA_INT_STAT         (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
1113#define GPDMA_INT_TCSTAT       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
1114#define GPDMA_INT_TCCLR        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
1115#define GPDMA_INT_ERR_STAT     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C))
1116#define GPDMA_INT_ERR_CLR      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010))
1117#define GPDMA_RAW_INT_TCSTAT   (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014))
1118#define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018))
1119#define GPDMA_ENABLED_CHNS     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C))
1120#define GPDMA_SOFT_BREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020))
1121#define GPDMA_SOFT_SREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024))
1122#define GPDMA_SOFT_LBREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028))
1123#define GPDMA_SOFT_LSREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C))
1124#define GPDMA_CONFIG           (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030))
1125#define GPDMA_SYNC             (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
1126
1127/* DMA channel 0 registers */
1128#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
1129#define GPDMA_CH0_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
1130#define GPDMA_CH0_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
1131#define GPDMA_CH0_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
1132#define GPDMA_CH0_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C))
1133#define GPDMA_CH0_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
1134
1135/* DMA channel 1 registers */
1136#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
1137#define GPDMA_CH1_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
1138#define GPDMA_CH1_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
1139#define GPDMA_CH1_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
1140#define GPDMA_CH1_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
1141#define GPDMA_CH1_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
1142
1143/* USB Controller */
1144#ifdef ARM_MULTILIB_ARCH_V4
1145  #define USB_INT_BASE_ADDR     0xE01FC1C0
1146  #define USB_BASE_ADDR         0xFFE0C200              /* USB Base Address */
1147#else
1148  #define USB_INT_BASE_ADDR     0x400fc1c0
1149  #define USB_BASE_ADDR         0x2008c200
1150#endif
1151
1152#define USB_INT_STAT    (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
1153
1154/* USB Device Interrupt Registers */
1155#define DEV_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00))
1156#define DEV_INT_EN      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04))
1157#define DEV_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08))
1158#define DEV_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C))
1159#define DEV_INT_PRIO    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C))
1160
1161/* USB Device Endpoint Interrupt Registers */
1162#define EP_INT_STAT     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30))
1163#define EP_INT_EN       (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34))
1164#define EP_INT_CLR      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38))
1165#define EP_INT_SET      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C))
1166#define EP_INT_PRIO     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40))
1167
1168/* USB Device Endpoint Realization Registers */
1169#define REALIZE_EP      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44))
1170#define EP_INDEX        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48))
1171#define MAXPACKET_SIZE  (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C))
1172
1173/* USB Device Command Reagisters */
1174#define CMD_CODE        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10))
1175#define CMD_DATA        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14))
1176
1177/* USB Device Data Transfer Registers */
1178#define RX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18))
1179#define TX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C))
1180#define RX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20))
1181#define TX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24))
1182#define USB_CTRL        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28))
1183
1184/* USB Device DMA Registers */
1185#define DMA_REQ_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50))
1186#define DMA_REQ_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54))
1187#define DMA_REQ_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58))
1188#define UDCA_HEAD           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80))
1189#define EP_DMA_STAT         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84))
1190#define EP_DMA_EN           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88))
1191#define EP_DMA_DIS          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C))
1192#define DMA_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90))
1193#define DMA_INT_EN          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94))
1194#define EOT_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0))
1195#define EOT_INT_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4))
1196#define EOT_INT_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8))
1197#define NDD_REQ_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC))
1198#define NDD_REQ_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0))
1199#define NDD_REQ_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4))
1200#define SYS_ERR_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8))
1201#define SYS_ERR_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
1202#define SYS_ERR_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
1203
1204/* USB Host Controller */
1205#ifdef ARM_MULTILIB_ARCH_V4
1206  #define USBHC_BASE_ADDR               0xFFE0C000
1207#else
1208  #define USBHC_BASE_ADDR               0x2008c000
1209#endif
1210#define HC_REVISION         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
1211#define HC_CONTROL          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
1212#define HC_CMD_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
1213#define HC_INT_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C))
1214#define HC_INT_EN           (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10))
1215#define HC_INT_DIS          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14))
1216#define HC_HCCA             (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18))
1217#define HC_PERIOD_CUR_ED    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C))
1218#define HC_CTRL_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20))
1219#define HC_CTRL_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24))
1220#define HC_BULK_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28))
1221#define HC_BULK_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C))
1222#define HC_DONE_HEAD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30))
1223#define HC_FM_INTERVAL      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34))
1224#define HC_FM_REMAINING     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38))
1225#define HC_FM_NUMBER        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C))
1226#define HC_PERIOD_START     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40))
1227#define HC_LS_THRHLD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44))
1228#define HC_RH_DESCA         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48))
1229#define HC_RH_DESCB         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C))
1230#define HC_RH_STAT          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50))
1231#define HC_RH_PORT_STAT1    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54))
1232#define HC_RH_PORT_STAT2    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
1233
1234/* USB OTG Controller */
1235#ifdef ARM_MULTILIB_ARCH_V4
1236  #define USBOTG_BASE_ADDR      0xFFE0C100
1237#else
1238  #define USBOTG_BASE_ADDR      0x2008c100
1239#endif
1240#define OTG_INT_STAT        (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
1241#define OTG_INT_EN          (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
1242#define OTG_INT_SET         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
1243#define OTG_INT_CLR         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C))
1244#define OTG_STAT_CTRL       (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
1245#define OTG_TIMER           (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
1246
1247#ifdef ARM_MULTILIB_ARCH_V4
1248  #define USBOTG_I2C_BASE_ADDR  0xFFE0C300
1249#else
1250  #define USBOTG_I2C_BASE_ADDR  0x2008c300
1251#endif
1252#define OTG_I2C_RX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1253#define OTG_I2C_TX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1254#define OTG_I2C_STS         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
1255#define OTG_I2C_CTL         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08))
1256#define OTG_I2C_CLKHI       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
1257#define OTG_I2C_CLKLO       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
1258
1259#ifdef ARM_MULTILIB_ARCH_V4
1260  #define USBOTG_CLK_BASE_ADDR  0xFFE0CFF0
1261#else
1262  #define USBOTG_CLK_BASE_ADDR  0x2008cff0
1263#endif
1264#define OTG_CLK_CTRL        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
1265#define OTG_CLK_STAT        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
1266
1267/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1268#ifdef ARM_MULTILIB_ARCH_V4
1269  #define MAC_BASE_ADDR         0xFFE00000 /* AHB Peripheral # 0 */
1270#else
1271  #define MAC_BASE_ADDR         0x20084000
1272#endif
1273#define MAC_MAC1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1274#define MAC_MAC2            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1275#define MAC_IPGT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1276#define MAC_IPGR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1277#define MAC_CLRT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1278#define MAC_MAXF            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1279#define MAC_SUPP            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1280#define MAC_TEST            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1281#define MAC_MCFG            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1282#define MAC_MCMD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1283#define MAC_MADR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1284#define MAC_MWTD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1285#define MAC_MRDD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1286#define MAC_MIND            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1287
1288#define MAC_SA0             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1289#define MAC_SA1             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1290#define MAC_SA2             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1291
1292#define MAC_COMMAND         (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */
1293#define MAC_STATUS          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1294#define MAC_RXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1295#define MAC_RXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1296#define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1297#define MAC_RXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1298#define MAC_RXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1299#define MAC_TXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1300#define MAC_TXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1301#define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1302#define MAC_TXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1303#define MAC_TXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1304
1305#define MAC_TSV0            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1306#define MAC_TSV1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1307#define MAC_RSV             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1308
1309#define MAC_FLOWCONTROLCNT  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1310#define MAC_FLOWCONTROLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1311
1312#define MAC_RXFILTERCTRL    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1313#define MAC_RXFILTERWOLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1314#define MAC_RXFILTERWOLCLR  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1315
1316#define MAC_HASHFILTERL     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1317#define MAC_HASHFILTERH     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1318
1319#define MAC_INTSTATUS       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1320#define MAC_INTENABLE       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
1321#define MAC_INTCLEAR        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1322#define MAC_INTSET          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1323
1324#define MAC_POWERDOWN       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1325#define MAC_MODULEID        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1326
1327/* LCD Controller */
1328
1329#ifdef ARM_MULTILIB_ARCH_V4
1330  #define LCD_CFG     (*(volatile uint32_t *) 0xE01FC1B8)
1331  #define LCD_BASE_ADDR 0xFFE10000
1332#else
1333  #define LCD_CFG     (*(volatile uint32_t *) 0x400FC1B8)
1334  #define LCD_BASE_ADDR 0x20088000
1335#endif
1336#define LCD_TIMH      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
1337#define LCD_TIMV      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
1338#define LCD_POL       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008))
1339#define LCD_LE        (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C))
1340#define LCD_UPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010))
1341#define LCD_LPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014))
1342#define LCD_CTRL      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018))
1343#define LCD_INTMSK    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C))
1344#define LCD_INTRAW    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020))
1345#define LCD_INTSTAT   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024))
1346#define LCD_INTCLR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028))
1347#define LCD_UPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C))
1348#define LCD_LPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030))
1349#define LCD_PAL_ADDR  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200))
1350#define CRSR_IMG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800))
1351#define CRSR_CTLR     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00))
1352#define CRSR_CFG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04))
1353#define CRSR_PAL0     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08))
1354#define CRSR_PAL1     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C))
1355#define CRSR_XY       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10))
1356#define CRSR_CLIP     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14))
1357#define CRSR_INTMSK   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20))
1358#define CRSR_INTCLR   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24))
1359#define CRSR_INTRAW   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28))
1360#define CRSR_INTSTAT  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C))
1361
1362/* Register Fields */
1363
1364#define GET_FIELD( val, mask, shift) \
1365  (((val) & (mask)) >> (shift))
1366
1367#define SET_FIELD( val, field, mask, shift) \
1368  (((val) & ~(mask)) | (((field) << (shift)) & (mask)))
1369
1370/* CLKSRCSEL */
1371
1372#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1373
1374#define GET_CLKSRCSEL_CLKSRC(reg) \
1375  GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
1376
1377#define SET_CLKSRCSEL_CLKSRC(reg, val) \
1378  SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1379
1380/* PLLCON */
1381
1382#define PLLCON_PLLE 0x00000001U
1383
1384#define PLLCON_PLLC 0x00000002U
1385
1386/* PLLCFG */
1387
1388#define PLLCFG_MSEL_MASK 0x00007fffU
1389
1390#define GET_PLLCFG_MSEL(reg) \
1391  GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
1392
1393#define SET_PLLCFG_MSEL(reg, val) \
1394  SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
1395
1396#define PLLCFG_NSEL_MASK 0x00ff0000U
1397
1398#define GET_PLLCFG_NSEL(reg) \
1399  GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
1400
1401#define SET_PLLCFG_NSEL(reg, val) \
1402  SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
1403
1404/* PLLSTAT */
1405
1406#define PLLSTAT_MSEL_MASK 0x00007fffU
1407
1408#define GET_PLLSTAT_MSEL(reg) \
1409  GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
1410
1411#define SET_PLLSTAT_MSEL(reg, val) \
1412  SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
1413
1414#define PLLSTAT_NSEL_MASK 0x00ff0000U
1415
1416#define GET_PLLSTAT_NSEL(reg) \
1417  GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
1418
1419#define SET_PLLSTAT_NSEL(reg, val) \
1420  SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
1421
1422#define PLLSTAT_PLLE 0x01000000U
1423
1424#define PLLSTAT_PLLC 0x02000000U
1425
1426#define PLLSTAT_PLOCK 0x04000000U
1427
1428/* CCLKCFG */
1429
1430#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1431
1432#define GET_CCLKCFG_CCLKSEL(reg) \
1433  GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
1434
1435#define SET_CCLKCFG_CCLKSEL(reg, val) \
1436  SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1437
1438/* MEMMAP */
1439
1440#define MEMMAP_MAP_MASK 0x00000003U
1441
1442#define GET_MEMMAP_MAP(reg) \
1443  GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
1444
1445#define SET_MEMMAP_MAP(reg, val) \
1446  SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
1447
1448/* TIR */
1449
1450#define TIR_MR0 0x00000001U
1451
1452#define TIR_MR1 0x00000002U
1453
1454#define TIR_MR2 0x00000004U
1455
1456#define TIR_MR3 0x00000008U
1457
1458#define TIR_CR0 0x00000010U
1459
1460#define TIR_CR1 0x00000020U
1461
1462#define TIR_CR2 0x00000040U
1463
1464#define TIR_CR3 0x00000080U
1465
1466/* TCR */
1467
1468#define TCR_EN 0x00000001U
1469
1470#define TCR_RST 0x00000002U
1471
1472/* TMCR */
1473
1474#define TMCR_MR0I 0x00000001U
1475
1476#define TMCR_MR0R 0x00000002U
1477
1478#define TMCR_MR0S 0x00000004U
1479
1480#define TMCR_MR1I 0x00000008U
1481
1482#define TMCR_MR1R 0x00000010U
1483
1484#define TMCR_MR1S 0x00000020U
1485
1486#define TMCR_MR2I 0x00000040U
1487
1488#define TMCR_MR2R 0x00000080U
1489
1490#define TMCR_MR2S 0x00000100U
1491
1492#define TMCR_MR3I 0x00000200U
1493
1494#define TMCR_MR3R 0x00000400U
1495
1496#define TMCR_MR3S 0x00000800U
1497
1498/* PCLKSEL0 */
1499
1500#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1501
1502#define GET_PCLKSEL0_PCLK_WDT(reg) \
1503  GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1504
1505#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
1506  SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1507
1508#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1509
1510#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
1511  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1512
1513#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
1514  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1515
1516#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1517
1518#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
1519  GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1520
1521#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
1522  SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1523
1524#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1525
1526#define GET_PCLKSEL0_PCLK_UART0(reg) \
1527  GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1528
1529#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
1530  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1531
1532#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1533
1534#define GET_PCLKSEL0_PCLK_UART1(reg) \
1535  GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1536
1537#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
1538  SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1539
1540#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1541
1542#define GET_PCLKSEL0_PCLK_PWM0(reg) \
1543  GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1544
1545#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
1546  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1547
1548#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1549
1550#define GET_PCLKSEL0_PCLK_PWM1(reg) \
1551  GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1552
1553#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
1554  SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1555
1556#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1557
1558#define GET_PCLKSEL0_PCLK_I2C0(reg) \
1559  GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1560
1561#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
1562  SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1563
1564#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1565
1566#define GET_PCLKSEL0_PCLK_SPI(reg) \
1567  GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1568
1569#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
1570  SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1571
1572#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1573
1574#define GET_PCLKSEL0_PCLK_RTC(reg) \
1575  GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1576
1577#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
1578  SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1579
1580#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1581
1582#define GET_PCLKSEL0_PCLK_SSP1(reg) \
1583  GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1584
1585#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
1586  SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1587
1588#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1589
1590#define GET_PCLKSEL0_PCLK_DAC(reg) \
1591  GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1592
1593#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
1594  SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1595
1596#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1597
1598#define GET_PCLKSEL0_PCLK_ADC(reg) \
1599  GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1600
1601#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
1602  SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1603
1604#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1605
1606#define GET_PCLKSEL0_PCLK_CAN1(reg) \
1607  GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1608
1609#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
1610  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1611
1612#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1613
1614#define GET_PCLKSEL0_PCLK_CAN2(reg) \
1615  GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1616
1617#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
1618  SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1619
1620/* PCLKSEL1 */
1621
1622#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1623
1624#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
1625  GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1626
1627#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
1628  SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1629
1630#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1631
1632#define GET_PCLKSEL1_PCLK_GPIO(reg) \
1633  GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1634
1635#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
1636  SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1637
1638#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1639
1640#define GET_PCLKSEL1_PCLK_PCB(reg) \
1641  GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1642
1643#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
1644  SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1645
1646#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1647
1648#define GET_PCLKSEL1_PCLK_I2C1(reg) \
1649  GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1650
1651#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
1652  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1653
1654#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1655
1656#define GET_PCLKSEL1_PCLK_SSP0(reg) \
1657  GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1658
1659#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
1660  SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1661
1662#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1663
1664#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
1665  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1666
1667#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
1668  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1669
1670#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1671
1672#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
1673  GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1674
1675#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
1676  SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1677
1678#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1679
1680#define GET_PCLKSEL1_PCLK_UART2(reg) \
1681  GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1682
1683#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
1684  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1685
1686#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1687
1688#define GET_PCLKSEL1_PCLK_UART3(reg) \
1689  GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1690
1691#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
1692  SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1693
1694#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1695
1696#define GET_PCLKSEL1_PCLK_I2C2(reg) \
1697  GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1698
1699#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
1700  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1701
1702#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1703
1704#define GET_PCLKSEL1_PCLK_I2S(reg) \
1705  GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1706
1707#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
1708  SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1709
1710#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1711
1712#define GET_PCLKSEL1_PCLK_MCI(reg) \
1713  GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1714
1715#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
1716  SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1717
1718#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1719
1720#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
1721  GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1722
1723#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
1724  SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1725
1726/* RTC_ILR */
1727
1728#define RTC_ILR_RTCCIF 0x00000001U
1729
1730#define RTC_ILR_RTCALF 0x00000002U
1731
1732#define RTC_ILR_RTSSF 0x00000004U
1733
1734/* RTC_CCR */
1735
1736#define RTC_CCR_CLKEN 0x00000001U
1737
1738#define RTC_CCR_CTCRST 0x00000002U
1739
1740#define RTC_CCR_CLKSRC 0x00000010U
1741
1742/* SSP */
1743
1744typedef struct {
1745  uint32_t cr0;
1746  uint32_t cr1;
1747  uint32_t dr;
1748  uint32_t sr;
1749  uint32_t cpsr;
1750  uint32_t imsc;
1751  uint32_t ris;
1752  uint32_t mis;
1753  uint32_t icr;
1754  uint32_t dmacr;
1755} lpc24xx_ssp;
1756
1757/* SSP_CR0 */
1758
1759#define SSP_CR0_DSS_MASK 0x0000000fU
1760
1761#define GET_SSP_CR0_DSS(reg) \
1762  GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
1763
1764#define SET_SSP_CR0_DSS(reg, val) \
1765  SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
1766
1767#define SSP_CR0_FRF_MASK 0x00000030U
1768
1769#define GET_SSP_CR0_FRF(reg) \
1770  GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
1771
1772#define SET_SSP_CR0_FRF(reg, val) \
1773  SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
1774
1775#define SSP_CR0_CPOL 0x00000040U
1776
1777#define SSP_CR0_CPHA 0x00000080U
1778
1779#define SSP_CR0_SCR_MASK 0x0000ff00U
1780
1781#define GET_SSP_CR0_SCR(reg) \
1782  GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
1783
1784#define SET_SSP_CR0_SCR(reg, val) \
1785  SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
1786
1787/* SSP_CR1 */
1788
1789#define SSP_CR1_LBM 0x00000001U
1790
1791#define SSP_CR1_SSE 0x00000002U
1792
1793#define SSP_CR1_MS 0x00000004U
1794
1795#define SSP_CR1_SOD 0x00000008U
1796
1797/* SSP_SR */
1798
1799#define SSP_SR_TFE 0x00000001U
1800
1801#define SSP_SR_TNF 0x00000002U
1802
1803#define SSP_SR_RNE 0x00000004U
1804
1805#define SSP_SR_RFF 0x00000008U
1806
1807#define SSP_SR_BSY 0x00000010U
1808
1809/* SSP_IMSC */
1810
1811#define SSP_IMSC_RORIM 0x00000001U
1812
1813#define SSP_IMSC_RTIM 0x00000002U
1814
1815#define SSP_IMSC_RXIM 0x00000004U
1816
1817#define SSP_IMSC_TXIM 0x00000008U
1818
1819/* SSP_RIS */
1820
1821#define SSP_RIS_RORRIS 0x00000001U
1822
1823#define SSP_RIS_RTRIS 0x00000002U
1824
1825#define SSP_RIS_RXRIS 0x00000004U
1826
1827#define SSP_RIS_TXRIS 0x00000008U
1828
1829/* SSP_MIS */
1830
1831#define SSP_MIS_RORRIS 0x00000001U
1832
1833#define SSP_MIS_RTRIS 0x00000002U
1834
1835#define SSP_MIS_RXRIS 0x00000004U
1836
1837#define SSP_MIS_TXRIS 0x00000008U
1838
1839/* SSP_ICR */
1840
1841#define SSP_ICR_RORRIS 0x00000001U
1842
1843#define SSP_ICR_RTRIS 0x00000002U
1844
1845#define SSP_ICR_RXRIS 0x00000004U
1846
1847#define SSP_ICR_TXRIS 0x00000008U
1848
1849/* SSP_DMACR */
1850
1851#define SSP_DMACR_RXDMAE 0x00000001U
1852
1853#define SSP_DMACR_TXDMAE 0x00000002U
1854
1855/* GPDMA */
1856
1857typedef struct {
1858  uint32_t src;
1859  uint32_t dest;
1860  uint32_t lli;
1861  uint32_t ctrl;
1862} lpc24xx_dma_descriptor;
1863
1864typedef struct {
1865  lpc24xx_dma_descriptor desc;
1866  uint32_t cfg;
1867} lpc24xx_dma_channel;
1868
1869#define GPDMA_CH_NUMBER 2
1870
1871#define GPDMA_STATUS_CH_0 0x00000001U
1872
1873#define GPDMA_STATUS_CH_1 0x00000002U
1874
1875#define GPDMA_CH_BASE_ADDR(i) \
1876  ((volatile lpc24xx_dma_channel *) \
1877    ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1878
1879/* GPDMA_CONFIG */
1880
1881#define GPDMA_CONFIG_EN 0x00000001U
1882
1883#define GPDMA_CONFIG_MODE 0x00000002U
1884
1885/* GPDMA_ENABLED_CHNS */
1886
1887#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1888
1889#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1890
1891/* GPDMA_CH_CTRL */
1892
1893#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1894
1895#define GET_GPDMA_CH_CTRL_TSZ(reg) \
1896  GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1897
1898#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
1899  SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1900
1901#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1902
1903#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1904
1905#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
1906  GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1907
1908#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
1909  SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1910
1911#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1912
1913#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
1914  GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1915
1916#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
1917  SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1918
1919#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1920
1921#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1922
1923#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1924
1925#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1926
1927#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1928
1929#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1930
1931#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1932
1933#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1934
1935#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1936
1937#define GET_GPDMA_CH_CTRL_SW(reg) \
1938  GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
1939
1940#define SET_GPDMA_CH_CTRL_SW(reg, val) \
1941  SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1942
1943#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1944
1945#define GET_GPDMA_CH_CTRL_DW(reg) \
1946  GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
1947
1948#define SET_GPDMA_CH_CTRL_DW(reg, val) \
1949  SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1950
1951#define GPDMA_CH_CTRL_W_8 0x00000000U
1952
1953#define GPDMA_CH_CTRL_W_16 0x00000001U
1954
1955#define GPDMA_CH_CTRL_W_32 0x00000002U
1956
1957#define GPDMA_CH_CTRL_SI 0x04000000U
1958
1959#define GPDMA_CH_CTRL_DI 0x08000000U
1960
1961#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1962
1963#define GET_GPDMA_CH_CTRL_PROT(reg) \
1964  GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1965
1966#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
1967  SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1968
1969#define GPDMA_CH_CTRL_ITC 0x80000000U
1970
1971/* GPDMA_CH_CFG */
1972
1973#define GPDMA_CH_CFG_EN 0x00000001U
1974
1975#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1976
1977#define GET_GPDMA_CH_CFG_SRCPER(reg) \
1978  GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1979
1980#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
1981  SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1982
1983#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1984
1985#define GET_GPDMA_CH_CFG_DESTPER(reg) \
1986  GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
1987
1988#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
1989  SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
1990
1991#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1992
1993#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1994
1995#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1996
1997#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1998
1999#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
2000
2001#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
2002
2003#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
2004
2005#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
2006
2007#define GET_GPDMA_CH_CFG_FLOW(reg) \
2008  GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
2009
2010#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
2011  SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
2012
2013#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
2014
2015#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
2016
2017#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
2018
2019#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
2020
2021#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
2022
2023#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
2024
2025#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
2026
2027#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
2028
2029#define GPDMA_CH_CFG_IE 0x00004000U
2030
2031#define GPDMA_CH_CFG_ITC 0x00008000U
2032
2033#define GPDMA_CH_CFG_LOCK 0x00010000U
2034
2035#define GPDMA_CH_CFG_ACTIVE 0x00020000U
2036
2037#define GPDMA_CH_CFG_HALT 0x00040000U
2038
2039/* AHBCFG */
2040
2041#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
2042
2043#define AHBCFG_BREAK_BURST_MASK 0x00000006U
2044
2045#define GET_AHBCFG_BREAK_BURST(reg) \
2046  GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
2047
2048#define SET_AHBCFG_BREAK_BURST(reg, val) \
2049  SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
2050
2051#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
2052
2053#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
2054
2055#define GET_AHBCFG_QUANTUM_SIZE(reg) \
2056  GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
2057
2058#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
2059  SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
2060
2061#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
2062
2063#define GET_AHBCFG_DEFAULT_MASTER(reg) \
2064  GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
2065
2066#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
2067  SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
2068
2069#define AHBCFG_EP1_MASK 0x00007000U
2070
2071#define GET_AHBCFG_EP1(reg) \
2072  GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
2073
2074#define SET_AHBCFG_EP1(reg, val) \
2075  SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
2076
2077#define AHBCFG_EP2_MASK 0x00070000U
2078
2079#define GET_AHBCFG_EP2(reg) \
2080  GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
2081
2082#define SET_AHBCFG_EP2(reg, val) \
2083  SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
2084
2085#define AHBCFG_EP3_MASK 0x00700000U
2086
2087#define GET_AHBCFG_EP3(reg) \
2088  GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
2089
2090#define SET_AHBCFG_EP3(reg, val) \
2091  SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
2092
2093#define AHBCFG_EP4_MASK 0x07000000U
2094
2095#define GET_AHBCFG_EP4(reg) \
2096  GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
2097
2098#define SET_AHBCFG_EP4(reg, val) \
2099  SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
2100
2101#define AHBCFG_EP5_MASK 0x70000000U
2102
2103#define GET_AHBCFG_EP5(reg) \
2104  GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
2105
2106#define SET_AHBCFG_EP5(reg, val) \
2107  SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
2108
2109/* I2C */
2110
2111typedef struct {
2112  uint32_t conset;
2113  uint32_t stat;
2114  uint32_t dat;
2115  uint32_t adr;
2116  uint32_t sclh;
2117  uint32_t scll;
2118  uint32_t conclr;
2119} lpc24xx_i2c;
2120
2121#define LPC24XX_I2C_AA (1U << 2U)
2122
2123#define LPC24XX_I2C_SI (1U << 3U)
2124
2125#define LPC24XX_I2C_STO (1U << 4U)
2126
2127#define LPC24XX_I2C_STA (1U << 5U)
2128
2129#define LPC24XX_I2C_EN (1U << 6U)
2130
2131/* IO */
2132
2133#ifdef ARM_MULTILIB_ARCH_V4
2134  #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
2135  #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
2136#else
2137  #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2)
2138  #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2)
2139  #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
2140  #define IOCON_MODE(val) BSP_FLD32(val, 3, 4)
2141  #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4)
2142  #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
2143  #define IOCON_HYS BSP_BIT32(5)
2144  #define IOCON_INV BSP_BIT32(6)
2145  #define IOCON_ADMODE BSP_BIT32(7)
2146  #define IOCON_FILTER BSP_BIT32(8)
2147  #define IOCON_HS BSP_BIT32(8)
2148  #define IOCON_SLEW BSP_BIT32(9)
2149  #define IOCON_HIDRIVE BSP_BIT32(9)
2150  #define IOCON_OD BSP_BIT32(10)
2151  #define IOCON_DACEN BSP_BIT32(16)
2152  #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR)
2153#endif
2154
2155typedef struct {
2156  uint32_t dir;
2157  uint32_t reserved [3];
2158  uint32_t mask;
2159  uint32_t pin;
2160  uint32_t set;
2161  uint32_t clr;
2162} lpc24xx_fio;
2163
2164#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
2165
2166#ifdef ARM_MULTILIB_ARCH_V4
2167
2168/* PCONP */
2169
2170#define PCONP_GPDMA (1U << 29)
2171#define PCONP_ETHERNET (1U << 30)
2172#define PCONP_USB (1U << 31)
2173
2174#endif /* ARM_MULTILIB_ARCH_V4 */
2175
2176/* I2S */
2177
2178static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR;
2179
2180/* ADC */
2181
2182#define ADC_CR_SEL(val) BSP_FLD32(val, 0, 7)
2183#define ADC_CR_SEL_GET(val) BSP_FLD32GET(val, 0, 7)
2184#define ADC_CR_SEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
2185#define ADC_CR_CLKDIV(val) BSP_FLD32(val, 8, 15)
2186#define ADC_CR_CLKDIV_GET(reg) BSP_FLD32GET(reg, 8, 15)
2187#define ADC_CR_CLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
2188#define ADC_CR_BURST BSP_BIT32(16)
2189#define ADC_CR_CLKS(val) BSP_FLD32(val, 17, 19)
2190#define ADC_CR_PDN BSP_BIT32(21)
2191#define ADC_CR_START(val) BSP_FLD32(val, 24, 26)
2192#define ADC_CR_EDGE BSP_BIT32(27)
2193
2194#define ADC_DR_VALUE(reg) BSP_FLD32GET(reg, 6, 15)
2195#define ADC_DR_OVERRUN BSP_BIT32(30)
2196#define ADC_DR_DONE BSP_BIT32(31)
2197
2198/* DAC */
2199
2200#define DAC_STEPS 1024
2201#define DAC_VALUE(val) BSP_FLD32(val, 6, 15)
2202#define DAC_BIAS BSP_BIT32(16)
2203
2204/** @} */
2205
2206#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
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