source: rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h @ 7ae2775

4.104.115
Last change on this file since 7ae2775 was 7ae2775, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 17, 2009 at 1:53:04 PM

ARM bsp maintenance

  • Property mode set to 100644
File size: 90.5 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc24xx
5 *
6 * @brief Register definitions.
7 */
8
9/*
10 * Copyright (c) 2008
11 * Embedded Brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be found in the file
18 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19 */
20
21#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
22#define LIBBSP_ARM_LPC24XX_LPC24XX_H
23
24#include <stdint.h>
25
26#include <bsp/utility.h>
27
28/* Vectored Interrupt Controller (VIC) */
29#define VIC_BASE_ADDR   0xFFFFF000
30#define VICIRQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
31#define VICFIQStatus   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004))
32#define VICRawIntr     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008))
33#define VICIntSelect   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C))
34#define VICIntEnable   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010))
35#define VICIntEnClear  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014))
36#define VICSoftInt     (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018))
37#define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C))
38#define VICProtection  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020))
39#define VICSWPrioMask  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
40
41#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
42#define VICVectAddr0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
43#define VICVectAddr1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
44#define VICVectAddr2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108))
45#define VICVectAddr3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C))
46#define VICVectAddr4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110))
47#define VICVectAddr5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114))
48#define VICVectAddr6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118))
49#define VICVectAddr7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C))
50#define VICVectAddr8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120))
51#define VICVectAddr9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124))
52#define VICVectAddr10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128))
53#define VICVectAddr11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C))
54#define VICVectAddr12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130))
55#define VICVectAddr13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134))
56#define VICVectAddr14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138))
57#define VICVectAddr15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C))
58#define VICVectAddr16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140))
59#define VICVectAddr17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144))
60#define VICVectAddr18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148))
61#define VICVectAddr19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C))
62#define VICVectAddr20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150))
63#define VICVectAddr21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154))
64#define VICVectAddr22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158))
65#define VICVectAddr23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C))
66#define VICVectAddr24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160))
67#define VICVectAddr25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164))
68#define VICVectAddr26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168))
69#define VICVectAddr27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C))
70#define VICVectAddr28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170))
71#define VICVectAddr29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174))
72#define VICVectAddr30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178))
73#define VICVectAddr31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
74
75#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
76#define VICVectPriority0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
77#define VICVectPriority1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
78#define VICVectPriority2   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208))
79#define VICVectPriority3   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C))
80#define VICVectPriority4   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210))
81#define VICVectPriority5   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214))
82#define VICVectPriority6   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218))
83#define VICVectPriority7   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C))
84#define VICVectPriority8   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220))
85#define VICVectPriority9   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224))
86#define VICVectPriority10  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228))
87#define VICVectPriority11  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C))
88#define VICVectPriority12  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230))
89#define VICVectPriority13  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234))
90#define VICVectPriority14  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238))
91#define VICVectPriority15  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C))
92#define VICVectPriority16  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240))
93#define VICVectPriority17  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244))
94#define VICVectPriority18  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248))
95#define VICVectPriority19  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C))
96#define VICVectPriority20  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250))
97#define VICVectPriority21  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254))
98#define VICVectPriority22  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258))
99#define VICVectPriority23  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C))
100#define VICVectPriority24  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260))
101#define VICVectPriority25  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264))
102#define VICVectPriority26  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268))
103#define VICVectPriority27  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C))
104#define VICVectPriority28  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270))
105#define VICVectPriority29  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274))
106#define VICVectPriority30  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278))
107#define VICVectPriority31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C))
108
109#define VICVectAddr    (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
110
111
112/* Pin Connect Block */
113#define PINSEL_BASE_ADDR        0xE002C000
114#define PINSEL0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
115#define PINSEL1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
116#define PINSEL2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
117#define PINSEL3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C))
118#define PINSEL4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10))
119#define PINSEL5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14))
120#define PINSEL6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18))
121#define PINSEL7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C))
122#define PINSEL8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20))
123#define PINSEL9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
124#define PINSEL10       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
125#define PINSEL11       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C))
126
127#define PINMODE0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
128#define PINMODE1        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44))
129#define PINMODE2        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48))
130#define PINMODE3        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C))
131#define PINMODE4        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50))
132#define PINMODE5        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54))
133#define PINMODE6        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58))
134#define PINMODE7        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C))
135#define PINMODE8        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
136#define PINMODE9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
137
138/* General Purpose Input/Output (GPIO) */
139#define GPIO_BASE_ADDR          0xE0028000
140#define IOPIN0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
141#define IOSET0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
142#define IODIR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
143#define IOCLR0         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C))
144#define IOPIN1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10))
145#define IOSET1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14))
146#define IODIR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18))
147#define IOCLR1         (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
148
149/* GPIO Interrupt Registers */
150#define IO0_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
151#define IO0_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
152#define IO0_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
153#define IO0_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
154#define IO0_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
155
156#define IO2_INT_EN_R    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
157#define IO2_INT_EN_F    (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
158#define IO2_INT_STAT_R  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
159#define IO2_INT_STAT_F  (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
160#define IO2_INT_CLR     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC))
161
162#define IO_INT_STAT     (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
163
164#define PARTCFG_BASE_ADDR               0x3FFF8000
165#define PARTCFG        (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
166
167/* Fast I/O setup */
168#define FIO_BASE_ADDR           0x3FFFC000
169#define FIO0DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
170#define FIO0MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
171#define FIO0PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
172#define FIO0SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
173#define FIO0CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
174
175#define FIO1DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
176#define FIO1MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
177#define FIO1PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
178#define FIO1SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
179#define FIO1CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
180
181#define FIO2DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
182#define FIO2MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
183#define FIO2PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
184#define FIO2SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
185#define FIO2CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
186
187#define FIO3DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
188#define FIO3MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
189#define FIO3PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
190#define FIO3SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
191#define FIO3CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
192
193#define FIO4DIR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
194#define FIO4MASK       (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
195#define FIO4PIN        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
196#define FIO4SET        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
197#define FIO4CLR        (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
198
199/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
200#define FIO0DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
201#define FIO1DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
202#define FIO2DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
203#define FIO3DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
204#define FIO4DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
205
206#define FIO0DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
207#define FIO1DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
208#define FIO2DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
209#define FIO3DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
210#define FIO4DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
211
212#define FIO0DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
213#define FIO1DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
214#define FIO2DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
215#define FIO3DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
216#define FIO4DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
217
218#define FIO0DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x04))
219#define FIO1DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x24))
220#define FIO2DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x44))
221#define FIO3DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x64))
222#define FIO4DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x84))
223
224#define FIO0DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
225#define FIO1DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
226#define FIO2DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
227#define FIO3DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
228#define FIO4DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
229
230#define FIO0DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
231#define FIO1DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
232#define FIO2DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
233#define FIO3DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
234#define FIO4DIRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
235
236#define FIO0MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
237#define FIO1MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
238#define FIO2MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
239#define FIO3MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
240#define FIO4MASK0      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
241
242#define FIO0MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
243#define FIO1MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
244#define FIO2MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
245#define FIO3MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
246#define FIO4MASK1      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
247
248#define FIO0MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
249#define FIO1MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
250#define FIO2MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
251#define FIO3MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
252#define FIO4MASK2      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
253
254#define FIO0MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
255#define FIO1MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
256#define FIO2MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
257#define FIO3MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
258#define FIO4MASK3      (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
259
260#define FIO0MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
261#define FIO1MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
262#define FIO2MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
263#define FIO3MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
264#define FIO4MASKL      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
265
266#define FIO0MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
267#define FIO1MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
268#define FIO2MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
269#define FIO3MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
270#define FIO4MASKU      (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
271
272#define FIO0PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
273#define FIO1PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
274#define FIO2PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
275#define FIO3PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
276#define FIO4PIN0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
277
278#define FIO0PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
279#define FIO1PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
280#define FIO2PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
281#define FIO3PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
282#define FIO4PIN1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
283
284#define FIO0PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
285#define FIO1PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
286#define FIO2PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
287#define FIO3PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
288#define FIO4PIN2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
289
290#define FIO0PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
291#define FIO1PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
292#define FIO2PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
293#define FIO3PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
294#define FIO4PIN3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
295
296#define FIO0PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
297#define FIO1PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
298#define FIO2PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
299#define FIO3PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
300#define FIO4PINL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
301
302#define FIO0PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
303#define FIO1PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
304#define FIO2PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
305#define FIO3PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
306#define FIO4PINU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
307
308#define FIO0SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
309#define FIO1SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
310#define FIO2SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
311#define FIO3SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
312#define FIO4SET0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
313
314#define FIO0SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
315#define FIO1SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
316#define FIO2SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
317#define FIO3SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
318#define FIO4SET1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
319
320#define FIO0SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
321#define FIO1SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
322#define FIO2SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
323#define FIO3SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
324#define FIO4SET2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
325
326#define FIO0SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
327#define FIO1SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
328#define FIO2SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
329#define FIO3SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
330#define FIO4SET3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
331
332#define FIO0SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
333#define FIO1SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
334#define FIO2SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
335#define FIO3SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
336#define FIO4SETL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
337
338#define FIO0SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
339#define FIO1SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
340#define FIO2SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
341#define FIO3SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
342#define FIO4SETU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
343
344#define FIO0CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
345#define FIO1CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
346#define FIO2CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
347#define FIO3CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
348#define FIO4CLR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
349
350#define FIO0CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
351#define FIO1CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
352#define FIO2CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
353#define FIO3CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
354#define FIO4CLR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
355
356#define FIO0CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
357#define FIO1CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
358#define FIO2CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
359#define FIO3CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
360#define FIO4CLR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
361
362#define FIO0CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
363#define FIO1CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
364#define FIO2CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
365#define FIO3CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
366#define FIO4CLR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
367
368#define FIO0CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
369#define FIO1CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
370#define FIO2CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
371#define FIO3CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
372#define FIO4CLRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
373
374#define FIO0CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
375#define FIO1CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
376#define FIO2CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
377#define FIO3CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
378#define FIO4CLRU       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
379
380
381/* System Control Block(SCB) modules include Memory Accelerator Module,
382Phase Locked Loop, VPB divider, Power Control, External Interrupt,
383Reset, and Code Security/Debugging */
384#define SCB_BASE_ADDR   0xE01FC000
385
386/* Memory Accelerator Module (MAM) */
387#define MAMCR          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000))
388#define MAMTIM         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004))
389#define MEMMAP         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040))
390
391/* Phase Locked Loop (PLL) */
392#define PLLCON         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080))
393#define PLLCFG         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084))
394#define PLLSTAT        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088))
395#define PLLFEED        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C))
396
397/* Power Control */
398#define PCON           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0))
399#define PCONP          (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4))
400
401/* Clock Divider */
402// #define APBDIV         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100))
403#define CCLKCFG        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104))
404#define USBCLKCFG      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108))
405#define CLKSRCSEL      (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
406#define PCLKSEL0       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
407#define PCLKSEL1       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
408       
409/* External Interrupts */
410#define EXTINT         (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
411#define INTWAKE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
412#define EXTMODE        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148))
413#define EXTPOLAR       (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C))
414
415/* Reset, reset source identification */
416#define RSIR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180))
417
418/* RSID, code security protection */
419#define CSPR           (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184))
420
421/* AHB configuration */
422#define AHBCFG1        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188))
423#define AHBCFG2        (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
424
425/* System Controls and Status */
426#define SCS            (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
427
428
429/* External Memory Controller (EMC) */
430#define EMC_BASE_ADDR           0xFFE08000
431#define EMC_CTRL       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
432#define EMC_STAT       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
433#define EMC_CONFIG     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
434
435/* Dynamic RAM access registers */
436#define EMC_DYN_CTRL     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020))
437#define EMC_DYN_RFSH     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024))
438#define EMC_DYN_RD_CFG   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028))
439#define EMC_DYN_RP       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030))
440#define EMC_DYN_RAS      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034))
441#define EMC_DYN_SREX     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038))
442#define EMC_DYN_APR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C))
443#define EMC_DYN_DAL      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040))
444#define EMC_DYN_WR       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044))
445#define EMC_DYN_RC       (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048))
446#define EMC_DYN_RFC      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C))
447#define EMC_DYN_XSR      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050))
448#define EMC_DYN_RRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054))
449#define EMC_DYN_MRD      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058))
450
451#define EMC_DYN_CFG0     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100))
452#define EMC_DYN_RASCAS0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104))
453#define EMC_DYN_CFG1     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140))
454#define EMC_DYN_RASCAS1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144))
455#define EMC_DYN_CFG2     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160))
456#define EMC_DYN_RASCAS2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164))
457#define EMC_DYN_CFG3     (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180))
458#define EMC_DYN_RASCAS3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184))
459
460/* static RAM access registers */
461#define EMC_STA_CFG0      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
462#define EMC_STA_WAITWEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
463#define EMC_STA_WAITOEN0  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208))
464#define EMC_STA_WAITRD0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C))
465#define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210))
466#define EMC_STA_WAITWR0   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214))
467#define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
468
469#define EMC_STA_CFG1      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
470#define EMC_STA_WAITWEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
471#define EMC_STA_WAITOEN1  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228))
472#define EMC_STA_WAITRD1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C))
473#define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230))
474#define EMC_STA_WAITWR1   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234))
475#define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
476
477#define EMC_STA_CFG2      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
478#define EMC_STA_WAITWEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
479#define EMC_STA_WAITOEN2  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248))
480#define EMC_STA_WAITRD2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C))
481#define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250))
482#define EMC_STA_WAITWR2   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254))
483#define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
484
485#define EMC_STA_CFG3      (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
486#define EMC_STA_WAITWEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
487#define EMC_STA_WAITOEN3  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268))
488#define EMC_STA_WAITRD3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C))
489#define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270))
490#define EMC_STA_WAITWR3   (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274))
491#define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278))
492
493#define EMC_STA_EXT_WAIT  (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
494
495       
496/* Timer 0 */
497#define TMR0_BASE_ADDR          0xE0004000
498#define T0IR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
499#define T0TCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
500#define T0TC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
501#define T0PR           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C))
502#define T0PC           (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10))
503#define T0MCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14))
504#define T0MR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18))
505#define T0MR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C))
506#define T0MR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20))
507#define T0MR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24))
508#define T0CCR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28))
509#define T0CR0          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C))
510#define T0CR1          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30))
511#define T0CR2          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34))
512#define T0CR3          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38))
513#define T0EMR          (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C))
514#define T0CTCR         (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
515
516/* Timer 1 */
517#define TMR1_BASE_ADDR          0xE0008000
518#define T1IR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
519#define T1TCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
520#define T1TC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
521#define T1PR           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C))
522#define T1PC           (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10))
523#define T1MCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14))
524#define T1MR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18))
525#define T1MR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C))
526#define T1MR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20))
527#define T1MR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24))
528#define T1CCR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28))
529#define T1CR0          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C))
530#define T1CR1          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30))
531#define T1CR2          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34))
532#define T1CR3          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38))
533#define T1EMR          (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C))
534#define T1CTCR         (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
535
536/* Timer 2 */
537#define TMR2_BASE_ADDR          0xE0070000
538#define T2IR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
539#define T2TCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
540#define T2TC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
541#define T2PR           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C))
542#define T2PC           (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10))
543#define T2MCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14))
544#define T2MR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18))
545#define T2MR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C))
546#define T2MR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20))
547#define T2MR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24))
548#define T2CCR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28))
549#define T2CR0          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C))
550#define T2CR1          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30))
551#define T2CR2          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34))
552#define T2CR3          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38))
553#define T2EMR          (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C))
554#define T2CTCR         (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
555
556/* Timer 3 */
557#define TMR3_BASE_ADDR          0xE0074000
558#define T3IR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
559#define T3TCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
560#define T3TC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
561#define T3PR           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C))
562#define T3PC           (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10))
563#define T3MCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14))
564#define T3MR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18))
565#define T3MR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C))
566#define T3MR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20))
567#define T3MR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24))
568#define T3CCR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28))
569#define T3CR0          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C))
570#define T3CR1          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30))
571#define T3CR2          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34))
572#define T3CR3          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38))
573#define T3EMR          (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C))
574#define T3CTCR         (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70))
575
576
577/* Pulse Width Modulator (PWM) */
578#define PWM0_BASE_ADDR          0xE0014000
579#define PWM0IR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
580#define PWM0TCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
581#define PWM0TC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
582#define PWM0PR          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C))
583#define PWM0PC          (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10))
584#define PWM0MCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14))
585#define PWM0MR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18))
586#define PWM0MR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C))
587#define PWM0MR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20))
588#define PWM0MR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24))
589#define PWM0CCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28))
590#define PWM0CR0         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C))
591#define PWM0CR1         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30))
592#define PWM0CR2         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34))
593#define PWM0CR3         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38))
594#define PWM0EMR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C))
595#define PWM0MR4         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40))
596#define PWM0MR5         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44))
597#define PWM0MR6         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48))
598#define PWM0PCR         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C))
599#define PWM0LER         (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
600#define PWM0CTCR        (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
601
602#define PWM1_BASE_ADDR          0xE0018000
603#define PWM1IR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
604#define PWM1TCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
605#define PWM1TC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
606#define PWM1PR          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C))
607#define PWM1PC          (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10))
608#define PWM1MCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14))
609#define PWM1MR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18))
610#define PWM1MR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C))
611#define PWM1MR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20))
612#define PWM1MR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24))
613#define PWM1CCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28))
614#define PWM1CR0         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C))
615#define PWM1CR1         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30))
616#define PWM1CR2         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34))
617#define PWM1CR3         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38))
618#define PWM1EMR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C))
619#define PWM1MR4         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40))
620#define PWM1MR5         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44))
621#define PWM1MR6         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48))
622#define PWM1PCR         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C))
623#define PWM1LER         (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50))
624#define PWM1CTCR        (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70))
625
626
627/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
628#define UART0_BASE_ADDR         0xE000C000
629#define U0RBR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
630#define U0THR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
631#define U0DLL          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
632#define U0DLM          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
633#define U0IER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
634#define U0IIR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
635#define U0FCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
636#define U0LCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C))
637#define U0LSR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14))
638#define U0SCR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C))
639#define U0ACR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20))
640#define U0ICR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24))
641#define U0FDR          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28))
642#define U0TER          (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
643
644/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
645#define UART1_BASE_ADDR         0xE0010000
646#define U1RBR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
647#define U1THR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
648#define U1DLL          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
649#define U1DLM          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
650#define U1IER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
651#define U1IIR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
652#define U1FCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
653#define U1LCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C))
654#define U1MCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10))
655#define U1LSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14))
656#define U1MSR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18))
657#define U1SCR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C))
658#define U1ACR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20))
659#define U1FDR          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28))
660#define U1TER          (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
661
662/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
663#define UART2_BASE_ADDR         0xE0078000
664#define U2RBR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
665#define U2THR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
666#define U2DLL          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
667#define U2DLM          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
668#define U2IER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
669#define U2IIR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
670#define U2FCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
671#define U2LCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C))
672#define U2LSR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14))
673#define U2SCR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C))
674#define U2ACR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20))
675#define U2ICR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24))
676#define U2FDR          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28))
677#define U2TER          (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
678
679/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
680#define UART3_BASE_ADDR         0xE007C000
681#define U3RBR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
682#define U3THR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
683#define U3DLL          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
684#define U3DLM          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
685#define U3IER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
686#define U3IIR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
687#define U3FCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
688#define U3LCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C))
689#define U3LSR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14))
690#define U3SCR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C))
691#define U3ACR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20))
692#define U3ICR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24))
693#define U3FDR          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28))
694#define U3TER          (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
695
696/* I2C Interface 0 */
697#define I2C0_BASE_ADDR          0xE001C000
698#define I20CONSET      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
699#define I20STAT        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
700#define I20DAT         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
701#define I20ADR         (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C))
702#define I20SCLH        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10))
703#define I20SCLL        (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14))
704#define I20CONCLR      (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
705
706/* I2C Interface 1 */
707#define I2C1_BASE_ADDR          0xE005C000
708#define I21CONSET      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
709#define I21STAT        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
710#define I21DAT         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
711#define I21ADR         (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C))
712#define I21SCLH        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10))
713#define I21SCLL        (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14))
714#define I21CONCLR      (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
715
716/* I2C Interface 2 */
717#define I2C2_BASE_ADDR          0xE0080000
718#define I22CONSET      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
719#define I22STAT        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
720#define I22DAT         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
721#define I22ADR         (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C))
722#define I22SCLH        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10))
723#define I22SCLL        (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14))
724#define I22CONCLR      (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18))
725
726/* SPI0 (Serial Peripheral Interface 0) */
727#define SPI0_BASE_ADDR          0xE0020000
728#define S0SPCR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00))
729#define S0SPSR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04))
730#define S0SPDR         (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08))
731#define S0SPCCR        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C))
732#define S0SPINT        (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
733
734/* SSP0 Controller */
735#define SSP0_BASE_ADDR          0xE0068000
736#define SSP0CR0        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
737#define SSP0CR1        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
738#define SSP0DR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
739#define SSP0SR         (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C))
740#define SSP0CPSR       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10))
741#define SSP0IMSC       (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14))
742#define SSP0RIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18))
743#define SSP0MIS        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C))
744#define SSP0ICR        (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20))
745#define SSP0DMACR      (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
746
747/* SSP1 Controller */
748#define SSP1_BASE_ADDR          0xE0030000
749#define SSP1CR0        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
750#define SSP1CR1        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
751#define SSP1DR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
752#define SSP1SR         (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C))
753#define SSP1CPSR       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10))
754#define SSP1IMSC       (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14))
755#define SSP1RIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18))
756#define SSP1MIS        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C))
757#define SSP1ICR        (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
758#define SSP1DMACR      (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
759
760
761/* Real Time Clock */
762#define RTC_BASE_ADDR           0xE0024000
763#define RTC_ILR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
764#define RTC_CTC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
765#define RTC_CCR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
766#define RTC_CIIR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C))
767#define RTC_AMR         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10))
768#define RTC_CTIME0      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14))
769#define RTC_CTIME1      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18))
770#define RTC_CTIME2      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C))
771#define RTC_SEC         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20))
772#define RTC_MIN         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24))
773#define RTC_HOUR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28))
774#define RTC_DOM         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C))
775#define RTC_DOW         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30))
776#define RTC_DOY         (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34))
777#define RTC_MONTH       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38))
778#define RTC_YEAR        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C))
779#define RTC_CISS        (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40))
780#define RTC_ALSEC       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60))
781#define RTC_ALMIN       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64))
782#define RTC_ALHOUR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68))
783#define RTC_ALDOM       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C))
784#define RTC_ALDOW       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70))
785#define RTC_ALDOY       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74))
786#define RTC_ALMON       (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78))
787#define RTC_ALYEAR      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C))
788#define RTC_PREINT      (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80))
789#define RTC_PREFRAC     (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84))
790
791
792/* A/D Converter 0 (AD0) */
793#define AD0_BASE_ADDR           0xE0034000
794#define AD0CR          (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
795#define AD0GDR         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
796#define AD0INTEN       (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
797#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
798#define AD0DR0         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
799#define AD0DR1         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
800#define AD0DR2         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18))
801#define AD0DR3         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C))
802#define AD0DR4         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20))
803#define AD0DR5         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24))
804#define AD0DR6         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28))
805#define AD0DR7         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C))
806#define AD0STAT        (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30))
807
808
809/* D/A Converter */
810#define DAC_BASE_ADDR           0xE006C000
811#define DACR           (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
812
813
814/* Watchdog */
815#define WDG_BASE_ADDR           0xE0000000
816#define WDMOD          (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
817#define WDTC           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
818#define WDFEED         (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
819#define WDTV           (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C))
820#define WDCLKSEL       (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
821
822/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
823#define CAN_ACCEPT_BASE_ADDR            0xE003C000
824#define CAN_AFMR                (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))         
825#define CAN_SFF_SA              (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))         
826#define CAN_SFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
827#define CAN_EFF_SA              (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
828#define CAN_EFF_GRP_SA  (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))         
829#define CAN_EOT                 (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
830#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))         
831#define CAN_LUT_ERR     (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
832
833#define CAN_CENTRAL_BASE_ADDR           0xE0040000     
834#define CAN_TX_SR       (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))         
835#define CAN_RX_SR       (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))         
836#define CAN_MSR         (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
837
838#define CAN1_BASE_ADDR          0xE0044000
839#define CAN1MOD         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))       
840#define CAN1CMR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))       
841#define CAN1GSR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))       
842#define CAN1ICR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))       
843#define CAN1IER         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
844#define CAN1BTR         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))       
845#define CAN1EWL         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))       
846#define CAN1SR          (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))       
847#define CAN1RFS         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))       
848#define CAN1RID         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
849#define CAN1RDA         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))       
850#define CAN1RDB         (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
851       
852#define CAN1TFI1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))       
853#define CAN1TID1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))       
854#define CAN1TDA1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
855#define CAN1TDB1        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))       
856#define CAN1TFI2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))       
857#define CAN1TID2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))       
858#define CAN1TDA2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))       
859#define CAN1TDB2        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
860#define CAN1TFI3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))       
861#define CAN1TID3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))       
862#define CAN1TDA3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))       
863#define CAN1TDB3        (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
864
865#define CAN2_BASE_ADDR          0xE0048000
866#define CAN2MOD         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))       
867#define CAN2CMR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))       
868#define CAN2GSR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))       
869#define CAN2ICR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))       
870#define CAN2IER         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
871#define CAN2BTR         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))       
872#define CAN2EWL         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))       
873#define CAN2SR          (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))       
874#define CAN2RFS         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))       
875#define CAN2RID         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
876#define CAN2RDA         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))       
877#define CAN2RDB         (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
878       
879#define CAN2TFI1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))       
880#define CAN2TID1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))       
881#define CAN2TDA1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
882#define CAN2TDB1        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))       
883#define CAN2TFI2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))       
884#define CAN2TID2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))       
885#define CAN2TDA2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))       
886#define CAN2TDB2        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
887#define CAN2TFI3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))       
888#define CAN2TID3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))       
889#define CAN2TDA3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))       
890#define CAN2TDB3        (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
891
892
893/* MultiMedia Card Interface(MCI) Controller */
894#define MCI_BASE_ADDR           0xE008C000
895#define MCI_POWER      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
896#define MCI_CLOCK      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
897#define MCI_ARGUMENT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
898#define MCI_COMMAND    (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C))
899#define MCI_RESP_CMD   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10))
900#define MCI_RESP0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14))
901#define MCI_RESP1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18))
902#define MCI_RESP2      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C))
903#define MCI_RESP3      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20))
904#define MCI_DATA_TMR   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24))
905#define MCI_DATA_LEN   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28))
906#define MCI_DATA_CTRL  (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C))
907#define MCI_DATA_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30))
908#define MCI_STATUS     (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34))
909#define MCI_CLEAR      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38))
910#define MCI_MASK0      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C))
911#define MCI_MASK1      (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40))
912#define MCI_FIFO_CNT   (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48))
913#define MCI_FIFO       (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80))
914
915
916/* I2S Interface Controller (I2S) */
917#define I2S_BASE_ADDR           0xE0088000
918#define I2S_DAO        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
919#define I2S_DAI        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
920#define I2S_TX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
921#define I2S_RX_FIFO    (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C))
922#define I2S_STATE      (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10))
923#define I2S_DMA1       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14))
924#define I2S_DMA2       (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18))
925#define I2S_IRQ        (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C))
926#define I2S_TXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20))
927#define I2S_RXRATE     (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24))
928
929
930/* General-purpose DMA Controller */
931#define DMA_BASE_ADDR           0xFFE04000
932#define GPDMA_INT_STAT         (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
933#define GPDMA_INT_TCSTAT       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
934#define GPDMA_INT_TCCLR        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
935#define GPDMA_INT_ERR_STAT     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C))
936#define GPDMA_INT_ERR_CLR      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010))
937#define GPDMA_RAW_INT_TCSTAT   (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014))
938#define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018))
939#define GPDMA_ENABLED_CHNS     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C))
940#define GPDMA_SOFT_BREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020))
941#define GPDMA_SOFT_SREQ        (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024))
942#define GPDMA_SOFT_LBREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028))
943#define GPDMA_SOFT_LSREQ       (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C))
944#define GPDMA_CONFIG           (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030))
945#define GPDMA_SYNC             (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
946
947/* DMA channel 0 registers */
948#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
949#define GPDMA_CH0_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
950#define GPDMA_CH0_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
951#define GPDMA_CH0_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
952#define GPDMA_CH0_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C))
953#define GPDMA_CH0_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
954
955/* DMA channel 1 registers */
956#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
957#define GPDMA_CH1_SRC      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
958#define GPDMA_CH1_DEST     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
959#define GPDMA_CH1_LLI      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
960#define GPDMA_CH1_CTRL     (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
961#define GPDMA_CH1_CFG      (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
962
963
964/* USB Controller */
965#define USB_INT_BASE_ADDR       0xE01FC1C0
966#define USB_BASE_ADDR           0xFFE0C200              /* USB Base Address */
967
968#define USB_INT_STAT    (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
969
970/* USB Device Interrupt Registers */
971#define DEV_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00))
972#define DEV_INT_EN      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04))
973#define DEV_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08))
974#define DEV_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C))
975#define DEV_INT_PRIO    (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C))
976
977/* USB Device Endpoint Interrupt Registers */
978#define EP_INT_STAT     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30))
979#define EP_INT_EN       (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34))
980#define EP_INT_CLR      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38))
981#define EP_INT_SET      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C))
982#define EP_INT_PRIO     (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40))
983
984/* USB Device Endpoint Realization Registers */
985#define REALIZE_EP      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44))
986#define EP_INDEX        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48))
987#define MAXPACKET_SIZE  (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C))
988
989/* USB Device Command Reagisters */
990#define CMD_CODE        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10))
991#define CMD_DATA        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14))
992
993/* USB Device Data Transfer Registers */
994#define RX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18))
995#define TX_DATA         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C))
996#define RX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20))
997#define TX_PLENGTH      (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24))
998#define USB_CTRL        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28))
999
1000/* USB Device DMA Registers */
1001#define DMA_REQ_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50))
1002#define DMA_REQ_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54))
1003#define DMA_REQ_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58))
1004#define UDCA_HEAD           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80))
1005#define EP_DMA_STAT         (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84))
1006#define EP_DMA_EN           (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88))
1007#define EP_DMA_DIS          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C))
1008#define DMA_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90))
1009#define DMA_INT_EN          (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94))
1010#define EOT_INT_STAT        (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0))
1011#define EOT_INT_CLR         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4))
1012#define EOT_INT_SET         (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8))
1013#define NDD_REQ_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC))
1014#define NDD_REQ_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0))
1015#define NDD_REQ_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4))
1016#define SYS_ERR_INT_STAT    (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8))
1017#define SYS_ERR_INT_CLR     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
1018#define SYS_ERR_INT_SET     (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
1019
1020
1021/* USB Host Controller */
1022#define USBHC_BASE_ADDR         0xFFE0C000
1023#define HC_REVISION         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
1024#define HC_CONTROL          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
1025#define HC_CMD_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
1026#define HC_INT_STAT         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C))
1027#define HC_INT_EN           (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10))
1028#define HC_INT_DIS          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14))
1029#define HC_HCCA             (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18))
1030#define HC_PERIOD_CUR_ED    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C))
1031#define HC_CTRL_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20))
1032#define HC_CTRL_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24))
1033#define HC_BULK_HEAD_ED     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28))
1034#define HC_BULK_CUR_ED      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C))
1035#define HC_DONE_HEAD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30))
1036#define HC_FM_INTERVAL      (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34))
1037#define HC_FM_REMAINING     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38))
1038#define HC_FM_NUMBER        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C))
1039#define HC_PERIOD_START     (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40))
1040#define HC_LS_THRHLD        (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44))
1041#define HC_RH_DESCA         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48))
1042#define HC_RH_DESCB         (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C))
1043#define HC_RH_STAT          (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50))
1044#define HC_RH_PORT_STAT1    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54))
1045#define HC_RH_PORT_STAT2    (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
1046
1047/* USB OTG Controller */
1048#define USBOTG_BASE_ADDR        0xFFE0C100
1049#define OTG_INT_STAT        (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
1050#define OTG_INT_EN          (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
1051#define OTG_INT_SET         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
1052#define OTG_INT_CLR         (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C))
1053#define OTG_STAT_CTRL       (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
1054#define OTG_TIMER           (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
1055
1056#define USBOTG_I2C_BASE_ADDR    0xFFE0C300
1057#define OTG_I2C_RX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1058#define OTG_I2C_TX          (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
1059#define OTG_I2C_STS         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
1060#define OTG_I2C_CTL         (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08))
1061#define OTG_I2C_CLKHI       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
1062#define OTG_I2C_CLKLO       (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
1063
1064#define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
1065#define OTG_CLK_CTRL        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
1066#define OTG_CLK_STAT        (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
1067
1068
1069/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1070#define MAC_BASE_ADDR           0xFFE00000 /* AHB Peripheral # 0 */
1071#define MAC_MAC1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1072#define MAC_MAC2            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1073#define MAC_IPGT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1074#define MAC_IPGR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1075#define MAC_CLRT            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1076#define MAC_MAXF            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1077#define MAC_SUPP            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1078#define MAC_TEST            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1079#define MAC_MCFG            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1080#define MAC_MCMD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1081#define MAC_MADR            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1082#define MAC_MWTD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1083#define MAC_MRDD            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1084#define MAC_MIND            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1085
1086#define MAC_SA0             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1087#define MAC_SA1             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1088#define MAC_SA2             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1089
1090#define MAC_COMMAND         (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */
1091#define MAC_STATUS          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1092#define MAC_RXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1093#define MAC_RXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1094#define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1095#define MAC_RXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1096#define MAC_RXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1097#define MAC_TXDESCRIPTOR    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1098#define MAC_TXSTATUS        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1099#define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1100#define MAC_TXPRODUCEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1101#define MAC_TXCONSUMEINDEX  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1102
1103#define MAC_TSV0            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1104#define MAC_TSV1            (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1105#define MAC_RSV             (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1106
1107#define MAC_FLOWCONTROLCNT  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1108#define MAC_FLOWCONTROLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1109
1110#define MAC_RXFILTERCTRL    (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1111#define MAC_RXFILTERWOLSTS  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1112#define MAC_RXFILTERWOLCLR  (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1113
1114#define MAC_HASHFILTERL     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1115#define MAC_HASHFILTERH     (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1116
1117#define MAC_INTSTATUS       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1118#define MAC_INTENABLE       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg  */
1119#define MAC_INTCLEAR        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1120#define MAC_INTSET          (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1121
1122#define MAC_POWERDOWN       (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1123#define MAC_MODULEID        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1124
1125/* LCD Controller */   
1126
1127#define LCD_BASE_ADDR 0xFFE10000                               
1128#define LCD_CFG       (*(volatile uint32_t *) 0xE01FC1B8)
1129#define LCD_TIMH      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
1130#define LCD_TIMV      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
1131#define LCD_POL       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008))
1132#define LCD_LE        (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C))
1133#define LCD_UPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010))
1134#define LCD_LPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014))
1135#define LCD_CTRL      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018))
1136#define LCD_INTMSK    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C))
1137#define LCD_INTRAW    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020))
1138#define LCD_INTSTAT   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024))
1139#define LCD_INTCLR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028))
1140#define LCD_UPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C))
1141#define LCD_LPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030))
1142#define LCD_PAL_ADDR  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200))
1143#define CRSR_IMG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800))
1144#define CRSR_CTLR     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00))
1145#define CRSR_CFG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04))
1146#define CRSR_PAL0     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08))
1147#define CRSR_PAL1     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C))
1148#define CRSR_XY       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10))
1149#define CRSR_CLIP     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14))
1150#define CRSR_INTMSK   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20))
1151#define CRSR_INTCLR   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24))
1152#define CRSR_INTRAW   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28))
1153#define CRSR_INTSTAT  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C))
1154
1155/* Register Fields */
1156
1157/* CLKSRCSEL */
1158
1159#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1160
1161#define GET_CLKSRCSEL_CLKSRC( reg) \
1162  GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
1163
1164#define SET_CLKSRCSEL_CLKSRC( reg, val) \
1165  SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1166
1167/* PLLCON */
1168
1169#define PLLCON_PLLE 0x00000001U
1170
1171#define PLLCON_PLLC 0x00000002U
1172
1173/* PLLCFG */
1174
1175#define PLLCFG_MSEL_MASK 0x00007fffU
1176
1177#define GET_PLLCFG_MSEL( reg) \
1178  GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
1179
1180#define SET_PLLCFG_MSEL( reg, val) \
1181  SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
1182
1183#define PLLCFG_NSEL_MASK 0x00ff0000U
1184
1185#define GET_PLLCFG_NSEL( reg) \
1186  GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
1187
1188#define SET_PLLCFG_NSEL( reg, val) \
1189  SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
1190
1191/* PLLSTAT */
1192
1193#define PLLSTAT_MSEL_MASK 0x00007fffU
1194
1195#define GET_PLLSTAT_MSEL( reg) \
1196  GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
1197
1198#define SET_PLLSTAT_MSEL( reg, val) \
1199  SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
1200
1201#define PLLSTAT_NSEL_MASK 0x00ff0000U
1202
1203#define GET_PLLSTAT_NSEL( reg) \
1204  GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
1205
1206#define SET_PLLSTAT_NSEL( reg, val) \
1207  SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
1208
1209#define PLLSTAT_PLLE 0x01000000U
1210
1211#define PLLSTAT_PLLC 0x02000000U
1212
1213#define PLLSTAT_PLOCK 0x04000000U
1214
1215/* CCLKCFG */
1216
1217#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1218
1219#define GET_CCLKCFG_CCLKSEL( reg) \
1220  GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
1221
1222#define SET_CCLKCFG_CCLKSEL( reg, val) \
1223  SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1224
1225/* MEMMAP */
1226
1227#define MEMMAP_MAP_MASK 0x00000003U
1228
1229#define GET_MEMMAP_MAP( reg) \
1230  GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
1231
1232#define SET_MEMMAP_MAP( reg, val) \
1233  SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
1234
1235/* TIR */
1236
1237#define TIR_MR0 0x00000001U
1238
1239#define TIR_MR1 0x00000002U
1240
1241#define TIR_MR2 0x00000004U
1242
1243#define TIR_MR3 0x00000008U
1244
1245#define TIR_CR0 0x00000010U
1246
1247#define TIR_CR1 0x00000020U
1248
1249#define TIR_CR2 0x00000040U
1250
1251#define TIR_CR3 0x00000080U
1252
1253/* TCR */
1254
1255#define TCR_EN 0x00000001U
1256
1257#define TCR_RST 0x00000002U
1258
1259/* TMCR */
1260
1261#define TMCR_MR0I 0x00000001U
1262
1263#define TMCR_MR0R 0x00000002U
1264
1265#define TMCR_MR0S 0x00000004U
1266
1267#define TMCR_MR1I 0x00000008U
1268
1269#define TMCR_MR1R 0x00000010U
1270
1271#define TMCR_MR1S 0x00000020U
1272
1273#define TMCR_MR2I 0x00000040U
1274
1275#define TMCR_MR2R 0x00000080U
1276
1277#define TMCR_MR2S 0x00000100U
1278
1279#define TMCR_MR3I 0x00000200U
1280
1281#define TMCR_MR3R 0x00000400U
1282
1283#define TMCR_MR3S 0x00000800U
1284
1285/* PCLKSEL0 */
1286
1287#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1288
1289#define GET_PCLKSEL0_PCLK_WDT( reg) \
1290  GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1291
1292#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
1293  SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1294
1295#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1296
1297#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
1298  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1299
1300#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
1301  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1302
1303#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1304
1305#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
1306  GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1307
1308#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
1309  SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1310
1311#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1312
1313#define GET_PCLKSEL0_PCLK_UART0( reg) \
1314  GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1315
1316#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
1317  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1318
1319#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1320
1321#define GET_PCLKSEL0_PCLK_UART1( reg) \
1322  GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1323
1324#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
1325  SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1326
1327#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1328
1329#define GET_PCLKSEL0_PCLK_PWM0( reg) \
1330  GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1331
1332#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
1333  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1334
1335#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1336
1337#define GET_PCLKSEL0_PCLK_PWM1( reg) \
1338  GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1339
1340#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
1341  SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1342
1343#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1344
1345#define GET_PCLKSEL0_PCLK_I2C0( reg) \
1346  GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1347
1348#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
1349  SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1350
1351#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1352
1353#define GET_PCLKSEL0_PCLK_SPI( reg) \
1354  GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1355
1356#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
1357  SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1358
1359#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1360
1361#define GET_PCLKSEL0_PCLK_RTC( reg) \
1362  GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1363
1364#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
1365  SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1366
1367#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1368
1369#define GET_PCLKSEL0_PCLK_SSP1( reg) \
1370  GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1371
1372#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
1373  SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1374
1375#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1376
1377#define GET_PCLKSEL0_PCLK_DAC( reg) \
1378  GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1379
1380#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
1381  SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1382
1383#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1384
1385#define GET_PCLKSEL0_PCLK_ADC( reg) \
1386  GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1387
1388#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
1389  SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1390
1391#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1392
1393#define GET_PCLKSEL0_PCLK_CAN1( reg) \
1394  GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1395
1396#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
1397  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1398
1399#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1400
1401#define GET_PCLKSEL0_PCLK_CAN2( reg) \
1402  GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1403
1404#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
1405  SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1406
1407/* PCLKSEL1 */
1408
1409#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1410
1411#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
1412  GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1413
1414#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
1415  SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1416
1417#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1418
1419#define GET_PCLKSEL1_PCLK_GPIO( reg) \
1420  GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1421
1422#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
1423  SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1424
1425#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1426
1427#define GET_PCLKSEL1_PCLK_PCB( reg) \
1428  GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1429
1430#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
1431  SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1432
1433#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1434
1435#define GET_PCLKSEL1_PCLK_I2C1( reg) \
1436  GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1437
1438#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
1439  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1440
1441#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1442
1443#define GET_PCLKSEL1_PCLK_SSP0( reg) \
1444  GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1445
1446#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
1447  SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1448
1449#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1450
1451#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
1452  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1453
1454#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
1455  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1456
1457#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1458
1459#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
1460  GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1461
1462#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
1463  SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1464
1465#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1466
1467#define GET_PCLKSEL1_PCLK_UART2( reg) \
1468  GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1469
1470#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
1471  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1472
1473#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1474
1475#define GET_PCLKSEL1_PCLK_UART3( reg) \
1476  GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1477
1478#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
1479  SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1480
1481#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1482
1483#define GET_PCLKSEL1_PCLK_I2C2( reg) \
1484  GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1485
1486#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
1487  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1488
1489#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1490
1491#define GET_PCLKSEL1_PCLK_I2S( reg) \
1492  GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1493
1494#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
1495  SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1496
1497#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1498
1499#define GET_PCLKSEL1_PCLK_MCI( reg) \
1500  GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1501
1502#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
1503  SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1504
1505#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1506
1507#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
1508  GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1509
1510#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
1511  SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1512
1513/* RTC_ILR */
1514
1515#define RTC_ILR_RTCCIF 0x00000001U
1516
1517#define RTC_ILR_RTCALF 0x00000002U
1518
1519#define RTC_ILR_RTSSF 0x00000004U
1520
1521/* RTC_CCR */
1522
1523#define RTC_CCR_CLKEN 0x00000001U
1524
1525#define RTC_CCR_CTCRST 0x00000002U
1526
1527#define RTC_CCR_CLKSRC 0x00000010U
1528
1529/* SSP */
1530
1531typedef struct {
1532  uint32_t cr0;
1533  uint32_t cr1;
1534  uint32_t dr;
1535  uint32_t sr;
1536  uint32_t cpsr;
1537  uint32_t imsc;
1538  uint32_t ris;
1539  uint32_t mis;
1540  uint32_t icr;
1541  uint32_t dmacr;
1542} lpc24xx_ssp;
1543
1544/* SSP_CR0 */
1545
1546#define SSP_CR0_DSS_MASK 0x0000000fU
1547
1548#define GET_SSP_CR0_DSS( reg) \
1549  GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
1550
1551#define SET_SSP_CR0_DSS( reg, val) \
1552  SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
1553
1554#define SSP_CR0_FRF_MASK 0x00000030U
1555
1556#define GET_SSP_CR0_FRF( reg) \
1557  GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
1558
1559#define SET_SSP_CR0_FRF( reg, val) \
1560  SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
1561
1562#define SSP_CR0_CPOL 0x00000040U
1563
1564#define SSP_CR0_CPHA 0x00000080U
1565
1566#define SSP_CR0_SCR_MASK 0x0000ff00U
1567
1568#define GET_SSP_CR0_SCR( reg) \
1569  GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
1570
1571#define SET_SSP_CR0_SCR( reg, val) \
1572  SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
1573
1574/* SSP_CR1 */
1575
1576#define SSP_CR1_LBM 0x00000001U
1577
1578#define SSP_CR1_SSE 0x00000002U
1579
1580#define SSP_CR1_MS 0x00000004U
1581
1582#define SSP_CR1_SOD 0x00000008U
1583
1584/* SSP_SR */
1585
1586#define SSP_SR_TFE 0x00000001U
1587
1588#define SSP_SR_TNF 0x00000002U
1589
1590#define SSP_SR_RNE 0x00000004U
1591
1592#define SSP_SR_RFF 0x00000008U
1593
1594#define SSP_SR_BSY 0x00000010U
1595
1596/* SSP_IMSC */
1597
1598#define SSP_IMSC_RORIM 0x00000001U
1599
1600#define SSP_IMSC_RTIM 0x00000002U
1601
1602#define SSP_IMSC_RXIM 0x00000004U
1603
1604#define SSP_IMSC_TXIM 0x00000008U
1605
1606/* SSP_RIS */
1607
1608#define SSP_RIS_RORRIS 0x00000001U
1609
1610#define SSP_RIS_RTRIS 0x00000002U
1611
1612#define SSP_RIS_RXRIS 0x00000004U
1613
1614#define SSP_RIS_TXRIS 0x00000008U
1615
1616/* SSP_MIS */
1617
1618#define SSP_MIS_RORRIS 0x00000001U
1619
1620#define SSP_MIS_RTRIS 0x00000002U
1621
1622#define SSP_MIS_RXRIS 0x00000004U
1623
1624#define SSP_MIS_TXRIS 0x00000008U
1625
1626/* SSP_ICR */
1627
1628#define SSP_ICR_RORRIS 0x00000001U
1629
1630#define SSP_ICR_RTRIS 0x00000002U
1631
1632#define SSP_ICR_RXRIS 0x00000004U
1633
1634#define SSP_ICR_TXRIS 0x00000008U
1635
1636/* SSP_DMACR */
1637
1638#define SSP_DMACR_RXDMAE 0x00000001U
1639
1640#define SSP_DMACR_TXDMAE 0x00000002U
1641
1642/* GPDMA */
1643
1644typedef struct {
1645  uint32_t src;
1646  uint32_t dest;
1647  uint32_t lli;
1648  uint32_t ctrl;
1649  uint32_t cfg;
1650} lpc24xx_dma_channel;
1651
1652#define GPDMA_CH_NUMBER 2
1653
1654#define GPDMA_STATUS_CH_0 0x00000001U
1655
1656#define GPDMA_STATUS_CH_1 0x00000002U
1657
1658#define GPDMA_CH_BASE_ADDR( i) \
1659  ((volatile lpc24xx_dma_channel *) \
1660    ((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1661
1662/* GPDMA_CONFIG */
1663
1664#define GPDMA_CONFIG_EN 0x00000001U
1665
1666#define GPDMA_CONFIG_MODE 0x00000002U
1667
1668/* GPDMA_ENABLED_CHNS */
1669
1670#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1671
1672#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1673
1674/* GPDMA_CH_CTRL */
1675
1676#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1677
1678#define GET_GPDMA_CH_CTRL_TSZ( reg) \
1679  GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1680
1681#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
1682  SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1683
1684#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1685
1686#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1687
1688#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
1689  GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1690
1691#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
1692  SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1693
1694#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1695
1696#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
1697  GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1698
1699#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
1700  SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1701
1702#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1703
1704#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1705
1706#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1707
1708#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1709
1710#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1711
1712#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1713
1714#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1715
1716#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1717
1718#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1719
1720#define GET_GPDMA_CH_CTRL_SW( reg) \
1721  GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
1722
1723#define SET_GPDMA_CH_CTRL_SW( reg, val) \
1724  SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1725
1726#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1727
1728#define GET_GPDMA_CH_CTRL_DW( reg) \
1729  GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
1730
1731#define SET_GPDMA_CH_CTRL_DW( reg, val) \
1732  SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1733
1734#define GPDMA_CH_CTRL_W_8 0x00000000U
1735
1736#define GPDMA_CH_CTRL_W_16 0x00000001U
1737
1738#define GPDMA_CH_CTRL_W_32 0x00000002U
1739
1740#define GPDMA_CH_CTRL_SI 0x04000000U
1741
1742#define GPDMA_CH_CTRL_DI 0x08000000U
1743
1744#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1745
1746#define GET_GPDMA_CH_CTRL_PROT( reg) \
1747  GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1748
1749#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
1750  SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1751
1752#define GPDMA_CH_CTRL_ITC 0x80000000U
1753
1754/* GPDMA_CH_CFG */
1755
1756#define GPDMA_CH_CFG_EN 0x00000001U
1757
1758#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1759
1760#define GET_GPDMA_CH_CFG_SRCPER( reg) \
1761  GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1762
1763#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
1764  SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1765
1766#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1767
1768#define GET_GPDMA_CH_CFG_DESTPER( reg) \
1769  GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
1770
1771#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
1772  SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
1773
1774#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1775
1776#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1777
1778#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1779
1780#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1781
1782#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1783
1784#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1785
1786#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1787
1788#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1789
1790#define GET_GPDMA_CH_CFG_FLOW( reg) \
1791  GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
1792
1793#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
1794  SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
1795
1796#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1797
1798#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1799
1800#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1801
1802#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1803
1804#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1805
1806#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1807
1808#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1809
1810#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1811
1812#define GPDMA_CH_CFG_IE 0x00004000U
1813
1814#define GPDMA_CH_CFG_ITC 0x00008000U
1815
1816#define GPDMA_CH_CFG_LOCK 0x00010000U
1817
1818#define GPDMA_CH_CFG_ACTIVE 0x00020000U
1819
1820#define GPDMA_CH_CFG_HALT 0x00040000U
1821
1822/* Ethernet (MAC) */
1823
1824typedef struct {
1825  uint32_t start;
1826  uint32_t control;
1827} lpc24xx_eth_transfer_descriptor;
1828
1829typedef struct {
1830  uint32_t status;
1831  uint32_t hash_crc;
1832} lpc24xx_eth_receive_info;
1833
1834#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
1835
1836#define ETH_RECEIVE_INFO_SIZE 8
1837
1838#define ETH_TRANSMIT_STATUS_SIZE 4
1839
1840/* ETH_RX_CTRL */
1841
1842#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
1843
1844#define GET_ETH_RX_CTRL_SIZE( reg) \
1845  GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
1846
1847#define SET_ETH_RX_CTRL_SIZE( reg, val) \
1848  SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
1849
1850#define ETH_RX_CTRL_INTERRUPT 0x80000000U
1851
1852/* ETH_RX_STAT */
1853
1854#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
1855
1856#define GET_ETH_RX_STAT_RXSIZE( reg) \
1857  GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
1858
1859#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
1860  SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
1861
1862#define ETH_RX_STAT_BYTES 0x00000100U
1863
1864#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
1865
1866#define ETH_RX_STAT_VLAN 0x00080000U
1867
1868#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
1869
1870#define ETH_RX_STAT_MULTICAST 0x00200000U
1871
1872#define ETH_RX_STAT_BROADCAST 0x00400000U
1873
1874#define ETH_RX_STAT_CRC_ERROR 0x00800000U
1875
1876#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
1877
1878#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
1879
1880#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
1881
1882#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
1883
1884#define ETH_RX_STAT_OVERRUN 0x10000000U
1885
1886#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
1887
1888#define ETH_RX_STAT_LAST_FLAG 0x40000000U
1889
1890#define ETH_RX_STAT_ERROR 0x80000000U
1891
1892/* ETH_TX_CTRL */
1893
1894#define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
1895
1896#define GET_ETH_TX_CTRL_SIZE( reg) \
1897  GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
1898
1899#define SET_ETH_TX_CTRL_SIZE( reg, val) \
1900  SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
1901
1902#define ETH_TX_CTRL_OVERRIDE 0x04000000U
1903
1904#define ETH_TX_CTRL_HUGE 0x08000000U
1905
1906#define ETH_TX_CTRL_PAD 0x10000000U
1907
1908#define ETH_TX_CTRL_CRC 0x20000000U
1909
1910#define ETH_TX_CTRL_LAST 0x40000000U
1911
1912#define ETH_TX_CTRL_INTERRUPT 0x80000000U
1913
1914/* ETH_TX_STAT */
1915
1916#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
1917
1918#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
1919  GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
1920
1921#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
1922  SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
1923
1924#define ETH_TX_STAT_DEFER 0x02000000U
1925
1926#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
1927
1928#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
1929
1930#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
1931
1932#define ETH_TX_STAT_UNDERRUN 0x20000000U
1933
1934#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
1935
1936#define ETH_TX_STAT_ERROR 0x80000000U
1937
1938/* ETH_INT */
1939
1940#define ETH_INT_RX_OVERRUN 0x00000001U
1941
1942#define ETH_INT_RX_ERROR 0x00000002U
1943
1944#define ETH_INT_RX_FINISHED 0x00000004U
1945
1946#define ETH_INT_RX_DONE 0x00000008U
1947
1948#define ETH_INT_TX_UNDERRUN 0x00000010U
1949
1950#define ETH_INT_TX_ERROR 0x00000020U
1951
1952#define ETH_INT_TX_FINISHED 0x00000040U
1953
1954#define ETH_INT_TX_DONE 0x00000080U
1955
1956#define ETH_INT_SOFT 0x00001000U
1957
1958#define ETH_INT_WAKEUP 0x00002000U
1959
1960/* ETH_RX_FIL_CTRL */
1961
1962#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
1963
1964#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
1965
1966#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
1967
1968#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
1969
1970#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
1971
1972#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
1973
1974#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
1975
1976#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
1977
1978/* ETH_CMD */
1979
1980#define ETH_CMD_RX_ENABLE 0x00000001U
1981
1982#define ETH_CMD_TX_ENABLE 0x00000002U
1983
1984#define ETH_CMD_REG_RESET 0x00000008U
1985
1986#define ETH_CMD_TX_RESET 0x00000010U
1987
1988#define ETH_CMD_RX_RESET 0x00000020U
1989
1990#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
1991
1992#define ETH_CMD_PASS_RX_FILTER 0X00000080U
1993
1994#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
1995
1996#define ETH_CMD_RMII 0x00000200U
1997
1998#define ETH_CMD_FULL_DUPLEX 0x00000400U
1999
2000/* ETH_STAT */
2001
2002#define ETH_STAT_RX_ACTIVE 0x00000001U
2003
2004#define ETH_STAT_TX_ACTIVE 0x00000002U
2005
2006/* AHBCFG */
2007
2008#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
2009
2010#define AHBCFG_BREAK_BURST_MASK 0x00000006U
2011
2012#define GET_AHBCFG_BREAK_BURST( reg) \
2013  GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
2014
2015#define SET_AHBCFG_BREAK_BURST( reg, val) \
2016  SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
2017
2018#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
2019
2020#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
2021
2022#define GET_AHBCFG_QUANTUM_SIZE( reg) \
2023  GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
2024
2025#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
2026  SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
2027
2028#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
2029
2030#define GET_AHBCFG_DEFAULT_MASTER( reg) \
2031  GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
2032
2033#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
2034  SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
2035
2036#define AHBCFG_EP1_MASK 0x00007000U
2037
2038#define GET_AHBCFG_EP1( reg) \
2039  GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
2040
2041#define SET_AHBCFG_EP1( reg, val) \
2042  SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
2043
2044#define AHBCFG_EP2_MASK 0x00070000U
2045
2046#define GET_AHBCFG_EP2( reg) \
2047  GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
2048
2049#define SET_AHBCFG_EP2( reg, val) \
2050  SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
2051
2052#define AHBCFG_EP3_MASK 0x00700000U
2053
2054#define GET_AHBCFG_EP3( reg) \
2055  GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
2056
2057#define SET_AHBCFG_EP3( reg, val) \
2058  SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
2059
2060#define AHBCFG_EP4_MASK 0x07000000U
2061
2062#define GET_AHBCFG_EP4( reg) \
2063  GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
2064
2065#define SET_AHBCFG_EP4( reg, val) \
2066  SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
2067
2068#define AHBCFG_EP5_MASK 0x70000000U
2069
2070#define GET_AHBCFG_EP5( reg) \
2071  GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
2072
2073#define SET_AHBCFG_EP5( reg, val) \
2074  SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
2075
2076/* EMC */
2077
2078#define EMC_DYN_CTRL_CE 0x00000001U
2079
2080#define EMC_DYN_CTRL_CS 0x00000002U
2081
2082#define EMC_DYN_CTRL_CMD_NORMAL 0x00000000U
2083
2084#define EMC_DYN_CTRL_CMD_MODE 0x00000080U
2085
2086#define EMC_DYN_CTRL_CMD_PALL 0x00000100U
2087
2088#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
2089
2090/* I2C */
2091
2092typedef struct {
2093  uint32_t conset;
2094  uint32_t stat;
2095  uint32_t dat;
2096  uint32_t adr;
2097  uint32_t sclh;
2098  uint32_t scll;
2099  uint32_t conclr;
2100} lpc24xx_i2c;
2101
2102#define LPC24XX_I2C_AA (1U << 2U)
2103
2104#define LPC24XX_I2C_SI (1U << 3U)
2105
2106#define LPC24XX_I2C_STO (1U << 4U)
2107
2108#define LPC24XX_I2C_STA (1U << 5U)
2109
2110#define LPC24XX_I2C_EN (1U << 6U)
2111
2112/* IO */
2113
2114typedef struct {
2115  uint32_t dir;
2116  uint32_t reserved [3];
2117  uint32_t mask;
2118  uint32_t pin;
2119  uint32_t set;
2120  uint32_t clr;
2121} lpc24xx_fio;
2122
2123static volatile uint32_t * const LPC24XX_PINSEL = &PINSEL0;
2124
2125static volatile uint32_t * const LPC24XX_PINMODE = &PINMODE0;
2126
2127static volatile lpc24xx_fio * const LPC24XX_FIO = (volatile lpc24xx_fio *) FIO_BASE_ADDR;
2128
2129#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
Note: See TracBrowser for help on using the repository browser.