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source: rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h @ 598a4505

4.115

Last change on this file since 598a4505 was 8f60119e, checked in by Sebastian Huber <sebastian.huber@…>, on 10/14/10 at 09:34:06

2010-10-14 Sebastian Huber <sebastian.huber@…>

include/lpc24xx.h, misc/system-clocks.c: Removed superfluous include of <bsp/utility.h>.

Property mode set to 100644

File size: 86.9 KB

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1	/**
2	* @file
3	*
4	* @ingroup lpc24xx_regs
5	*
6	* @brief Register definitions.
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be found in the file
18	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19	*/
20
21	#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
22	#define LIBBSP_ARM_LPC24XX_LPC24XX_H
23
24	#include <stdint.h>
25
26	/**
27	* @defgroup lpc24xx_regs Register Definitions
28	*
29	* @ingroup lpc24xx
30	*
31	* @brief Register definitions.
32	*
33	* @{
34	*/
35
36	/* Vectored Interrupt Controller (VIC) */
37	#define VIC_BASE_ADDR 0xFFFFF000
38	#define VICIRQStatus ((volatile uint32_t ) (VIC_BASE_ADDR + 0x000))
39	#define VICFIQStatus ((volatile uint32_t ) (VIC_BASE_ADDR + 0x004))
40	#define VICRawIntr ((volatile uint32_t ) (VIC_BASE_ADDR + 0x008))
41	#define VICIntSelect ((volatile uint32_t ) (VIC_BASE_ADDR + 0x00C))
42	#define VICIntEnable ((volatile uint32_t ) (VIC_BASE_ADDR + 0x010))
43	#define VICIntEnClear ((volatile uint32_t ) (VIC_BASE_ADDR + 0x014))
44	#define VICSoftInt ((volatile uint32_t ) (VIC_BASE_ADDR + 0x018))
45	#define VICSoftIntClear ((volatile uint32_t ) (VIC_BASE_ADDR + 0x01C))
46	#define VICProtection ((volatile uint32_t ) (VIC_BASE_ADDR + 0x020))
47	#define VICSWPrioMask ((volatile uint32_t ) (VIC_BASE_ADDR + 0x024))
48
49	#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
50	#define VICVectAddr0 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x100))
51	#define VICVectAddr1 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x104))
52	#define VICVectAddr2 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x108))
53	#define VICVectAddr3 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x10C))
54	#define VICVectAddr4 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x110))
55	#define VICVectAddr5 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x114))
56	#define VICVectAddr6 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x118))
57	#define VICVectAddr7 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x11C))
58	#define VICVectAddr8 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x120))
59	#define VICVectAddr9 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x124))
60	#define VICVectAddr10 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x128))
61	#define VICVectAddr11 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x12C))
62	#define VICVectAddr12 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x130))
63	#define VICVectAddr13 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x134))
64	#define VICVectAddr14 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x138))
65	#define VICVectAddr15 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x13C))
66	#define VICVectAddr16 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x140))
67	#define VICVectAddr17 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x144))
68	#define VICVectAddr18 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x148))
69	#define VICVectAddr19 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x14C))
70	#define VICVectAddr20 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x150))
71	#define VICVectAddr21 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x154))
72	#define VICVectAddr22 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x158))
73	#define VICVectAddr23 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x15C))
74	#define VICVectAddr24 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x160))
75	#define VICVectAddr25 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x164))
76	#define VICVectAddr26 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x168))
77	#define VICVectAddr27 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x16C))
78	#define VICVectAddr28 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x170))
79	#define VICVectAddr29 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x174))
80	#define VICVectAddr30 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x178))
81	#define VICVectAddr31 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x17C))
82
83	#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
84	#define VICVectPriority0 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x200))
85	#define VICVectPriority1 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x204))
86	#define VICVectPriority2 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x208))
87	#define VICVectPriority3 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x20C))
88	#define VICVectPriority4 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x210))
89	#define VICVectPriority5 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x214))
90	#define VICVectPriority6 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x218))
91	#define VICVectPriority7 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x21C))
92	#define VICVectPriority8 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x220))
93	#define VICVectPriority9 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x224))
94	#define VICVectPriority10 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x228))
95	#define VICVectPriority11 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x22C))
96	#define VICVectPriority12 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x230))
97	#define VICVectPriority13 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x234))
98	#define VICVectPriority14 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x238))
99	#define VICVectPriority15 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x23C))
100	#define VICVectPriority16 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x240))
101	#define VICVectPriority17 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x244))
102	#define VICVectPriority18 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x248))
103	#define VICVectPriority19 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x24C))
104	#define VICVectPriority20 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x250))
105	#define VICVectPriority21 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x254))
106	#define VICVectPriority22 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x258))
107	#define VICVectPriority23 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x25C))
108	#define VICVectPriority24 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x260))
109	#define VICVectPriority25 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x264))
110	#define VICVectPriority26 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x268))
111	#define VICVectPriority27 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x26C))
112	#define VICVectPriority28 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x270))
113	#define VICVectPriority29 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x274))
114	#define VICVectPriority30 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x278))
115	#define VICVectPriority31 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x27C))
116
117	#define VICVectAddr ((volatile uint32_t ) (VIC_BASE_ADDR + 0xF00))
118
119
120	/* Pin Connect Block */
121	#define PINSEL_BASE_ADDR 0xE002C000
122	#define PINSEL0 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x00))
123	#define PINSEL1 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x04))
124	#define PINSEL2 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x08))
125	#define PINSEL3 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x0C))
126	#define PINSEL4 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x10))
127	#define PINSEL5 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x14))
128	#define PINSEL6 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x18))
129	#define PINSEL7 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x1C))
130	#define PINSEL8 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x20))
131	#define PINSEL9 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x24))
132	#define PINSEL10 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x28))
133	#define PINSEL11 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x2C))
134
135	#define PINMODE0 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x40))
136	#define PINMODE1 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x44))
137	#define PINMODE2 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x48))
138	#define PINMODE3 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x4C))
139	#define PINMODE4 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x50))
140	#define PINMODE5 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x54))
141	#define PINMODE6 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x58))
142	#define PINMODE7 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x5C))
143	#define PINMODE8 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x60))
144	#define PINMODE9 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x64))
145
146	/* General Purpose Input/Output (GPIO) */
147	#define GPIO_BASE_ADDR 0xE0028000
148	#define IOPIN0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x00))
149	#define IOSET0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x04))
150	#define IODIR0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x08))
151	#define IOCLR0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x0C))
152	#define IOPIN1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x10))
153	#define IOSET1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x14))
154	#define IODIR1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x18))
155	#define IOCLR1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x1C))
156
157	/* GPIO Interrupt Registers */
158	#define IO0_INT_EN_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x90))
159	#define IO0_INT_EN_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x94))
160	#define IO0_INT_STAT_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x84))
161	#define IO0_INT_STAT_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x88))
162	#define IO0_INT_CLR ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x8C))
163
164	#define IO2_INT_EN_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xB0))
165	#define IO2_INT_EN_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xB4))
166	#define IO2_INT_STAT_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xA4))
167	#define IO2_INT_STAT_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xA8))
168	#define IO2_INT_CLR ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xAC))
169
170	#define IO_INT_STAT ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x80))
171
172	#define PARTCFG_BASE_ADDR 0x3FFF8000
173	#define PARTCFG ((volatile uint32_t ) (PARTCFG_BASE_ADDR + 0x00))
174
175	/* Fast I/O setup */
176	#define FIO_BASE_ADDR 0x3FFFC000
177	#define FIO0DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x00))
178	#define FIO0MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x10))
179	#define FIO0PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x14))
180	#define FIO0SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x18))
181	#define FIO0CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x1C))
182
183	#define FIO1DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x20))
184	#define FIO1MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x30))
185	#define FIO1PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x34))
186	#define FIO1SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x38))
187	#define FIO1CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x3C))
188
189	#define FIO2DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x40))
190	#define FIO2MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x50))
191	#define FIO2PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x54))
192	#define FIO2SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x58))
193	#define FIO2CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x5C))
194
195	#define FIO3DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x60))
196	#define FIO3MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x70))
197	#define FIO3PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x74))
198	#define FIO3SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x78))
199	#define FIO3CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x7C))
200
201	#define FIO4DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x80))
202	#define FIO4MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x90))
203	#define FIO4PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x94))
204	#define FIO4SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x98))
205	#define FIO4CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x9C))
206
207	/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
208	#define FIO0DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x00))
209	#define FIO1DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x20))
210	#define FIO2DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x40))
211	#define FIO3DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x60))
212	#define FIO4DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x80))
213
214	#define FIO0DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x01))
215	#define FIO1DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x21))
216	#define FIO2DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x41))
217	#define FIO3DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x61))
218	#define FIO4DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x81))
219
220	#define FIO0DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x02))
221	#define FIO1DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x22))
222	#define FIO2DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x42))
223	#define FIO3DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x62))
224	#define FIO4DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x82))
225
226	#define FIO0DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x03))
227	#define FIO1DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x23))
228	#define FIO2DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x43))
229	#define FIO3DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x63))
230	#define FIO4DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x83))
231
232	#define FIO0DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x00))
233	#define FIO1DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x20))
234	#define FIO2DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x40))
235	#define FIO3DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x60))
236	#define FIO4DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x80))
237
238	#define FIO0DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x02))
239	#define FIO1DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x22))
240	#define FIO2DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x42))
241	#define FIO3DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x62))
242	#define FIO4DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x82))
243
244	#define FIO0MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x10))
245	#define FIO1MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x30))
246	#define FIO2MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x50))
247	#define FIO3MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x70))
248	#define FIO4MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x90))
249
250	#define FIO0MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x11))
251	#define FIO1MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x21))
252	#define FIO2MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x51))
253	#define FIO3MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x71))
254	#define FIO4MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x91))
255
256	#define FIO0MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x12))
257	#define FIO1MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x32))
258	#define FIO2MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x52))
259	#define FIO3MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x72))
260	#define FIO4MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x92))
261
262	#define FIO0MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x13))
263	#define FIO1MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x33))
264	#define FIO2MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x53))
265	#define FIO3MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x73))
266	#define FIO4MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x93))
267
268	#define FIO0MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x10))
269	#define FIO1MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x30))
270	#define FIO2MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x50))
271	#define FIO3MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x70))
272	#define FIO4MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x90))
273
274	#define FIO0MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x12))
275	#define FIO1MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x32))
276	#define FIO2MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x52))
277	#define FIO3MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x72))
278	#define FIO4MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x92))
279
280	#define FIO0PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x14))
281	#define FIO1PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x34))
282	#define FIO2PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x54))
283	#define FIO3PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x74))
284	#define FIO4PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x94))
285
286	#define FIO0PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x15))
287	#define FIO1PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x25))
288	#define FIO2PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x55))
289	#define FIO3PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x75))
290	#define FIO4PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x95))
291
292	#define FIO0PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x16))
293	#define FIO1PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x36))
294	#define FIO2PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x56))
295	#define FIO3PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x76))
296	#define FIO4PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x96))
297
298	#define FIO0PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x17))
299	#define FIO1PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x37))
300	#define FIO2PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x57))
301	#define FIO3PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x77))
302	#define FIO4PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x97))
303
304	#define FIO0PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x14))
305	#define FIO1PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x34))
306	#define FIO2PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x54))
307	#define FIO3PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x74))
308	#define FIO4PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x94))
309
310	#define FIO0PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x16))
311	#define FIO1PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x36))
312	#define FIO2PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x56))
313	#define FIO3PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x76))
314	#define FIO4PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x96))
315
316	#define FIO0SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x18))
317	#define FIO1SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x38))
318	#define FIO2SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x58))
319	#define FIO3SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x78))
320	#define FIO4SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x98))
321
322	#define FIO0SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x19))
323	#define FIO1SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x29))
324	#define FIO2SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x59))
325	#define FIO3SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x79))
326	#define FIO4SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x99))
327
328	#define FIO0SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1A))
329	#define FIO1SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3A))
330	#define FIO2SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5A))
331	#define FIO3SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7A))
332	#define FIO4SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9A))
333
334	#define FIO0SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1B))
335	#define FIO1SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3B))
336	#define FIO2SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5B))
337	#define FIO3SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7B))
338	#define FIO4SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9B))
339
340	#define FIO0SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x18))
341	#define FIO1SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x38))
342	#define FIO2SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x58))
343	#define FIO3SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x78))
344	#define FIO4SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x98))
345
346	#define FIO0SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1A))
347	#define FIO1SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3A))
348	#define FIO2SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5A))
349	#define FIO3SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7A))
350	#define FIO4SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9A))
351
352	#define FIO0CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1C))
353	#define FIO1CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3C))
354	#define FIO2CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5C))
355	#define FIO3CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7C))
356	#define FIO4CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9C))
357
358	#define FIO0CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1D))
359	#define FIO1CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x2D))
360	#define FIO2CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5D))
361	#define FIO3CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7D))
362	#define FIO4CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9D))
363
364	#define FIO0CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1E))
365	#define FIO1CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3E))
366	#define FIO2CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5E))
367	#define FIO3CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7E))
368	#define FIO4CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9E))
369
370	#define FIO0CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1F))
371	#define FIO1CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3F))
372	#define FIO2CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5F))
373	#define FIO3CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7F))
374	#define FIO4CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9F))
375
376	#define FIO0CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1C))
377	#define FIO1CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3C))
378	#define FIO2CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5C))
379	#define FIO3CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7C))
380	#define FIO4CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9C))
381
382	#define FIO0CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1E))
383	#define FIO1CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3E))
384	#define FIO2CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5E))
385	#define FIO3CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7E))
386	#define FIO4CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9E))
387
388
389	/* System Control Block(SCB) modules include Memory Accelerator Module,
390	Phase Locked Loop, VPB divider, Power Control, External Interrupt,
391	Reset, and Code Security/Debugging */
392	#define SCB_BASE_ADDR 0xE01FC000
393
394	/* Memory Accelerator Module (MAM) */
395	#define MAMCR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x000))
396	#define MAMTIM ((volatile uint32_t ) (SCB_BASE_ADDR + 0x004))
397	#define MEMMAP ((volatile uint32_t ) (SCB_BASE_ADDR + 0x040))
398
399	/* Phase Locked Loop (PLL) */
400	#define PLLCON ((volatile uint32_t ) (SCB_BASE_ADDR + 0x080))
401	#define PLLCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x084))
402	#define PLLSTAT ((volatile uint32_t ) (SCB_BASE_ADDR + 0x088))
403	#define PLLFEED ((volatile uint32_t ) (SCB_BASE_ADDR + 0x08C))
404
405	/* Power Control */
406	#define PCON ((volatile uint32_t ) (SCB_BASE_ADDR + 0x0C0))
407	#define PCONP ((volatile uint32_t ) (SCB_BASE_ADDR + 0x0C4))
408
409	/* Clock Divider */
410	// #define APBDIV ((volatile uint32_t ) (SCB_BASE_ADDR + 0x100))
411	#define CCLKCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x104))
412	#define USBCLKCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x108))
413	#define CLKSRCSEL ((volatile uint32_t ) (SCB_BASE_ADDR + 0x10C))
414	#define PCLKSEL0 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1A8))
415	#define PCLKSEL1 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1AC))
416
417	/* External Interrupts */
418	#define EXTINT ((volatile uint32_t ) (SCB_BASE_ADDR + 0x140))
419	#define INTWAKE ((volatile uint32_t ) (SCB_BASE_ADDR + 0x144))
420	#define EXTMODE ((volatile uint32_t ) (SCB_BASE_ADDR + 0x148))
421	#define EXTPOLAR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x14C))
422
423	/* Reset, reset source identification */
424	#define RSIR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x180))
425
426	/* RSID, code security protection */
427	#define CSPR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x184))
428
429	/* AHB configuration */
430	#define AHBCFG1 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x188))
431	#define AHBCFG2 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x18C))
432
433	/* System Controls and Status */
434	#define SCS ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1A0))
435
436
437	/* External Memory Controller (EMC) */
438	#define EMC_BASE_ADDR 0xFFE08000
439	#define EMC_CTRL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x000))
440	#define EMC_STAT ((volatile uint32_t ) (EMC_BASE_ADDR + 0x004))
441	#define EMC_CONFIG ((volatile uint32_t ) (EMC_BASE_ADDR + 0x008))
442
443	/* Dynamic RAM access registers */
444	#define EMC_DYN_CTRL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x020))
445	#define EMC_DYN_RFSH ((volatile uint32_t ) (EMC_BASE_ADDR + 0x024))
446	#define EMC_DYN_RD_CFG ((volatile uint32_t ) (EMC_BASE_ADDR + 0x028))
447	#define EMC_DYN_RP ((volatile uint32_t ) (EMC_BASE_ADDR + 0x030))
448	#define EMC_DYN_RAS ((volatile uint32_t ) (EMC_BASE_ADDR + 0x034))
449	#define EMC_DYN_SREX ((volatile uint32_t ) (EMC_BASE_ADDR + 0x038))
450	#define EMC_DYN_APR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x03C))
451	#define EMC_DYN_DAL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x040))
452	#define EMC_DYN_WR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x044))
453	#define EMC_DYN_RC ((volatile uint32_t ) (EMC_BASE_ADDR + 0x048))
454	#define EMC_DYN_RFC ((volatile uint32_t ) (EMC_BASE_ADDR + 0x04C))
455	#define EMC_DYN_XSR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x050))
456	#define EMC_DYN_RRD ((volatile uint32_t ) (EMC_BASE_ADDR + 0x054))
457	#define EMC_DYN_MRD ((volatile uint32_t ) (EMC_BASE_ADDR + 0x058))
458
459	#define EMC_DYN_CFG0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x100))
460	#define EMC_DYN_RASCAS0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x104))
461	#define EMC_DYN_CFG1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x140))
462	#define EMC_DYN_RASCAS1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x144))
463	#define EMC_DYN_CFG2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x160))
464	#define EMC_DYN_RASCAS2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x164))
465	#define EMC_DYN_CFG3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x180))
466	#define EMC_DYN_RASCAS3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x184))
467
468	/* static RAM access registers */
469	#define EMC_STA_BASE_0 ((uint32_t *) (EMC_BASE_ADDR + 0x200))
470	#define EMC_STA_CFG0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x200))
471	#define EMC_STA_WAITWEN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x204))
472	#define EMC_STA_WAITOEN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x208))
473	#define EMC_STA_WAITRD0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x20C))
474	#define EMC_STA_WAITPAGE0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x210))
475	#define EMC_STA_WAITWR0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x214))
476	#define EMC_STA_WAITTURN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x218))
477
478	#define EMC_STA_BASE_1 ((uint32_t *) (EMC_BASE_ADDR + 0x220))
479	#define EMC_STA_CFG1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x220))
480	#define EMC_STA_WAITWEN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x224))
481	#define EMC_STA_WAITOEN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x228))
482	#define EMC_STA_WAITRD1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x22C))
483	#define EMC_STA_WAITPAGE1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x230))
484	#define EMC_STA_WAITWR1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x234))
485	#define EMC_STA_WAITTURN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x238))
486
487	#define EMC_STA_BASE_2 ((uint32_t *) (EMC_BASE_ADDR + 0x240))
488	#define EMC_STA_CFG2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x240))
489	#define EMC_STA_WAITWEN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x244))
490	#define EMC_STA_WAITOEN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x248))
491	#define EMC_STA_WAITRD2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x24C))
492	#define EMC_STA_WAITPAGE2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x250))
493	#define EMC_STA_WAITWR2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x254))
494	#define EMC_STA_WAITTURN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x258))
495
496	#define EMC_STA_BASE_3 ((uint32_t *) (EMC_BASE_ADDR + 0x260))
497	#define EMC_STA_CFG3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x260))
498	#define EMC_STA_WAITWEN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x264))
499	#define EMC_STA_WAITOEN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x268))
500	#define EMC_STA_WAITRD3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x26C))
501	#define EMC_STA_WAITPAGE3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x270))
502	#define EMC_STA_WAITWR3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x274))
503	#define EMC_STA_WAITTURN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x278))
504
505	#define EMC_STA_EXT_WAIT ((volatile uint32_t ) (EMC_BASE_ADDR + 0x880))
506
507
508	/* Timer 0 */
509	#define TMR0_BASE_ADDR 0xE0004000
510	#define T0IR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x00))
511	#define T0TCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x04))
512	#define T0TC ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x08))
513	#define T0PR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x0C))
514	#define T0PC ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x10))
515	#define T0MCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x14))
516	#define T0MR0 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x18))
517	#define T0MR1 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x1C))
518	#define T0MR2 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x20))
519	#define T0MR3 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x24))
520	#define T0CCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x28))
521	#define T0CR0 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x2C))
522	#define T0CR1 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x30))
523	#define T0CR2 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x34))
524	#define T0CR3 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x38))
525	#define T0EMR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x3C))
526	#define T0CTCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x70))
527
528	/* Timer 1 */
529	#define TMR1_BASE_ADDR 0xE0008000
530	#define T1IR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x00))
531	#define T1TCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x04))
532	#define T1TC ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x08))
533	#define T1PR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x0C))
534	#define T1PC ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x10))
535	#define T1MCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x14))
536	#define T1MR0 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x18))
537	#define T1MR1 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x1C))
538	#define T1MR2 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x20))
539	#define T1MR3 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x24))
540	#define T1CCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x28))
541	#define T1CR0 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x2C))
542	#define T1CR1 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x30))
543	#define T1CR2 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x34))
544	#define T1CR3 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x38))
545	#define T1EMR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x3C))
546	#define T1CTCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x70))
547
548	/* Timer 2 */
549	#define TMR2_BASE_ADDR 0xE0070000
550	#define T2IR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x00))
551	#define T2TCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x04))
552	#define T2TC ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x08))
553	#define T2PR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x0C))
554	#define T2PC ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x10))
555	#define T2MCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x14))
556	#define T2MR0 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x18))
557	#define T2MR1 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x1C))
558	#define T2MR2 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x20))
559	#define T2MR3 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x24))
560	#define T2CCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x28))
561	#define T2CR0 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x2C))
562	#define T2CR1 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x30))
563	#define T2CR2 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x34))
564	#define T2CR3 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x38))
565	#define T2EMR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x3C))
566	#define T2CTCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x70))
567
568	/* Timer 3 */
569	#define TMR3_BASE_ADDR 0xE0074000
570	#define T3IR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x00))
571	#define T3TCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x04))
572	#define T3TC ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x08))
573	#define T3PR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x0C))
574	#define T3PC ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x10))
575	#define T3MCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x14))
576	#define T3MR0 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x18))
577	#define T3MR1 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x1C))
578	#define T3MR2 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x20))
579	#define T3MR3 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x24))
580	#define T3CCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x28))
581	#define T3CR0 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x2C))
582	#define T3CR1 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x30))
583	#define T3CR2 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x34))
584	#define T3CR3 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x38))
585	#define T3EMR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x3C))
586	#define T3CTCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x70))
587
588
589	/* Pulse Width Modulator (PWM) */
590	#define PWM0_BASE_ADDR 0xE0014000
591	#define PWM0IR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x00))
592	#define PWM0TCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x04))
593	#define PWM0TC ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x08))
594	#define PWM0PR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x0C))
595	#define PWM0PC ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x10))
596	#define PWM0MCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x14))
597	#define PWM0MR0 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x18))
598	#define PWM0MR1 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x1C))
599	#define PWM0MR2 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x20))
600	#define PWM0MR3 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x24))
601	#define PWM0CCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x28))
602	#define PWM0CR0 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x2C))
603	#define PWM0CR1 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x30))
604	#define PWM0CR2 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x34))
605	#define PWM0CR3 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x38))
606	#define PWM0EMR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x3C))
607	#define PWM0MR4 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x40))
608	#define PWM0MR5 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x44))
609	#define PWM0MR6 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x48))
610	#define PWM0PCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x4C))
611	#define PWM0LER ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x50))
612	#define PWM0CTCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x70))
613
614	#define PWM1_BASE_ADDR 0xE0018000
615	#define PWM1IR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x00))
616	#define PWM1TCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x04))
617	#define PWM1TC ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x08))
618	#define PWM1PR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x0C))
619	#define PWM1PC ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x10))
620	#define PWM1MCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x14))
621	#define PWM1MR0 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x18))
622	#define PWM1MR1 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x1C))
623	#define PWM1MR2 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x20))
624	#define PWM1MR3 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x24))
625	#define PWM1CCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x28))
626	#define PWM1CR0 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x2C))
627	#define PWM1CR1 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x30))
628	#define PWM1CR2 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x34))
629	#define PWM1CR3 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x38))
630	#define PWM1EMR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x3C))
631	#define PWM1MR4 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x40))
632	#define PWM1MR5 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x44))
633	#define PWM1MR6 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x48))
634	#define PWM1PCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x4C))
635	#define PWM1LER ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x50))
636	#define PWM1CTCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x70))
637
638
639	/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
640	#define UART0_BASE_ADDR 0xE000C000
641	#define U0RBR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
642	#define U0THR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
643	#define U0DLL ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
644	#define U0DLM ((volatile uint32_t ) (UART0_BASE_ADDR + 0x04))
645	#define U0IER ((volatile uint32_t ) (UART0_BASE_ADDR + 0x04))
646	#define U0IIR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x08))
647	#define U0FCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x08))
648	#define U0LCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x0C))
649	#define U0LSR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x14))
650	#define U0SCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x1C))
651	#define U0ACR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x20))
652	#define U0ICR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x24))
653	#define U0FDR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x28))
654	#define U0TER ((volatile uint32_t ) (UART0_BASE_ADDR + 0x30))
655
656	/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
657	#define UART1_BASE_ADDR 0xE0010000
658	#define U1RBR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
659	#define U1THR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
660	#define U1DLL ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
661	#define U1DLM ((volatile uint32_t ) (UART1_BASE_ADDR + 0x04))
662	#define U1IER ((volatile uint32_t ) (UART1_BASE_ADDR + 0x04))
663	#define U1IIR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x08))
664	#define U1FCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x08))
665	#define U1LCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x0C))
666	#define U1MCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x10))
667	#define U1LSR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x14))
668	#define U1MSR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x18))
669	#define U1SCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x1C))
670	#define U1ACR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x20))
671	#define U1FDR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x28))
672	#define U1TER ((volatile uint32_t ) (UART1_BASE_ADDR + 0x30))
673
674	/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
675	#define UART2_BASE_ADDR 0xE0078000
676	#define U2RBR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
677	#define U2THR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
678	#define U2DLL ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
679	#define U2DLM ((volatile uint32_t ) (UART2_BASE_ADDR + 0x04))
680	#define U2IER ((volatile uint32_t ) (UART2_BASE_ADDR + 0x04))
681	#define U2IIR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x08))
682	#define U2FCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x08))
683	#define U2LCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x0C))
684	#define U2LSR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x14))
685	#define U2SCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x1C))
686	#define U2ACR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x20))
687	#define U2ICR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x24))
688	#define U2FDR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x28))
689	#define U2TER ((volatile uint32_t ) (UART2_BASE_ADDR + 0x30))
690
691	/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
692	#define UART3_BASE_ADDR 0xE007C000
693	#define U3RBR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
694	#define U3THR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
695	#define U3DLL ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
696	#define U3DLM ((volatile uint32_t ) (UART3_BASE_ADDR + 0x04))
697	#define U3IER ((volatile uint32_t ) (UART3_BASE_ADDR + 0x04))
698	#define U3IIR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x08))
699	#define U3FCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x08))
700	#define U3LCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x0C))
701	#define U3LSR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x14))
702	#define U3SCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x1C))
703	#define U3ACR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x20))
704	#define U3ICR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x24))
705	#define U3FDR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x28))
706	#define U3TER ((volatile uint32_t ) (UART3_BASE_ADDR + 0x30))
707
708	/* I2C Interface 0 */
709	#define I2C0_BASE_ADDR 0xE001C000
710	#define I20CONSET ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x00))
711	#define I20STAT ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x04))
712	#define I20DAT ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x08))
713	#define I20ADR ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x0C))
714	#define I20SCLH ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x10))
715	#define I20SCLL ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x14))
716	#define I20CONCLR ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x18))
717
718	/* I2C Interface 1 */
719	#define I2C1_BASE_ADDR 0xE005C000
720	#define I21CONSET ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x00))
721	#define I21STAT ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x04))
722	#define I21DAT ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x08))
723	#define I21ADR ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x0C))
724	#define I21SCLH ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x10))
725	#define I21SCLL ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x14))
726	#define I21CONCLR ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x18))
727
728	/* I2C Interface 2 */
729	#define I2C2_BASE_ADDR 0xE0080000
730	#define I22CONSET ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x00))
731	#define I22STAT ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x04))
732	#define I22DAT ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x08))
733	#define I22ADR ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x0C))
734	#define I22SCLH ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x10))
735	#define I22SCLL ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x14))
736	#define I22CONCLR ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x18))
737
738	/* SPI0 (Serial Peripheral Interface 0) */
739	#define SPI0_BASE_ADDR 0xE0020000
740	#define S0SPCR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x00))
741	#define S0SPSR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x04))
742	#define S0SPDR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x08))
743	#define S0SPCCR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x0C))
744	#define S0SPINT ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x1C))
745
746	/* SSP0 Controller */
747	#define SSP0_BASE_ADDR 0xE0068000
748	#define SSP0CR0 ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x00))
749	#define SSP0CR1 ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x04))
750	#define SSP0DR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x08))
751	#define SSP0SR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x0C))
752	#define SSP0CPSR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x10))
753	#define SSP0IMSC ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x14))
754	#define SSP0RIS ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x18))
755	#define SSP0MIS ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x1C))
756	#define SSP0ICR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x20))
757	#define SSP0DMACR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x24))
758
759	/* SSP1 Controller */
760	#define SSP1_BASE_ADDR 0xE0030000
761	#define SSP1CR0 ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x00))
762	#define SSP1CR1 ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x04))
763	#define SSP1DR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x08))
764	#define SSP1SR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x0C))
765	#define SSP1CPSR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x10))
766	#define SSP1IMSC ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x14))
767	#define SSP1RIS ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x18))
768	#define SSP1MIS ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x1C))
769	#define SSP1ICR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x20))
770	#define SSP1DMACR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x24))
771
772
773	/* Real Time Clock */
774	#define RTC_BASE_ADDR 0xE0024000
775	#define RTC_ILR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x00))
776	#define RTC_CTC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x04))
777	#define RTC_CCR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x08))
778	#define RTC_CIIR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x0C))
779	#define RTC_AMR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x10))
780	#define RTC_CTIME0 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x14))
781	#define RTC_CTIME1 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x18))
782	#define RTC_CTIME2 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x1C))
783	#define RTC_SEC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x20))
784	#define RTC_MIN ((volatile uint32_t ) (RTC_BASE_ADDR + 0x24))
785	#define RTC_HOUR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x28))
786	#define RTC_DOM ((volatile uint32_t ) (RTC_BASE_ADDR + 0x2C))
787	#define RTC_DOW ((volatile uint32_t ) (RTC_BASE_ADDR + 0x30))
788	#define RTC_DOY ((volatile uint32_t ) (RTC_BASE_ADDR + 0x34))
789	#define RTC_MONTH ((volatile uint32_t ) (RTC_BASE_ADDR + 0x38))
790	#define RTC_YEAR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x3C))
791	#define RTC_CISS ((volatile uint32_t ) (RTC_BASE_ADDR + 0x40))
792	#define RTC_ALSEC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x60))
793	#define RTC_ALMIN ((volatile uint32_t ) (RTC_BASE_ADDR + 0x64))
794	#define RTC_ALHOUR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x68))
795	#define RTC_ALDOM ((volatile uint32_t ) (RTC_BASE_ADDR + 0x6C))
796	#define RTC_ALDOW ((volatile uint32_t ) (RTC_BASE_ADDR + 0x70))
797	#define RTC_ALDOY ((volatile uint32_t ) (RTC_BASE_ADDR + 0x74))
798	#define RTC_ALMON ((volatile uint32_t ) (RTC_BASE_ADDR + 0x78))
799	#define RTC_ALYEAR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x7C))
800	#define RTC_PREINT ((volatile uint32_t ) (RTC_BASE_ADDR + 0x80))
801	#define RTC_PREFRAC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x84))
802
803
804	/* A/D Converter 0 (AD0) */
805	#define AD0_BASE_ADDR 0xE0034000
806	#define AD0CR ((volatile uint32_t ) (AD0_BASE_ADDR + 0x00))
807	#define AD0GDR ((volatile uint32_t ) (AD0_BASE_ADDR + 0x04))
808	#define AD0INTEN ((volatile uint32_t ) (AD0_BASE_ADDR + 0x0C))
809	#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
810	#define AD0DR0 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x10))
811	#define AD0DR1 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x14))
812	#define AD0DR2 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x18))
813	#define AD0DR3 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x1C))
814	#define AD0DR4 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x20))
815	#define AD0DR5 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x24))
816	#define AD0DR6 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x28))
817	#define AD0DR7 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x2C))
818	#define AD0STAT ((volatile uint32_t ) (AD0_BASE_ADDR + 0x30))
819
820
821	/* D/A Converter */
822	#define DAC_BASE_ADDR 0xE006C000
823	#define DACR ((volatile uint32_t ) (DAC_BASE_ADDR + 0x00))
824
825
826	/* Watchdog */
827	#define WDG_BASE_ADDR 0xE0000000
828	#define WDMOD ((volatile uint32_t ) (WDG_BASE_ADDR + 0x00))
829	#define WDTC ((volatile uint32_t ) (WDG_BASE_ADDR + 0x04))
830	#define WDFEED ((volatile uint32_t ) (WDG_BASE_ADDR + 0x08))
831	#define WDTV ((volatile uint32_t ) (WDG_BASE_ADDR + 0x0C))
832	#define WDCLKSEL ((volatile uint32_t ) (WDG_BASE_ADDR + 0x10))
833
834	/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
835	#define CAN_ACCEPT_BASE_ADDR 0xE003C000
836	#define CAN_AFMR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x00))
837	#define CAN_SFF_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x04))
838	#define CAN_SFF_GRP_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x08))
839	#define CAN_EFF_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x0C))
840	#define CAN_EFF_GRP_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x10))
841	#define CAN_EOT ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x14))
842	#define CAN_LUT_ERR_ADR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x18))
843	#define CAN_LUT_ERR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x1C))
844
845	#define CAN_CENTRAL_BASE_ADDR 0xE0040000
846	#define CAN_TX_SR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x00))
847	#define CAN_RX_SR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x04))
848	#define CAN_MSR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x08))
849
850	#define CAN1_BASE_ADDR 0xE0044000
851	#define CAN1MOD ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x00))
852	#define CAN1CMR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x04))
853	#define CAN1GSR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x08))
854	#define CAN1ICR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x0C))
855	#define CAN1IER ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x10))
856	#define CAN1BTR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x14))
857	#define CAN1EWL ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x18))
858	#define CAN1SR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x1C))
859	#define CAN1RFS ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x20))
860	#define CAN1RID ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x24))
861	#define CAN1RDA ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x28))
862	#define CAN1RDB ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x2C))
863
864	#define CAN1TFI1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x30))
865	#define CAN1TID1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x34))
866	#define CAN1TDA1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x38))
867	#define CAN1TDB1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x3C))
868	#define CAN1TFI2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x40))
869	#define CAN1TID2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x44))
870	#define CAN1TDA2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x48))
871	#define CAN1TDB2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x4C))
872	#define CAN1TFI3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x50))
873	#define CAN1TID3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x54))
874	#define CAN1TDA3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x58))
875	#define CAN1TDB3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x5C))
876
877	#define CAN2_BASE_ADDR 0xE0048000
878	#define CAN2MOD ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x00))
879	#define CAN2CMR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x04))
880	#define CAN2GSR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x08))
881	#define CAN2ICR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x0C))
882	#define CAN2IER ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x10))
883	#define CAN2BTR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x14))
884	#define CAN2EWL ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x18))
885	#define CAN2SR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x1C))
886	#define CAN2RFS ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x20))
887	#define CAN2RID ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x24))
888	#define CAN2RDA ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x28))
889	#define CAN2RDB ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x2C))
890
891	#define CAN2TFI1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x30))
892	#define CAN2TID1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x34))
893	#define CAN2TDA1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x38))
894	#define CAN2TDB1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x3C))
895	#define CAN2TFI2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x40))
896	#define CAN2TID2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x44))
897	#define CAN2TDA2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x48))
898	#define CAN2TDB2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x4C))
899	#define CAN2TFI3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x50))
900	#define CAN2TID3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x54))
901	#define CAN2TDA3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x58))
902	#define CAN2TDB3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x5C))
903
904
905	/* MultiMedia Card Interface(MCI) Controller */
906	#define MCI_BASE_ADDR 0xE008C000
907	#define MCI_POWER ((volatile uint32_t ) (MCI_BASE_ADDR + 0x00))
908	#define MCI_CLOCK ((volatile uint32_t ) (MCI_BASE_ADDR + 0x04))
909	#define MCI_ARGUMENT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x08))
910	#define MCI_COMMAND ((volatile uint32_t ) (MCI_BASE_ADDR + 0x0C))
911	#define MCI_RESP_CMD ((volatile uint32_t ) (MCI_BASE_ADDR + 0x10))
912	#define MCI_RESP0 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x14))
913	#define MCI_RESP1 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x18))
914	#define MCI_RESP2 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x1C))
915	#define MCI_RESP3 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x20))
916	#define MCI_DATA_TMR ((volatile uint32_t ) (MCI_BASE_ADDR + 0x24))
917	#define MCI_DATA_LEN ((volatile uint32_t ) (MCI_BASE_ADDR + 0x28))
918	#define MCI_DATA_CTRL ((volatile uint32_t ) (MCI_BASE_ADDR + 0x2C))
919	#define MCI_DATA_CNT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x30))
920	#define MCI_STATUS ((volatile uint32_t ) (MCI_BASE_ADDR + 0x34))
921	#define MCI_CLEAR ((volatile uint32_t ) (MCI_BASE_ADDR + 0x38))
922	#define MCI_MASK0 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x3C))
923	#define MCI_MASK1 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x40))
924	#define MCI_FIFO_CNT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x48))
925	#define MCI_FIFO ((volatile uint32_t ) (MCI_BASE_ADDR + 0x80))
926
927
928	/* I2S Interface Controller (I2S) */
929	#define I2S_BASE_ADDR 0xE0088000
930	#define I2S_DAO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x00))
931	#define I2S_DAI ((volatile uint32_t ) (I2S_BASE_ADDR + 0x04))
932	#define I2S_TX_FIFO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x08))
933	#define I2S_RX_FIFO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x0C))
934	#define I2S_STATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x10))
935	#define I2S_DMA1 ((volatile uint32_t ) (I2S_BASE_ADDR + 0x14))
936	#define I2S_DMA2 ((volatile uint32_t ) (I2S_BASE_ADDR + 0x18))
937	#define I2S_IRQ ((volatile uint32_t ) (I2S_BASE_ADDR + 0x1C))
938	#define I2S_TXRATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x20))
939	#define I2S_RXRATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x24))
940
941
942	/* General-purpose DMA Controller */
943	#define DMA_BASE_ADDR 0xFFE04000
944	#define GPDMA_INT_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x000))
945	#define GPDMA_INT_TCSTAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x004))
946	#define GPDMA_INT_TCCLR ((volatile uint32_t ) (DMA_BASE_ADDR + 0x008))
947	#define GPDMA_INT_ERR_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x00C))
948	#define GPDMA_INT_ERR_CLR ((volatile uint32_t ) (DMA_BASE_ADDR + 0x010))
949	#define GPDMA_RAW_INT_TCSTAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x014))
950	#define GPDMA_RAW_INT_ERR_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x018))
951	#define GPDMA_ENABLED_CHNS ((volatile uint32_t ) (DMA_BASE_ADDR + 0x01C))
952	#define GPDMA_SOFT_BREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x020))
953	#define GPDMA_SOFT_SREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x024))
954	#define GPDMA_SOFT_LBREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x028))
955	#define GPDMA_SOFT_LSREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x02C))
956	#define GPDMA_CONFIG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x030))
957	#define GPDMA_SYNC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x034))
958
959	/* DMA channel 0 registers */
960	#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
961	#define GPDMA_CH0_SRC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x100))
962	#define GPDMA_CH0_DEST ((volatile uint32_t ) (DMA_BASE_ADDR + 0x104))
963	#define GPDMA_CH0_LLI ((volatile uint32_t ) (DMA_BASE_ADDR + 0x108))
964	#define GPDMA_CH0_CTRL ((volatile uint32_t ) (DMA_BASE_ADDR + 0x10C))
965	#define GPDMA_CH0_CFG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x110))
966
967	/* DMA channel 1 registers */
968	#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
969	#define GPDMA_CH1_SRC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x120))
970	#define GPDMA_CH1_DEST ((volatile uint32_t ) (DMA_BASE_ADDR + 0x124))
971	#define GPDMA_CH1_LLI ((volatile uint32_t ) (DMA_BASE_ADDR + 0x128))
972	#define GPDMA_CH1_CTRL ((volatile uint32_t ) (DMA_BASE_ADDR + 0x12C))
973	#define GPDMA_CH1_CFG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x130))
974
975
976	/* USB Controller */
977	#define USB_INT_BASE_ADDR 0xE01FC1C0
978	#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
979
980	#define USB_INT_STAT ((volatile uint32_t ) (USB_INT_BASE_ADDR + 0x00))
981
982	/* USB Device Interrupt Registers */
983	#define DEV_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x00))
984	#define DEV_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x04))
985	#define DEV_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x08))
986	#define DEV_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x0C))
987	#define DEV_INT_PRIO ((volatile uint32_t ) (USB_BASE_ADDR + 0x2C))
988
989	/* USB Device Endpoint Interrupt Registers */
990	#define EP_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x30))
991	#define EP_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x34))
992	#define EP_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x38))
993	#define EP_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x3C))
994	#define EP_INT_PRIO ((volatile uint32_t ) (USB_BASE_ADDR + 0x40))
995
996	/* USB Device Endpoint Realization Registers */
997	#define REALIZE_EP ((volatile uint32_t ) (USB_BASE_ADDR + 0x44))
998	#define EP_INDEX ((volatile uint32_t ) (USB_BASE_ADDR + 0x48))
999	#define MAXPACKET_SIZE ((volatile uint32_t ) (USB_BASE_ADDR + 0x4C))
1000
1001	/* USB Device Command Reagisters */
1002	#define CMD_CODE ((volatile uint32_t ) (USB_BASE_ADDR + 0x10))
1003	#define CMD_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x14))
1004
1005	/* USB Device Data Transfer Registers */
1006	#define RX_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x18))
1007	#define TX_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x1C))
1008	#define RX_PLENGTH ((volatile uint32_t ) (USB_BASE_ADDR + 0x20))
1009	#define TX_PLENGTH ((volatile uint32_t ) (USB_BASE_ADDR + 0x24))
1010	#define USB_CTRL ((volatile uint32_t ) (USB_BASE_ADDR + 0x28))
1011
1012	/* USB Device DMA Registers */
1013	#define DMA_REQ_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x50))
1014	#define DMA_REQ_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x54))
1015	#define DMA_REQ_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x58))
1016	#define UDCA_HEAD ((volatile uint32_t ) (USB_BASE_ADDR + 0x80))
1017	#define EP_DMA_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x84))
1018	#define EP_DMA_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x88))
1019	#define EP_DMA_DIS ((volatile uint32_t ) (USB_BASE_ADDR + 0x8C))
1020	#define DMA_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x90))
1021	#define DMA_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x94))
1022	#define EOT_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xA0))
1023	#define EOT_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xA4))
1024	#define EOT_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xA8))
1025	#define NDD_REQ_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xAC))
1026	#define NDD_REQ_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xB0))
1027	#define NDD_REQ_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xB4))
1028	#define SYS_ERR_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xB8))
1029	#define SYS_ERR_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xBC))
1030	#define SYS_ERR_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xC0))
1031
1032
1033	/* USB Host Controller */
1034	#define USBHC_BASE_ADDR 0xFFE0C000
1035	#define HC_REVISION ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x00))
1036	#define HC_CONTROL ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x04))
1037	#define HC_CMD_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x08))
1038	#define HC_INT_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x0C))
1039	#define HC_INT_EN ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x10))
1040	#define HC_INT_DIS ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x14))
1041	#define HC_HCCA ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x18))
1042	#define HC_PERIOD_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x1C))
1043	#define HC_CTRL_HEAD_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x20))
1044	#define HC_CTRL_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x24))
1045	#define HC_BULK_HEAD_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x28))
1046	#define HC_BULK_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x2C))
1047	#define HC_DONE_HEAD ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x30))
1048	#define HC_FM_INTERVAL ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x34))
1049	#define HC_FM_REMAINING ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x38))
1050	#define HC_FM_NUMBER ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x3C))
1051	#define HC_PERIOD_START ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x40))
1052	#define HC_LS_THRHLD ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x44))
1053	#define HC_RH_DESCA ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x48))
1054	#define HC_RH_DESCB ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x4C))
1055	#define HC_RH_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x50))
1056	#define HC_RH_PORT_STAT1 ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x54))
1057	#define HC_RH_PORT_STAT2 ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x58))
1058
1059	/* USB OTG Controller */
1060	#define USBOTG_BASE_ADDR 0xFFE0C100
1061	#define OTG_INT_STAT ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x00))
1062	#define OTG_INT_EN ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x04))
1063	#define OTG_INT_SET ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x08))
1064	#define OTG_INT_CLR ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x0C))
1065	#define OTG_STAT_CTRL ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x10))
1066	#define OTG_TIMER ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x14))
1067
1068	#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1069	#define OTG_I2C_RX ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x00))
1070	#define OTG_I2C_TX ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x00))
1071	#define OTG_I2C_STS ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x04))
1072	#define OTG_I2C_CTL ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x08))
1073	#define OTG_I2C_CLKHI ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x0C))
1074	#define OTG_I2C_CLKLO ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x10))
1075
1076	#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1077	#define OTG_CLK_CTRL ((volatile uint32_t ) (USBOTG_CLK_BASE_ADDR + 0x04))
1078	#define OTG_CLK_STAT ((volatile uint32_t ) (USBOTG_CLK_BASE_ADDR + 0x08))
1079
1080
1081	/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1082	#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
1083	#define MAC_MAC1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1084	#define MAC_MAC2 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1085	#define MAC_IPGT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1086	#define MAC_IPGR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1087	#define MAC_CLRT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1088	#define MAC_MAXF ((volatile uint32_t ) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1089	#define MAC_SUPP ((volatile uint32_t ) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1090	#define MAC_TEST ((volatile uint32_t ) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1091	#define MAC_MCFG ((volatile uint32_t ) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1092	#define MAC_MCMD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1093	#define MAC_MADR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1094	#define MAC_MWTD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1095	#define MAC_MRDD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1096	#define MAC_MIND ((volatile uint32_t ) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1097
1098	#define MAC_SA0 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1099	#define MAC_SA1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1100	#define MAC_SA2 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1101
1102	#define MAC_COMMAND ((volatile uint32_t ) (MAC_BASE_ADDR + 0x100)) /* Command reg */
1103	#define MAC_STATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1104	#define MAC_RXDESCRIPTOR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1105	#define MAC_RXSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1106	#define MAC_RXDESCRIPTORNUM ((volatile uint32_t ) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1107	#define MAC_RXPRODUCEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1108	#define MAC_RXCONSUMEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1109	#define MAC_TXDESCRIPTOR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1110	#define MAC_TXSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1111	#define MAC_TXDESCRIPTORNUM ((volatile uint32_t ) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1112	#define MAC_TXPRODUCEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1113	#define MAC_TXCONSUMEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1114
1115	#define MAC_TSV0 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1116	#define MAC_TSV1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1117	#define MAC_RSV ((volatile uint32_t ) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1118
1119	#define MAC_FLOWCONTROLCNT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1120	#define MAC_FLOWCONTROLSTS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1121
1122	#define MAC_RXFILTERCTRL ((volatile uint32_t ) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1123	#define MAC_RXFILTERWOLSTS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1124	#define MAC_RXFILTERWOLCLR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1125
1126	#define MAC_HASHFILTERL ((volatile uint32_t ) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1127	#define MAC_HASHFILTERH ((volatile uint32_t ) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1128
1129	#define MAC_INTSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1130	#define MAC_INTENABLE ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
1131	#define MAC_INTCLEAR ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1132	#define MAC_INTSET ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1133
1134	#define MAC_POWERDOWN ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1135	#define MAC_MODULEID ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1136
1137	/* LCD Controller */
1138
1139	#define LCD_BASE_ADDR 0xFFE10000
1140	#define LCD_CFG ((volatile uint32_t ) 0xE01FC1B8)
1141	#define LCD_TIMH ((volatile uint32_t ) (LCD_BASE_ADDR + 0x000))
1142	#define LCD_TIMV ((volatile uint32_t ) (LCD_BASE_ADDR + 0x004))
1143	#define LCD_POL ((volatile uint32_t ) (LCD_BASE_ADDR + 0x008))
1144	#define LCD_LE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x00C))
1145	#define LCD_UPBASE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x010))
1146	#define LCD_LPBASE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x014))
1147	#define LCD_CTRL ((volatile uint32_t ) (LCD_BASE_ADDR + 0x018))
1148	#define LCD_INTMSK ((volatile uint32_t ) (LCD_BASE_ADDR + 0x01C))
1149	#define LCD_INTRAW ((volatile uint32_t ) (LCD_BASE_ADDR + 0x020))
1150	#define LCD_INTSTAT ((volatile uint32_t ) (LCD_BASE_ADDR + 0x024))
1151	#define LCD_INTCLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x028))
1152	#define LCD_UPCURR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x02C))
1153	#define LCD_LPCURR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x030))
1154	#define LCD_PAL_ADDR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x200))
1155	#define CRSR_IMG ((volatile uint32_t ) (LCD_BASE_ADDR + 0x800))
1156	#define CRSR_CTLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC00))
1157	#define CRSR_CFG ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC04))
1158	#define CRSR_PAL0 ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC08))
1159	#define CRSR_PAL1 ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC0C))
1160	#define CRSR_XY ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC10))
1161	#define CRSR_CLIP ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC14))
1162	#define CRSR_INTMSK ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC20))
1163	#define CRSR_INTCLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC24))
1164	#define CRSR_INTRAW ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC28))
1165	#define CRSR_INTSTAT ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC2C))
1166
1167	/* Register Fields */
1168
1169	#define GET_FIELD( val, mask, shift) \
1170	(((val) & (mask)) >> (shift))
1171
1172	#define SET_FIELD( val, field, mask, shift) \
1173	(((val) & ~(mask)) \| (((field) << (shift)) & (mask)))
1174
1175	/* CLKSRCSEL */
1176
1177	#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1178
1179	#define GET_CLKSRCSEL_CLKSRC(reg) \
1180	GET_FIELD(reg, CLKSRCSEL_CLKSRC_MASK, 0)
1181
1182	#define SET_CLKSRCSEL_CLKSRC(reg, val) \
1183	SET_FIELD(reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1184
1185	/* PLLCON */
1186
1187	#define PLLCON_PLLE 0x00000001U
1188
1189	#define PLLCON_PLLC 0x00000002U
1190
1191	/* PLLCFG */
1192
1193	#define PLLCFG_MSEL_MASK 0x00007fffU
1194
1195	#define GET_PLLCFG_MSEL(reg) \
1196	GET_FIELD(reg, PLLCFG_MSEL_MASK, 0)
1197
1198	#define SET_PLLCFG_MSEL(reg, val) \
1199	SET_FIELD(reg, val, PLLCFG_MSEL_MASK, 0)
1200
1201	#define PLLCFG_NSEL_MASK 0x00ff0000U
1202
1203	#define GET_PLLCFG_NSEL(reg) \
1204	GET_FIELD(reg, PLLCFG_NSEL_MASK, 16)
1205
1206	#define SET_PLLCFG_NSEL(reg, val) \
1207	SET_FIELD(reg, val, PLLCFG_NSEL_MASK, 16)
1208
1209	/* PLLSTAT */
1210
1211	#define PLLSTAT_MSEL_MASK 0x00007fffU
1212
1213	#define GET_PLLSTAT_MSEL(reg) \
1214	GET_FIELD(reg, PLLSTAT_MSEL_MASK, 0)
1215
1216	#define SET_PLLSTAT_MSEL(reg, val) \
1217	SET_FIELD(reg, val, PLLSTAT_MSEL_MASK, 0)
1218
1219	#define PLLSTAT_NSEL_MASK 0x00ff0000U
1220
1221	#define GET_PLLSTAT_NSEL(reg) \
1222	GET_FIELD(reg, PLLSTAT_NSEL_MASK, 16)
1223
1224	#define SET_PLLSTAT_NSEL(reg, val) \
1225	SET_FIELD(reg, val, PLLSTAT_NSEL_MASK, 16)
1226
1227	#define PLLSTAT_PLLE 0x01000000U
1228
1229	#define PLLSTAT_PLLC 0x02000000U
1230
1231	#define PLLSTAT_PLOCK 0x04000000U
1232
1233	/* CCLKCFG */
1234
1235	#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1236
1237	#define GET_CCLKCFG_CCLKSEL(reg) \
1238	GET_FIELD(reg, CCLKCFG_CCLKSEL_MASK, 0)
1239
1240	#define SET_CCLKCFG_CCLKSEL(reg, val) \
1241	SET_FIELD(reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1242
1243	/* MEMMAP */
1244
1245	#define MEMMAP_MAP_MASK 0x00000003U
1246
1247	#define GET_MEMMAP_MAP(reg) \
1248	GET_FIELD(reg, MEMMAP_MAP_MASK, 0)
1249
1250	#define SET_MEMMAP_MAP(reg, val) \
1251	SET_FIELD(reg, val, MEMMAP_MAP_MASK, 0)
1252
1253	/* TIR */
1254
1255	#define TIR_MR0 0x00000001U
1256
1257	#define TIR_MR1 0x00000002U
1258
1259	#define TIR_MR2 0x00000004U
1260
1261	#define TIR_MR3 0x00000008U
1262
1263	#define TIR_CR0 0x00000010U
1264
1265	#define TIR_CR1 0x00000020U
1266
1267	#define TIR_CR2 0x00000040U
1268
1269	#define TIR_CR3 0x00000080U
1270
1271	/* TCR */
1272
1273	#define TCR_EN 0x00000001U
1274
1275	#define TCR_RST 0x00000002U
1276
1277	/* TMCR */
1278
1279	#define TMCR_MR0I 0x00000001U
1280
1281	#define TMCR_MR0R 0x00000002U
1282
1283	#define TMCR_MR0S 0x00000004U
1284
1285	#define TMCR_MR1I 0x00000008U
1286
1287	#define TMCR_MR1R 0x00000010U
1288
1289	#define TMCR_MR1S 0x00000020U
1290
1291	#define TMCR_MR2I 0x00000040U
1292
1293	#define TMCR_MR2R 0x00000080U
1294
1295	#define TMCR_MR2S 0x00000100U
1296
1297	#define TMCR_MR3I 0x00000200U
1298
1299	#define TMCR_MR3R 0x00000400U
1300
1301	#define TMCR_MR3S 0x00000800U
1302
1303	/* PCLKSEL0 */
1304
1305	#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1306
1307	#define GET_PCLKSEL0_PCLK_WDT(reg) \
1308	GET_FIELD(reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1309
1310	#define SET_PCLKSEL0_PCLK_WDT(reg, val) \
1311	SET_FIELD(reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1312
1313	#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1314
1315	#define GET_PCLKSEL0_PCLK_TIMER0(reg) \
1316	GET_FIELD(reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1317
1318	#define SET_PCLKSEL0_PCLK_TIMER0(reg, val) \
1319	SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1320
1321	#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1322
1323	#define GET_PCLKSEL0_PCLK_TIMER1(reg) \
1324	GET_FIELD(reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1325
1326	#define SET_PCLKSEL0_PCLK_TIMER1(reg, val) \
1327	SET_FIELD(reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1328
1329	#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1330
1331	#define GET_PCLKSEL0_PCLK_UART0(reg) \
1332	GET_FIELD(reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1333
1334	#define SET_PCLKSEL0_PCLK_UART0(reg, val) \
1335	SET_FIELD(reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1336
1337	#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1338
1339	#define GET_PCLKSEL0_PCLK_UART1(reg) \
1340	GET_FIELD(reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1341
1342	#define SET_PCLKSEL0_PCLK_UART1(reg, val) \
1343	SET_FIELD(reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1344
1345	#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1346
1347	#define GET_PCLKSEL0_PCLK_PWM0(reg) \
1348	GET_FIELD(reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1349
1350	#define SET_PCLKSEL0_PCLK_PWM0(reg, val) \
1351	SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1352
1353	#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1354
1355	#define GET_PCLKSEL0_PCLK_PWM1(reg) \
1356	GET_FIELD(reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1357
1358	#define SET_PCLKSEL0_PCLK_PWM1(reg, val) \
1359	SET_FIELD(reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1360
1361	#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1362
1363	#define GET_PCLKSEL0_PCLK_I2C0(reg) \
1364	GET_FIELD(reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1365
1366	#define SET_PCLKSEL0_PCLK_I2C0(reg, val) \
1367	SET_FIELD(reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1368
1369	#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1370
1371	#define GET_PCLKSEL0_PCLK_SPI(reg) \
1372	GET_FIELD(reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1373
1374	#define SET_PCLKSEL0_PCLK_SPI(reg, val) \
1375	SET_FIELD(reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1376
1377	#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1378
1379	#define GET_PCLKSEL0_PCLK_RTC(reg) \
1380	GET_FIELD(reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1381
1382	#define SET_PCLKSEL0_PCLK_RTC(reg, val) \
1383	SET_FIELD(reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1384
1385	#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1386
1387	#define GET_PCLKSEL0_PCLK_SSP1(reg) \
1388	GET_FIELD(reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1389
1390	#define SET_PCLKSEL0_PCLK_SSP1(reg, val) \
1391	SET_FIELD(reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1392
1393	#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1394
1395	#define GET_PCLKSEL0_PCLK_DAC(reg) \
1396	GET_FIELD(reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1397
1398	#define SET_PCLKSEL0_PCLK_DAC(reg, val) \
1399	SET_FIELD(reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1400
1401	#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1402
1403	#define GET_PCLKSEL0_PCLK_ADC(reg) \
1404	GET_FIELD(reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1405
1406	#define SET_PCLKSEL0_PCLK_ADC(reg, val) \
1407	SET_FIELD(reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1408
1409	#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1410
1411	#define GET_PCLKSEL0_PCLK_CAN1(reg) \
1412	GET_FIELD(reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1413
1414	#define SET_PCLKSEL0_PCLK_CAN1(reg, val) \
1415	SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1416
1417	#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1418
1419	#define GET_PCLKSEL0_PCLK_CAN2(reg) \
1420	GET_FIELD(reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1421
1422	#define SET_PCLKSEL0_PCLK_CAN2(reg, val) \
1423	SET_FIELD(reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1424
1425	/* PCLKSEL1 */
1426
1427	#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1428
1429	#define GET_PCLKSEL1_PCLK_BAT_RAM(reg) \
1430	GET_FIELD(reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1431
1432	#define SET_PCLKSEL1_PCLK_BAT_RAM(reg, val) \
1433	SET_FIELD(reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1434
1435	#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1436
1437	#define GET_PCLKSEL1_PCLK_GPIO(reg) \
1438	GET_FIELD(reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1439
1440	#define SET_PCLKSEL1_PCLK_GPIO(reg, val) \
1441	SET_FIELD(reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1442
1443	#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1444
1445	#define GET_PCLKSEL1_PCLK_PCB(reg) \
1446	GET_FIELD(reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1447
1448	#define SET_PCLKSEL1_PCLK_PCB(reg, val) \
1449	SET_FIELD(reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1450
1451	#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1452
1453	#define GET_PCLKSEL1_PCLK_I2C1(reg) \
1454	GET_FIELD(reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1455
1456	#define SET_PCLKSEL1_PCLK_I2C1(reg, val) \
1457	SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1458
1459	#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1460
1461	#define GET_PCLKSEL1_PCLK_SSP0(reg) \
1462	GET_FIELD(reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1463
1464	#define SET_PCLKSEL1_PCLK_SSP0(reg, val) \
1465	SET_FIELD(reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1466
1467	#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1468
1469	#define GET_PCLKSEL1_PCLK_TIMER2(reg) \
1470	GET_FIELD(reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1471
1472	#define SET_PCLKSEL1_PCLK_TIMER2(reg, val) \
1473	SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1474
1475	#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1476
1477	#define GET_PCLKSEL1_PCLK_TIMER3(reg) \
1478	GET_FIELD(reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1479
1480	#define SET_PCLKSEL1_PCLK_TIMER3(reg, val) \
1481	SET_FIELD(reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1482
1483	#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1484
1485	#define GET_PCLKSEL1_PCLK_UART2(reg) \
1486	GET_FIELD(reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1487
1488	#define SET_PCLKSEL1_PCLK_UART2(reg, val) \
1489	SET_FIELD(reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1490
1491	#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1492
1493	#define GET_PCLKSEL1_PCLK_UART3(reg) \
1494	GET_FIELD(reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1495
1496	#define SET_PCLKSEL1_PCLK_UART3(reg, val) \
1497	SET_FIELD(reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1498
1499	#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1500
1501	#define GET_PCLKSEL1_PCLK_I2C2(reg) \
1502	GET_FIELD(reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1503
1504	#define SET_PCLKSEL1_PCLK_I2C2(reg, val) \
1505	SET_FIELD(reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1506
1507	#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1508
1509	#define GET_PCLKSEL1_PCLK_I2S(reg) \
1510	GET_FIELD(reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1511
1512	#define SET_PCLKSEL1_PCLK_I2S(reg, val) \
1513	SET_FIELD(reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1514
1515	#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1516
1517	#define GET_PCLKSEL1_PCLK_MCI(reg) \
1518	GET_FIELD(reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1519
1520	#define SET_PCLKSEL1_PCLK_MCI(reg, val) \
1521	SET_FIELD(reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1522
1523	#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1524
1525	#define GET_PCLKSEL1_PCLK_SYSCON(reg) \
1526	GET_FIELD(reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1527
1528	#define SET_PCLKSEL1_PCLK_SYSCON(reg, val) \
1529	SET_FIELD(reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1530
1531	/* RTC_ILR */
1532
1533	#define RTC_ILR_RTCCIF 0x00000001U
1534
1535	#define RTC_ILR_RTCALF 0x00000002U
1536
1537	#define RTC_ILR_RTSSF 0x00000004U
1538
1539	/* RTC_CCR */
1540
1541	#define RTC_CCR_CLKEN 0x00000001U
1542
1543	#define RTC_CCR_CTCRST 0x00000002U
1544
1545	#define RTC_CCR_CLKSRC 0x00000010U
1546
1547	/* SSP */
1548
1549	typedef struct {
1550	uint32_t cr0;
1551	uint32_t cr1;
1552	uint32_t dr;
1553	uint32_t sr;
1554	uint32_t cpsr;
1555	uint32_t imsc;
1556	uint32_t ris;
1557	uint32_t mis;
1558	uint32_t icr;
1559	uint32_t dmacr;
1560	} lpc24xx_ssp;
1561
1562	/* SSP_CR0 */
1563
1564	#define SSP_CR0_DSS_MASK 0x0000000fU
1565
1566	#define GET_SSP_CR0_DSS(reg) \
1567	GET_FIELD(reg, SSP_CR0_DSS_MASK, 0)
1568
1569	#define SET_SSP_CR0_DSS(reg, val) \
1570	SET_FIELD(reg, val, SSP_CR0_DSS_MASK, 0)
1571
1572	#define SSP_CR0_FRF_MASK 0x00000030U
1573
1574	#define GET_SSP_CR0_FRF(reg) \
1575	GET_FIELD(reg, SSP_CR0_FRF_MASK, 4)
1576
1577	#define SET_SSP_CR0_FRF(reg, val) \
1578	SET_FIELD(reg, val, SSP_CR0_FRF_MASK, 4)
1579
1580	#define SSP_CR0_CPOL 0x00000040U
1581
1582	#define SSP_CR0_CPHA 0x00000080U
1583
1584	#define SSP_CR0_SCR_MASK 0x0000ff00U
1585
1586	#define GET_SSP_CR0_SCR(reg) \
1587	GET_FIELD(reg, SSP_CR0_SCR_MASK, 8)
1588
1589	#define SET_SSP_CR0_SCR(reg, val) \
1590	SET_FIELD(reg, val, SSP_CR0_SCR_MASK, 8)
1591
1592	/* SSP_CR1 */
1593
1594	#define SSP_CR1_LBM 0x00000001U
1595
1596	#define SSP_CR1_SSE 0x00000002U
1597
1598	#define SSP_CR1_MS 0x00000004U
1599
1600	#define SSP_CR1_SOD 0x00000008U
1601
1602	/* SSP_SR */
1603
1604	#define SSP_SR_TFE 0x00000001U
1605
1606	#define SSP_SR_TNF 0x00000002U
1607
1608	#define SSP_SR_RNE 0x00000004U
1609
1610	#define SSP_SR_RFF 0x00000008U
1611
1612	#define SSP_SR_BSY 0x00000010U
1613
1614	/* SSP_IMSC */
1615
1616	#define SSP_IMSC_RORIM 0x00000001U
1617
1618	#define SSP_IMSC_RTIM 0x00000002U
1619
1620	#define SSP_IMSC_RXIM 0x00000004U
1621
1622	#define SSP_IMSC_TXIM 0x00000008U
1623
1624	/* SSP_RIS */
1625
1626	#define SSP_RIS_RORRIS 0x00000001U
1627
1628	#define SSP_RIS_RTRIS 0x00000002U
1629
1630	#define SSP_RIS_RXRIS 0x00000004U
1631
1632	#define SSP_RIS_TXRIS 0x00000008U
1633
1634	/* SSP_MIS */
1635
1636	#define SSP_MIS_RORRIS 0x00000001U
1637
1638	#define SSP_MIS_RTRIS 0x00000002U
1639
1640	#define SSP_MIS_RXRIS 0x00000004U
1641
1642	#define SSP_MIS_TXRIS 0x00000008U
1643
1644	/* SSP_ICR */
1645
1646	#define SSP_ICR_RORRIS 0x00000001U
1647
1648	#define SSP_ICR_RTRIS 0x00000002U
1649
1650	#define SSP_ICR_RXRIS 0x00000004U
1651
1652	#define SSP_ICR_TXRIS 0x00000008U
1653
1654	/* SSP_DMACR */
1655
1656	#define SSP_DMACR_RXDMAE 0x00000001U
1657
1658	#define SSP_DMACR_TXDMAE 0x00000002U
1659
1660	/* GPDMA */
1661
1662	typedef struct {
1663	uint32_t src;
1664	uint32_t dest;
1665	uint32_t lli;
1666	uint32_t ctrl;
1667	} lpc24xx_dma_descriptor;
1668
1669	typedef struct {
1670	lpc24xx_dma_descriptor desc;
1671	uint32_t cfg;
1672	} lpc24xx_dma_channel;
1673
1674	#define GPDMA_CH_NUMBER 2
1675
1676	#define GPDMA_STATUS_CH_0 0x00000001U
1677
1678	#define GPDMA_STATUS_CH_1 0x00000002U
1679
1680	#define GPDMA_CH_BASE_ADDR(i) \
1681	((volatile lpc24xx_dma_channel *) \
1682	((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1683
1684	/* GPDMA_CONFIG */
1685
1686	#define GPDMA_CONFIG_EN 0x00000001U
1687
1688	#define GPDMA_CONFIG_MODE 0x00000002U
1689
1690	/* GPDMA_ENABLED_CHNS */
1691
1692	#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1693
1694	#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1695
1696	/* GPDMA_CH_CTRL */
1697
1698	#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1699
1700	#define GET_GPDMA_CH_CTRL_TSZ(reg) \
1701	GET_FIELD(reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1702
1703	#define SET_GPDMA_CH_CTRL_TSZ(reg, val) \
1704	SET_FIELD(reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1705
1706	#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1707
1708	#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1709
1710	#define GET_GPDMA_CH_CTRL_SBSZ(reg) \
1711	GET_FIELD(reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1712
1713	#define SET_GPDMA_CH_CTRL_SBSZ(reg, val) \
1714	SET_FIELD(reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1715
1716	#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1717
1718	#define GET_GPDMA_CH_CTRL_DBSZ(reg) \
1719	GET_FIELD(reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1720
1721	#define SET_GPDMA_CH_CTRL_DBSZ(reg, val) \
1722	SET_FIELD(reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1723
1724	#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1725
1726	#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1727
1728	#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1729
1730	#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1731
1732	#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1733
1734	#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1735
1736	#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1737
1738	#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1739
1740	#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1741
1742	#define GET_GPDMA_CH_CTRL_SW(reg) \
1743	GET_FIELD(reg, GPDMA_CH_CTRL_SW_MASK, 18)
1744
1745	#define SET_GPDMA_CH_CTRL_SW(reg, val) \
1746	SET_FIELD(reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1747
1748	#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1749
1750	#define GET_GPDMA_CH_CTRL_DW(reg) \
1751	GET_FIELD(reg, GPDMA_CH_CTRL_DW_MASK, 21)
1752
1753	#define SET_GPDMA_CH_CTRL_DW(reg, val) \
1754	SET_FIELD(reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1755
1756	#define GPDMA_CH_CTRL_W_8 0x00000000U
1757
1758	#define GPDMA_CH_CTRL_W_16 0x00000001U
1759
1760	#define GPDMA_CH_CTRL_W_32 0x00000002U
1761
1762	#define GPDMA_CH_CTRL_SI 0x04000000U
1763
1764	#define GPDMA_CH_CTRL_DI 0x08000000U
1765
1766	#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1767
1768	#define GET_GPDMA_CH_CTRL_PROT(reg) \
1769	GET_FIELD(reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1770
1771	#define SET_GPDMA_CH_CTRL_PROT(reg, val) \
1772	SET_FIELD(reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1773
1774	#define GPDMA_CH_CTRL_ITC 0x80000000U
1775
1776	/* GPDMA_CH_CFG */
1777
1778	#define GPDMA_CH_CFG_EN 0x00000001U
1779
1780	#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1781
1782	#define GET_GPDMA_CH_CFG_SRCPER(reg) \
1783	GET_FIELD(reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1784
1785	#define SET_GPDMA_CH_CFG_SRCPER(reg, val) \
1786	SET_FIELD(reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1787
1788	#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1789
1790	#define GET_GPDMA_CH_CFG_DESTPER(reg) \
1791	GET_FIELD(reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
1792
1793	#define SET_GPDMA_CH_CFG_DESTPER(reg, val) \
1794	SET_FIELD(reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
1795
1796	#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1797
1798	#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1799
1800	#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1801
1802	#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1803
1804	#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1805
1806	#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1807
1808	#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1809
1810	#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1811
1812	#define GET_GPDMA_CH_CFG_FLOW(reg) \
1813	GET_FIELD(reg, GPDMA_CH_CFG_FLOW_MASK, 11)
1814
1815	#define SET_GPDMA_CH_CFG_FLOW(reg, val) \
1816	SET_FIELD(reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
1817
1818	#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1819
1820	#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1821
1822	#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1823
1824	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1825
1826	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1827
1828	#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1829
1830	#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1831
1832	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1833
1834	#define GPDMA_CH_CFG_IE 0x00004000U
1835
1836	#define GPDMA_CH_CFG_ITC 0x00008000U
1837
1838	#define GPDMA_CH_CFG_LOCK 0x00010000U
1839
1840	#define GPDMA_CH_CFG_ACTIVE 0x00020000U
1841
1842	#define GPDMA_CH_CFG_HALT 0x00040000U
1843
1844	/* AHBCFG */
1845
1846	#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
1847
1848	#define AHBCFG_BREAK_BURST_MASK 0x00000006U
1849
1850	#define GET_AHBCFG_BREAK_BURST(reg) \
1851	GET_FIELD(reg, AHBCFG_BREAK_BURST_MASK, 1)
1852
1853	#define SET_AHBCFG_BREAK_BURST(reg, val) \
1854	SET_FIELD(reg, val, AHBCFG_BREAK_BURST_MASK, 1)
1855
1856	#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
1857
1858	#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
1859
1860	#define GET_AHBCFG_QUANTUM_SIZE(reg) \
1861	GET_FIELD(reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
1862
1863	#define SET_AHBCFG_QUANTUM_SIZE(reg, val) \
1864	SET_FIELD(reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
1865
1866	#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
1867
1868	#define GET_AHBCFG_DEFAULT_MASTER(reg) \
1869	GET_FIELD(reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
1870
1871	#define SET_AHBCFG_DEFAULT_MASTER(reg, val) \
1872	SET_FIELD(reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
1873
1874	#define AHBCFG_EP1_MASK 0x00007000U
1875
1876	#define GET_AHBCFG_EP1(reg) \
1877	GET_FIELD(reg, AHBCFG_EP1_MASK, 12)
1878
1879	#define SET_AHBCFG_EP1(reg, val) \
1880	SET_FIELD(reg, val, AHBCFG_EP1_MASK, 12)
1881
1882	#define AHBCFG_EP2_MASK 0x00070000U
1883
1884	#define GET_AHBCFG_EP2(reg) \
1885	GET_FIELD(reg, AHBCFG_EP2_MASK, 16)
1886
1887	#define SET_AHBCFG_EP2(reg, val) \
1888	SET_FIELD(reg, val, AHBCFG_EP2_MASK, 16)
1889
1890	#define AHBCFG_EP3_MASK 0x00700000U
1891
1892	#define GET_AHBCFG_EP3(reg) \
1893	GET_FIELD(reg, AHBCFG_EP3_MASK, 20)
1894
1895	#define SET_AHBCFG_EP3(reg, val) \
1896	SET_FIELD(reg, val, AHBCFG_EP3_MASK, 20)
1897
1898	#define AHBCFG_EP4_MASK 0x07000000U
1899
1900	#define GET_AHBCFG_EP4(reg) \
1901	GET_FIELD(reg, AHBCFG_EP4_MASK, 24)
1902
1903	#define SET_AHBCFG_EP4(reg, val) \
1904	SET_FIELD(reg, val, AHBCFG_EP4_MASK, 24)
1905
1906	#define AHBCFG_EP5_MASK 0x70000000U
1907
1908	#define GET_AHBCFG_EP5(reg) \
1909	GET_FIELD(reg, AHBCFG_EP5_MASK, 28)
1910
1911	#define SET_AHBCFG_EP5(reg, val) \
1912	SET_FIELD(reg, val, AHBCFG_EP5_MASK, 28)
1913
1914	/* EMC */
1915
1916	#define EMC_DYN_CTRL_CE 0x00000001U
1917
1918	#define EMC_DYN_CTRL_CS 0x00000002U
1919
1920	#define EMC_DYN_CTRL_CMD_NORMAL 0x00000000U
1921
1922	#define EMC_DYN_CTRL_CMD_MODE 0x00000080U
1923
1924	#define EMC_DYN_CTRL_CMD_PALL 0x00000100U
1925
1926	#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
1927
1928	typedef struct {
1929	uint32_t cfg;
1930	uint32_t waitwen;
1931	uint32_t waitoen;
1932	uint32_t waitrd;
1933	uint32_t waitpage;
1934	uint32_t waitwr;
1935	uint32_t waitrun;
1936	} lpc24xx_emc_static;
1937
1938	/* I2C */
1939
1940	typedef struct {
1941	uint32_t conset;
1942	uint32_t stat;
1943	uint32_t dat;
1944	uint32_t adr;
1945	uint32_t sclh;
1946	uint32_t scll;
1947	uint32_t conclr;
1948	} lpc24xx_i2c;
1949
1950	#define LPC24XX_I2C_AA (1U << 2U)
1951
1952	#define LPC24XX_I2C_SI (1U << 3U)
1953
1954	#define LPC24XX_I2C_STO (1U << 4U)
1955
1956	#define LPC24XX_I2C_STA (1U << 5U)
1957
1958	#define LPC24XX_I2C_EN (1U << 6U)
1959
1960	/* IO */
1961
1962	typedef struct {
1963	uint32_t dir;
1964	uint32_t reserved [3];
1965	uint32_t mask;
1966	uint32_t pin;
1967	uint32_t set;
1968	uint32_t clr;
1969	} lpc24xx_fio;
1970
1971	#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
1972
1973	#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
1974
1975	#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
1976
1977	/* PCONP */
1978
1979	#define PCONP_GPDMA (1U << 29)
1980	#define PCONP_ETHERNET (1U << 30)
1981	#define PCONP_USB (1U << 31)
1982
1983	/** @} */
1984
1985	#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */

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