Context Navigation

source: rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h @ 32b8506

4.104.115

Last change on this file since 32b8506 was 32b8506, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/29/09 at 14:53:02
Whitespace removal.
Property mode set to `100644`
File size: 90.7 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup lpc24xx_regs
5	*
6	* @brief Register definitions.
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be found in the file
18	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19	*/
20
21	#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
22	#define LIBBSP_ARM_LPC24XX_LPC24XX_H
23
24	#include <stdint.h>
25
26	#include <bsp/utility.h>
27
28	/**
29	* @defgroup lpc24xx_regs Register Definitions
30	*
31	* @ingroup lpc24xx
32	*
33	* @brief Register definitions.
34	*
35	* @{
36	*/
37
38	/* Vectored Interrupt Controller (VIC) */
39	#define VIC_BASE_ADDR 0xFFFFF000
40	#define VICIRQStatus ((volatile uint32_t ) (VIC_BASE_ADDR + 0x000))
41	#define VICFIQStatus ((volatile uint32_t ) (VIC_BASE_ADDR + 0x004))
42	#define VICRawIntr ((volatile uint32_t ) (VIC_BASE_ADDR + 0x008))
43	#define VICIntSelect ((volatile uint32_t ) (VIC_BASE_ADDR + 0x00C))
44	#define VICIntEnable ((volatile uint32_t ) (VIC_BASE_ADDR + 0x010))
45	#define VICIntEnClear ((volatile uint32_t ) (VIC_BASE_ADDR + 0x014))
46	#define VICSoftInt ((volatile uint32_t ) (VIC_BASE_ADDR + 0x018))
47	#define VICSoftIntClear ((volatile uint32_t ) (VIC_BASE_ADDR + 0x01C))
48	#define VICProtection ((volatile uint32_t ) (VIC_BASE_ADDR + 0x020))
49	#define VICSWPrioMask ((volatile uint32_t ) (VIC_BASE_ADDR + 0x024))
50
51	#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
52	#define VICVectAddr0 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x100))
53	#define VICVectAddr1 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x104))
54	#define VICVectAddr2 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x108))
55	#define VICVectAddr3 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x10C))
56	#define VICVectAddr4 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x110))
57	#define VICVectAddr5 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x114))
58	#define VICVectAddr6 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x118))
59	#define VICVectAddr7 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x11C))
60	#define VICVectAddr8 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x120))
61	#define VICVectAddr9 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x124))
62	#define VICVectAddr10 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x128))
63	#define VICVectAddr11 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x12C))
64	#define VICVectAddr12 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x130))
65	#define VICVectAddr13 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x134))
66	#define VICVectAddr14 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x138))
67	#define VICVectAddr15 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x13C))
68	#define VICVectAddr16 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x140))
69	#define VICVectAddr17 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x144))
70	#define VICVectAddr18 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x148))
71	#define VICVectAddr19 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x14C))
72	#define VICVectAddr20 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x150))
73	#define VICVectAddr21 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x154))
74	#define VICVectAddr22 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x158))
75	#define VICVectAddr23 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x15C))
76	#define VICVectAddr24 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x160))
77	#define VICVectAddr25 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x164))
78	#define VICVectAddr26 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x168))
79	#define VICVectAddr27 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x16C))
80	#define VICVectAddr28 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x170))
81	#define VICVectAddr29 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x174))
82	#define VICVectAddr30 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x178))
83	#define VICVectAddr31 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x17C))
84
85	#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
86	#define VICVectPriority0 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x200))
87	#define VICVectPriority1 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x204))
88	#define VICVectPriority2 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x208))
89	#define VICVectPriority3 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x20C))
90	#define VICVectPriority4 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x210))
91	#define VICVectPriority5 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x214))
92	#define VICVectPriority6 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x218))
93	#define VICVectPriority7 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x21C))
94	#define VICVectPriority8 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x220))
95	#define VICVectPriority9 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x224))
96	#define VICVectPriority10 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x228))
97	#define VICVectPriority11 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x22C))
98	#define VICVectPriority12 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x230))
99	#define VICVectPriority13 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x234))
100	#define VICVectPriority14 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x238))
101	#define VICVectPriority15 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x23C))
102	#define VICVectPriority16 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x240))
103	#define VICVectPriority17 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x244))
104	#define VICVectPriority18 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x248))
105	#define VICVectPriority19 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x24C))
106	#define VICVectPriority20 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x250))
107	#define VICVectPriority21 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x254))
108	#define VICVectPriority22 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x258))
109	#define VICVectPriority23 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x25C))
110	#define VICVectPriority24 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x260))
111	#define VICVectPriority25 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x264))
112	#define VICVectPriority26 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x268))
113	#define VICVectPriority27 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x26C))
114	#define VICVectPriority28 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x270))
115	#define VICVectPriority29 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x274))
116	#define VICVectPriority30 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x278))
117	#define VICVectPriority31 ((volatile uint32_t ) (VIC_BASE_ADDR + 0x27C))
118
119	#define VICVectAddr ((volatile uint32_t ) (VIC_BASE_ADDR + 0xF00))
120
121
122	/* Pin Connect Block */
123	#define PINSEL_BASE_ADDR 0xE002C000
124	#define PINSEL0 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x00))
125	#define PINSEL1 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x04))
126	#define PINSEL2 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x08))
127	#define PINSEL3 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x0C))
128	#define PINSEL4 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x10))
129	#define PINSEL5 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x14))
130	#define PINSEL6 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x18))
131	#define PINSEL7 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x1C))
132	#define PINSEL8 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x20))
133	#define PINSEL9 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x24))
134	#define PINSEL10 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x28))
135	#define PINSEL11 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x2C))
136
137	#define PINMODE0 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x40))
138	#define PINMODE1 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x44))
139	#define PINMODE2 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x48))
140	#define PINMODE3 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x4C))
141	#define PINMODE4 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x50))
142	#define PINMODE5 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x54))
143	#define PINMODE6 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x58))
144	#define PINMODE7 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x5C))
145	#define PINMODE8 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x60))
146	#define PINMODE9 ((volatile uint32_t ) (PINSEL_BASE_ADDR + 0x64))
147
148	/* General Purpose Input/Output (GPIO) */
149	#define GPIO_BASE_ADDR 0xE0028000
150	#define IOPIN0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x00))
151	#define IOSET0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x04))
152	#define IODIR0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x08))
153	#define IOCLR0 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x0C))
154	#define IOPIN1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x10))
155	#define IOSET1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x14))
156	#define IODIR1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x18))
157	#define IOCLR1 ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x1C))
158
159	/* GPIO Interrupt Registers */
160	#define IO0_INT_EN_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x90))
161	#define IO0_INT_EN_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x94))
162	#define IO0_INT_STAT_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x84))
163	#define IO0_INT_STAT_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x88))
164	#define IO0_INT_CLR ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x8C))
165
166	#define IO2_INT_EN_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xB0))
167	#define IO2_INT_EN_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xB4))
168	#define IO2_INT_STAT_R ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xA4))
169	#define IO2_INT_STAT_F ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xA8))
170	#define IO2_INT_CLR ((volatile uint32_t ) (GPIO_BASE_ADDR + 0xAC))
171
172	#define IO_INT_STAT ((volatile uint32_t ) (GPIO_BASE_ADDR + 0x80))
173
174	#define PARTCFG_BASE_ADDR 0x3FFF8000
175	#define PARTCFG ((volatile uint32_t ) (PARTCFG_BASE_ADDR + 0x00))
176
177	/* Fast I/O setup */
178	#define FIO_BASE_ADDR 0x3FFFC000
179	#define FIO0DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x00))
180	#define FIO0MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x10))
181	#define FIO0PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x14))
182	#define FIO0SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x18))
183	#define FIO0CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x1C))
184
185	#define FIO1DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x20))
186	#define FIO1MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x30))
187	#define FIO1PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x34))
188	#define FIO1SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x38))
189	#define FIO1CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x3C))
190
191	#define FIO2DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x40))
192	#define FIO2MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x50))
193	#define FIO2PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x54))
194	#define FIO2SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x58))
195	#define FIO2CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x5C))
196
197	#define FIO3DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x60))
198	#define FIO3MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x70))
199	#define FIO3PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x74))
200	#define FIO3SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x78))
201	#define FIO3CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x7C))
202
203	#define FIO4DIR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x80))
204	#define FIO4MASK ((volatile uint32_t ) (FIO_BASE_ADDR + 0x90))
205	#define FIO4PIN ((volatile uint32_t ) (FIO_BASE_ADDR + 0x94))
206	#define FIO4SET ((volatile uint32_t ) (FIO_BASE_ADDR + 0x98))
207	#define FIO4CLR ((volatile uint32_t ) (FIO_BASE_ADDR + 0x9C))
208
209	/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
210	#define FIO0DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x01))
211	#define FIO1DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x21))
212	#define FIO2DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x41))
213	#define FIO3DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x61))
214	#define FIO4DIR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x81))
215
216	#define FIO0DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x02))
217	#define FIO1DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x22))
218	#define FIO2DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x42))
219	#define FIO3DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x62))
220	#define FIO4DIR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x82))
221
222	#define FIO0DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x03))
223	#define FIO1DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x23))
224	#define FIO2DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x43))
225	#define FIO3DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x63))
226	#define FIO4DIR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x83))
227
228	#define FIO0DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x04))
229	#define FIO1DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x24))
230	#define FIO2DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x44))
231	#define FIO3DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x64))
232	#define FIO4DIR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x84))
233
234	#define FIO0DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x00))
235	#define FIO1DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x20))
236	#define FIO2DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x40))
237	#define FIO3DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x60))
238	#define FIO4DIRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x80))
239
240	#define FIO0DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x02))
241	#define FIO1DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x22))
242	#define FIO2DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x42))
243	#define FIO3DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x62))
244	#define FIO4DIRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x82))
245
246	#define FIO0MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x10))
247	#define FIO1MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x30))
248	#define FIO2MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x50))
249	#define FIO3MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x70))
250	#define FIO4MASK0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x90))
251
252	#define FIO0MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x11))
253	#define FIO1MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x21))
254	#define FIO2MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x51))
255	#define FIO3MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x71))
256	#define FIO4MASK1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x91))
257
258	#define FIO0MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x12))
259	#define FIO1MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x32))
260	#define FIO2MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x52))
261	#define FIO3MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x72))
262	#define FIO4MASK2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x92))
263
264	#define FIO0MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x13))
265	#define FIO1MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x33))
266	#define FIO2MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x53))
267	#define FIO3MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x73))
268	#define FIO4MASK3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x93))
269
270	#define FIO0MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x10))
271	#define FIO1MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x30))
272	#define FIO2MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x50))
273	#define FIO3MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x70))
274	#define FIO4MASKL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x90))
275
276	#define FIO0MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x12))
277	#define FIO1MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x32))
278	#define FIO2MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x52))
279	#define FIO3MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x72))
280	#define FIO4MASKU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x92))
281
282	#define FIO0PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x14))
283	#define FIO1PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x34))
284	#define FIO2PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x54))
285	#define FIO3PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x74))
286	#define FIO4PIN0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x94))
287
288	#define FIO0PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x15))
289	#define FIO1PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x25))
290	#define FIO2PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x55))
291	#define FIO3PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x75))
292	#define FIO4PIN1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x95))
293
294	#define FIO0PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x16))
295	#define FIO1PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x36))
296	#define FIO2PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x56))
297	#define FIO3PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x76))
298	#define FIO4PIN2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x96))
299
300	#define FIO0PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x17))
301	#define FIO1PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x37))
302	#define FIO2PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x57))
303	#define FIO3PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x77))
304	#define FIO4PIN3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x97))
305
306	#define FIO0PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x14))
307	#define FIO1PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x34))
308	#define FIO2PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x54))
309	#define FIO3PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x74))
310	#define FIO4PINL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x94))
311
312	#define FIO0PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x16))
313	#define FIO1PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x36))
314	#define FIO2PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x56))
315	#define FIO3PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x76))
316	#define FIO4PINU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x96))
317
318	#define FIO0SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x18))
319	#define FIO1SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x38))
320	#define FIO2SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x58))
321	#define FIO3SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x78))
322	#define FIO4SET0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x98))
323
324	#define FIO0SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x19))
325	#define FIO1SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x29))
326	#define FIO2SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x59))
327	#define FIO3SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x79))
328	#define FIO4SET1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x99))
329
330	#define FIO0SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1A))
331	#define FIO1SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3A))
332	#define FIO2SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5A))
333	#define FIO3SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7A))
334	#define FIO4SET2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9A))
335
336	#define FIO0SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1B))
337	#define FIO1SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3B))
338	#define FIO2SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5B))
339	#define FIO3SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7B))
340	#define FIO4SET3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9B))
341
342	#define FIO0SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x18))
343	#define FIO1SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x38))
344	#define FIO2SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x58))
345	#define FIO3SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x78))
346	#define FIO4SETL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x98))
347
348	#define FIO0SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1A))
349	#define FIO1SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3A))
350	#define FIO2SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5A))
351	#define FIO3SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7A))
352	#define FIO4SETU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9A))
353
354	#define FIO0CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1C))
355	#define FIO1CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3C))
356	#define FIO2CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5C))
357	#define FIO3CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7C))
358	#define FIO4CLR0 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9C))
359
360	#define FIO0CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1D))
361	#define FIO1CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x2D))
362	#define FIO2CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5D))
363	#define FIO3CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7D))
364	#define FIO4CLR1 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9D))
365
366	#define FIO0CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1E))
367	#define FIO1CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3E))
368	#define FIO2CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5E))
369	#define FIO3CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7E))
370	#define FIO4CLR2 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9E))
371
372	#define FIO0CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x1F))
373	#define FIO1CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x3F))
374	#define FIO2CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x5F))
375	#define FIO3CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x7F))
376	#define FIO4CLR3 ((volatile uint8_t ) (FIO_BASE_ADDR + 0x9F))
377
378	#define FIO0CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1C))
379	#define FIO1CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3C))
380	#define FIO2CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5C))
381	#define FIO3CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7C))
382	#define FIO4CLRL ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9C))
383
384	#define FIO0CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x1E))
385	#define FIO1CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x3E))
386	#define FIO2CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x5E))
387	#define FIO3CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x7E))
388	#define FIO4CLRU ((volatile uint16_t ) (FIO_BASE_ADDR + 0x9E))
389
390
391	/* System Control Block(SCB) modules include Memory Accelerator Module,
392	Phase Locked Loop, VPB divider, Power Control, External Interrupt,
393	Reset, and Code Security/Debugging */
394	#define SCB_BASE_ADDR 0xE01FC000
395
396	/* Memory Accelerator Module (MAM) */
397	#define MAMCR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x000))
398	#define MAMTIM ((volatile uint32_t ) (SCB_BASE_ADDR + 0x004))
399	#define MEMMAP ((volatile uint32_t ) (SCB_BASE_ADDR + 0x040))
400
401	/* Phase Locked Loop (PLL) */
402	#define PLLCON ((volatile uint32_t ) (SCB_BASE_ADDR + 0x080))
403	#define PLLCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x084))
404	#define PLLSTAT ((volatile uint32_t ) (SCB_BASE_ADDR + 0x088))
405	#define PLLFEED ((volatile uint32_t ) (SCB_BASE_ADDR + 0x08C))
406
407	/* Power Control */
408	#define PCON ((volatile uint32_t ) (SCB_BASE_ADDR + 0x0C0))
409	#define PCONP ((volatile uint32_t ) (SCB_BASE_ADDR + 0x0C4))
410
411	/* Clock Divider */
412	// #define APBDIV ((volatile uint32_t ) (SCB_BASE_ADDR + 0x100))
413	#define CCLKCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x104))
414	#define USBCLKCFG ((volatile uint32_t ) (SCB_BASE_ADDR + 0x108))
415	#define CLKSRCSEL ((volatile uint32_t ) (SCB_BASE_ADDR + 0x10C))
416	#define PCLKSEL0 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1A8))
417	#define PCLKSEL1 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1AC))
418
419	/* External Interrupts */
420	#define EXTINT ((volatile uint32_t ) (SCB_BASE_ADDR + 0x140))
421	#define INTWAKE ((volatile uint32_t ) (SCB_BASE_ADDR + 0x144))
422	#define EXTMODE ((volatile uint32_t ) (SCB_BASE_ADDR + 0x148))
423	#define EXTPOLAR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x14C))
424
425	/* Reset, reset source identification */
426	#define RSIR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x180))
427
428	/* RSID, code security protection */
429	#define CSPR ((volatile uint32_t ) (SCB_BASE_ADDR + 0x184))
430
431	/* AHB configuration */
432	#define AHBCFG1 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x188))
433	#define AHBCFG2 ((volatile uint32_t ) (SCB_BASE_ADDR + 0x18C))
434
435	/* System Controls and Status */
436	#define SCS ((volatile uint32_t ) (SCB_BASE_ADDR + 0x1A0))
437
438
439	/* External Memory Controller (EMC) */
440	#define EMC_BASE_ADDR 0xFFE08000
441	#define EMC_CTRL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x000))
442	#define EMC_STAT ((volatile uint32_t ) (EMC_BASE_ADDR + 0x004))
443	#define EMC_CONFIG ((volatile uint32_t ) (EMC_BASE_ADDR + 0x008))
444
445	/* Dynamic RAM access registers */
446	#define EMC_DYN_CTRL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x020))
447	#define EMC_DYN_RFSH ((volatile uint32_t ) (EMC_BASE_ADDR + 0x024))
448	#define EMC_DYN_RD_CFG ((volatile uint32_t ) (EMC_BASE_ADDR + 0x028))
449	#define EMC_DYN_RP ((volatile uint32_t ) (EMC_BASE_ADDR + 0x030))
450	#define EMC_DYN_RAS ((volatile uint32_t ) (EMC_BASE_ADDR + 0x034))
451	#define EMC_DYN_SREX ((volatile uint32_t ) (EMC_BASE_ADDR + 0x038))
452	#define EMC_DYN_APR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x03C))
453	#define EMC_DYN_DAL ((volatile uint32_t ) (EMC_BASE_ADDR + 0x040))
454	#define EMC_DYN_WR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x044))
455	#define EMC_DYN_RC ((volatile uint32_t ) (EMC_BASE_ADDR + 0x048))
456	#define EMC_DYN_RFC ((volatile uint32_t ) (EMC_BASE_ADDR + 0x04C))
457	#define EMC_DYN_XSR ((volatile uint32_t ) (EMC_BASE_ADDR + 0x050))
458	#define EMC_DYN_RRD ((volatile uint32_t ) (EMC_BASE_ADDR + 0x054))
459	#define EMC_DYN_MRD ((volatile uint32_t ) (EMC_BASE_ADDR + 0x058))
460
461	#define EMC_DYN_CFG0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x100))
462	#define EMC_DYN_RASCAS0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x104))
463	#define EMC_DYN_CFG1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x140))
464	#define EMC_DYN_RASCAS1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x144))
465	#define EMC_DYN_CFG2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x160))
466	#define EMC_DYN_RASCAS2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x164))
467	#define EMC_DYN_CFG3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x180))
468	#define EMC_DYN_RASCAS3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x184))
469
470	/* static RAM access registers */
471	#define EMC_STA_BASE_0 ((uint32_t *) (EMC_BASE_ADDR + 0x200))
472	#define EMC_STA_CFG0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x200))
473	#define EMC_STA_WAITWEN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x204))
474	#define EMC_STA_WAITOEN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x208))
475	#define EMC_STA_WAITRD0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x20C))
476	#define EMC_STA_WAITPAGE0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x210))
477	#define EMC_STA_WAITWR0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x214))
478	#define EMC_STA_WAITTURN0 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x218))
479
480	#define EMC_STA_BASE_1 ((uint32_t *) (EMC_BASE_ADDR + 0x220))
481	#define EMC_STA_CFG1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x220))
482	#define EMC_STA_WAITWEN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x224))
483	#define EMC_STA_WAITOEN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x228))
484	#define EMC_STA_WAITRD1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x22C))
485	#define EMC_STA_WAITPAGE1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x230))
486	#define EMC_STA_WAITWR1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x234))
487	#define EMC_STA_WAITTURN1 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x238))
488
489	#define EMC_STA_BASE_2 ((uint32_t *) (EMC_BASE_ADDR + 0x240))
490	#define EMC_STA_CFG2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x240))
491	#define EMC_STA_WAITWEN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x244))
492	#define EMC_STA_WAITOEN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x248))
493	#define EMC_STA_WAITRD2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x24C))
494	#define EMC_STA_WAITPAGE2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x250))
495	#define EMC_STA_WAITWR2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x254))
496	#define EMC_STA_WAITTURN2 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x258))
497
498	#define EMC_STA_BASE_3 ((uint32_t *) (EMC_BASE_ADDR + 0x260))
499	#define EMC_STA_CFG3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x260))
500	#define EMC_STA_WAITWEN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x264))
501	#define EMC_STA_WAITOEN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x268))
502	#define EMC_STA_WAITRD3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x26C))
503	#define EMC_STA_WAITPAGE3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x270))
504	#define EMC_STA_WAITWR3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x274))
505	#define EMC_STA_WAITTURN3 ((volatile uint32_t ) (EMC_BASE_ADDR + 0x278))
506
507	#define EMC_STA_EXT_WAIT ((volatile uint32_t ) (EMC_BASE_ADDR + 0x880))
508
509
510	/* Timer 0 */
511	#define TMR0_BASE_ADDR 0xE0004000
512	#define T0IR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x00))
513	#define T0TCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x04))
514	#define T0TC ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x08))
515	#define T0PR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x0C))
516	#define T0PC ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x10))
517	#define T0MCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x14))
518	#define T0MR0 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x18))
519	#define T0MR1 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x1C))
520	#define T0MR2 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x20))
521	#define T0MR3 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x24))
522	#define T0CCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x28))
523	#define T0CR0 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x2C))
524	#define T0CR1 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x30))
525	#define T0CR2 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x34))
526	#define T0CR3 ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x38))
527	#define T0EMR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x3C))
528	#define T0CTCR ((volatile uint32_t ) (TMR0_BASE_ADDR + 0x70))
529
530	/* Timer 1 */
531	#define TMR1_BASE_ADDR 0xE0008000
532	#define T1IR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x00))
533	#define T1TCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x04))
534	#define T1TC ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x08))
535	#define T1PR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x0C))
536	#define T1PC ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x10))
537	#define T1MCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x14))
538	#define T1MR0 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x18))
539	#define T1MR1 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x1C))
540	#define T1MR2 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x20))
541	#define T1MR3 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x24))
542	#define T1CCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x28))
543	#define T1CR0 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x2C))
544	#define T1CR1 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x30))
545	#define T1CR2 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x34))
546	#define T1CR3 ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x38))
547	#define T1EMR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x3C))
548	#define T1CTCR ((volatile uint32_t ) (TMR1_BASE_ADDR + 0x70))
549
550	/* Timer 2 */
551	#define TMR2_BASE_ADDR 0xE0070000
552	#define T2IR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x00))
553	#define T2TCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x04))
554	#define T2TC ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x08))
555	#define T2PR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x0C))
556	#define T2PC ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x10))
557	#define T2MCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x14))
558	#define T2MR0 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x18))
559	#define T2MR1 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x1C))
560	#define T2MR2 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x20))
561	#define T2MR3 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x24))
562	#define T2CCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x28))
563	#define T2CR0 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x2C))
564	#define T2CR1 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x30))
565	#define T2CR2 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x34))
566	#define T2CR3 ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x38))
567	#define T2EMR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x3C))
568	#define T2CTCR ((volatile uint32_t ) (TMR2_BASE_ADDR + 0x70))
569
570	/* Timer 3 */
571	#define TMR3_BASE_ADDR 0xE0074000
572	#define T3IR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x00))
573	#define T3TCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x04))
574	#define T3TC ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x08))
575	#define T3PR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x0C))
576	#define T3PC ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x10))
577	#define T3MCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x14))
578	#define T3MR0 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x18))
579	#define T3MR1 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x1C))
580	#define T3MR2 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x20))
581	#define T3MR3 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x24))
582	#define T3CCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x28))
583	#define T3CR0 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x2C))
584	#define T3CR1 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x30))
585	#define T3CR2 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x34))
586	#define T3CR3 ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x38))
587	#define T3EMR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x3C))
588	#define T3CTCR ((volatile uint32_t ) (TMR3_BASE_ADDR + 0x70))
589
590
591	/* Pulse Width Modulator (PWM) */
592	#define PWM0_BASE_ADDR 0xE0014000
593	#define PWM0IR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x00))
594	#define PWM0TCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x04))
595	#define PWM0TC ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x08))
596	#define PWM0PR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x0C))
597	#define PWM0PC ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x10))
598	#define PWM0MCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x14))
599	#define PWM0MR0 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x18))
600	#define PWM0MR1 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x1C))
601	#define PWM0MR2 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x20))
602	#define PWM0MR3 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x24))
603	#define PWM0CCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x28))
604	#define PWM0CR0 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x2C))
605	#define PWM0CR1 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x30))
606	#define PWM0CR2 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x34))
607	#define PWM0CR3 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x38))
608	#define PWM0EMR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x3C))
609	#define PWM0MR4 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x40))
610	#define PWM0MR5 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x44))
611	#define PWM0MR6 ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x48))
612	#define PWM0PCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x4C))
613	#define PWM0LER ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x50))
614	#define PWM0CTCR ((volatile uint32_t ) (PWM0_BASE_ADDR + 0x70))
615
616	#define PWM1_BASE_ADDR 0xE0018000
617	#define PWM1IR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x00))
618	#define PWM1TCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x04))
619	#define PWM1TC ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x08))
620	#define PWM1PR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x0C))
621	#define PWM1PC ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x10))
622	#define PWM1MCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x14))
623	#define PWM1MR0 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x18))
624	#define PWM1MR1 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x1C))
625	#define PWM1MR2 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x20))
626	#define PWM1MR3 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x24))
627	#define PWM1CCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x28))
628	#define PWM1CR0 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x2C))
629	#define PWM1CR1 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x30))
630	#define PWM1CR2 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x34))
631	#define PWM1CR3 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x38))
632	#define PWM1EMR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x3C))
633	#define PWM1MR4 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x40))
634	#define PWM1MR5 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x44))
635	#define PWM1MR6 ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x48))
636	#define PWM1PCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x4C))
637	#define PWM1LER ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x50))
638	#define PWM1CTCR ((volatile uint32_t ) (PWM1_BASE_ADDR + 0x70))
639
640
641	/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
642	#define UART0_BASE_ADDR 0xE000C000
643	#define U0RBR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
644	#define U0THR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
645	#define U0DLL ((volatile uint32_t ) (UART0_BASE_ADDR + 0x00))
646	#define U0DLM ((volatile uint32_t ) (UART0_BASE_ADDR + 0x04))
647	#define U0IER ((volatile uint32_t ) (UART0_BASE_ADDR + 0x04))
648	#define U0IIR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x08))
649	#define U0FCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x08))
650	#define U0LCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x0C))
651	#define U0LSR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x14))
652	#define U0SCR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x1C))
653	#define U0ACR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x20))
654	#define U0ICR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x24))
655	#define U0FDR ((volatile uint32_t ) (UART0_BASE_ADDR + 0x28))
656	#define U0TER ((volatile uint32_t ) (UART0_BASE_ADDR + 0x30))
657
658	/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
659	#define UART1_BASE_ADDR 0xE0010000
660	#define U1RBR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
661	#define U1THR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
662	#define U1DLL ((volatile uint32_t ) (UART1_BASE_ADDR + 0x00))
663	#define U1DLM ((volatile uint32_t ) (UART1_BASE_ADDR + 0x04))
664	#define U1IER ((volatile uint32_t ) (UART1_BASE_ADDR + 0x04))
665	#define U1IIR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x08))
666	#define U1FCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x08))
667	#define U1LCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x0C))
668	#define U1MCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x10))
669	#define U1LSR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x14))
670	#define U1MSR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x18))
671	#define U1SCR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x1C))
672	#define U1ACR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x20))
673	#define U1FDR ((volatile uint32_t ) (UART1_BASE_ADDR + 0x28))
674	#define U1TER ((volatile uint32_t ) (UART1_BASE_ADDR + 0x30))
675
676	/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
677	#define UART2_BASE_ADDR 0xE0078000
678	#define U2RBR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
679	#define U2THR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
680	#define U2DLL ((volatile uint32_t ) (UART2_BASE_ADDR + 0x00))
681	#define U2DLM ((volatile uint32_t ) (UART2_BASE_ADDR + 0x04))
682	#define U2IER ((volatile uint32_t ) (UART2_BASE_ADDR + 0x04))
683	#define U2IIR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x08))
684	#define U2FCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x08))
685	#define U2LCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x0C))
686	#define U2LSR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x14))
687	#define U2SCR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x1C))
688	#define U2ACR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x20))
689	#define U2ICR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x24))
690	#define U2FDR ((volatile uint32_t ) (UART2_BASE_ADDR + 0x28))
691	#define U2TER ((volatile uint32_t ) (UART2_BASE_ADDR + 0x30))
692
693	/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
694	#define UART3_BASE_ADDR 0xE007C000
695	#define U3RBR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
696	#define U3THR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
697	#define U3DLL ((volatile uint32_t ) (UART3_BASE_ADDR + 0x00))
698	#define U3DLM ((volatile uint32_t ) (UART3_BASE_ADDR + 0x04))
699	#define U3IER ((volatile uint32_t ) (UART3_BASE_ADDR + 0x04))
700	#define U3IIR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x08))
701	#define U3FCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x08))
702	#define U3LCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x0C))
703	#define U3LSR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x14))
704	#define U3SCR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x1C))
705	#define U3ACR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x20))
706	#define U3ICR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x24))
707	#define U3FDR ((volatile uint32_t ) (UART3_BASE_ADDR + 0x28))
708	#define U3TER ((volatile uint32_t ) (UART3_BASE_ADDR + 0x30))
709
710	/* I2C Interface 0 */
711	#define I2C0_BASE_ADDR 0xE001C000
712	#define I20CONSET ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x00))
713	#define I20STAT ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x04))
714	#define I20DAT ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x08))
715	#define I20ADR ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x0C))
716	#define I20SCLH ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x10))
717	#define I20SCLL ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x14))
718	#define I20CONCLR ((volatile uint32_t ) (I2C0_BASE_ADDR + 0x18))
719
720	/* I2C Interface 1 */
721	#define I2C1_BASE_ADDR 0xE005C000
722	#define I21CONSET ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x00))
723	#define I21STAT ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x04))
724	#define I21DAT ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x08))
725	#define I21ADR ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x0C))
726	#define I21SCLH ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x10))
727	#define I21SCLL ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x14))
728	#define I21CONCLR ((volatile uint32_t ) (I2C1_BASE_ADDR + 0x18))
729
730	/* I2C Interface 2 */
731	#define I2C2_BASE_ADDR 0xE0080000
732	#define I22CONSET ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x00))
733	#define I22STAT ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x04))
734	#define I22DAT ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x08))
735	#define I22ADR ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x0C))
736	#define I22SCLH ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x10))
737	#define I22SCLL ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x14))
738	#define I22CONCLR ((volatile uint32_t ) (I2C2_BASE_ADDR + 0x18))
739
740	/* SPI0 (Serial Peripheral Interface 0) */
741	#define SPI0_BASE_ADDR 0xE0020000
742	#define S0SPCR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x00))
743	#define S0SPSR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x04))
744	#define S0SPDR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x08))
745	#define S0SPCCR ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x0C))
746	#define S0SPINT ((volatile uint32_t ) (SPI0_BASE_ADDR + 0x1C))
747
748	/* SSP0 Controller */
749	#define SSP0_BASE_ADDR 0xE0068000
750	#define SSP0CR0 ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x00))
751	#define SSP0CR1 ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x04))
752	#define SSP0DR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x08))
753	#define SSP0SR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x0C))
754	#define SSP0CPSR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x10))
755	#define SSP0IMSC ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x14))
756	#define SSP0RIS ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x18))
757	#define SSP0MIS ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x1C))
758	#define SSP0ICR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x20))
759	#define SSP0DMACR ((volatile uint32_t ) (SSP0_BASE_ADDR + 0x24))
760
761	/* SSP1 Controller */
762	#define SSP1_BASE_ADDR 0xE0030000
763	#define SSP1CR0 ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x00))
764	#define SSP1CR1 ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x04))
765	#define SSP1DR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x08))
766	#define SSP1SR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x0C))
767	#define SSP1CPSR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x10))
768	#define SSP1IMSC ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x14))
769	#define SSP1RIS ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x18))
770	#define SSP1MIS ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x1C))
771	#define SSP1ICR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x20))
772	#define SSP1DMACR ((volatile uint32_t ) (SSP1_BASE_ADDR + 0x24))
773
774
775	/* Real Time Clock */
776	#define RTC_BASE_ADDR 0xE0024000
777	#define RTC_ILR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x00))
778	#define RTC_CTC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x04))
779	#define RTC_CCR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x08))
780	#define RTC_CIIR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x0C))
781	#define RTC_AMR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x10))
782	#define RTC_CTIME0 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x14))
783	#define RTC_CTIME1 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x18))
784	#define RTC_CTIME2 ((volatile uint32_t ) (RTC_BASE_ADDR + 0x1C))
785	#define RTC_SEC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x20))
786	#define RTC_MIN ((volatile uint32_t ) (RTC_BASE_ADDR + 0x24))
787	#define RTC_HOUR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x28))
788	#define RTC_DOM ((volatile uint32_t ) (RTC_BASE_ADDR + 0x2C))
789	#define RTC_DOW ((volatile uint32_t ) (RTC_BASE_ADDR + 0x30))
790	#define RTC_DOY ((volatile uint32_t ) (RTC_BASE_ADDR + 0x34))
791	#define RTC_MONTH ((volatile uint32_t ) (RTC_BASE_ADDR + 0x38))
792	#define RTC_YEAR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x3C))
793	#define RTC_CISS ((volatile uint32_t ) (RTC_BASE_ADDR + 0x40))
794	#define RTC_ALSEC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x60))
795	#define RTC_ALMIN ((volatile uint32_t ) (RTC_BASE_ADDR + 0x64))
796	#define RTC_ALHOUR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x68))
797	#define RTC_ALDOM ((volatile uint32_t ) (RTC_BASE_ADDR + 0x6C))
798	#define RTC_ALDOW ((volatile uint32_t ) (RTC_BASE_ADDR + 0x70))
799	#define RTC_ALDOY ((volatile uint32_t ) (RTC_BASE_ADDR + 0x74))
800	#define RTC_ALMON ((volatile uint32_t ) (RTC_BASE_ADDR + 0x78))
801	#define RTC_ALYEAR ((volatile uint32_t ) (RTC_BASE_ADDR + 0x7C))
802	#define RTC_PREINT ((volatile uint32_t ) (RTC_BASE_ADDR + 0x80))
803	#define RTC_PREFRAC ((volatile uint32_t ) (RTC_BASE_ADDR + 0x84))
804
805
806	/* A/D Converter 0 (AD0) */
807	#define AD0_BASE_ADDR 0xE0034000
808	#define AD0CR ((volatile uint32_t ) (AD0_BASE_ADDR + 0x00))
809	#define AD0GDR ((volatile uint32_t ) (AD0_BASE_ADDR + 0x04))
810	#define AD0INTEN ((volatile uint32_t ) (AD0_BASE_ADDR + 0x0C))
811	#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
812	#define AD0DR0 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x10))
813	#define AD0DR1 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x14))
814	#define AD0DR2 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x18))
815	#define AD0DR3 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x1C))
816	#define AD0DR4 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x20))
817	#define AD0DR5 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x24))
818	#define AD0DR6 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x28))
819	#define AD0DR7 ((volatile uint32_t ) (AD0_BASE_ADDR + 0x2C))
820	#define AD0STAT ((volatile uint32_t ) (AD0_BASE_ADDR + 0x30))
821
822
823	/* D/A Converter */
824	#define DAC_BASE_ADDR 0xE006C000
825	#define DACR ((volatile uint32_t ) (DAC_BASE_ADDR + 0x00))
826
827
828	/* Watchdog */
829	#define WDG_BASE_ADDR 0xE0000000
830	#define WDMOD ((volatile uint32_t ) (WDG_BASE_ADDR + 0x00))
831	#define WDTC ((volatile uint32_t ) (WDG_BASE_ADDR + 0x04))
832	#define WDFEED ((volatile uint32_t ) (WDG_BASE_ADDR + 0x08))
833	#define WDTV ((volatile uint32_t ) (WDG_BASE_ADDR + 0x0C))
834	#define WDCLKSEL ((volatile uint32_t ) (WDG_BASE_ADDR + 0x10))
835
836	/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
837	#define CAN_ACCEPT_BASE_ADDR 0xE003C000
838	#define CAN_AFMR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x00))
839	#define CAN_SFF_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x04))
840	#define CAN_SFF_GRP_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x08))
841	#define CAN_EFF_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x0C))
842	#define CAN_EFF_GRP_SA ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x10))
843	#define CAN_EOT ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x14))
844	#define CAN_LUT_ERR_ADR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x18))
845	#define CAN_LUT_ERR ((volatile uint32_t ) (CAN_ACCEPT_BASE_ADDR + 0x1C))
846
847	#define CAN_CENTRAL_BASE_ADDR 0xE0040000
848	#define CAN_TX_SR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x00))
849	#define CAN_RX_SR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x04))
850	#define CAN_MSR ((volatile uint32_t ) (CAN_CENTRAL_BASE_ADDR + 0x08))
851
852	#define CAN1_BASE_ADDR 0xE0044000
853	#define CAN1MOD ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x00))
854	#define CAN1CMR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x04))
855	#define CAN1GSR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x08))
856	#define CAN1ICR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x0C))
857	#define CAN1IER ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x10))
858	#define CAN1BTR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x14))
859	#define CAN1EWL ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x18))
860	#define CAN1SR ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x1C))
861	#define CAN1RFS ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x20))
862	#define CAN1RID ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x24))
863	#define CAN1RDA ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x28))
864	#define CAN1RDB ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x2C))
865
866	#define CAN1TFI1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x30))
867	#define CAN1TID1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x34))
868	#define CAN1TDA1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x38))
869	#define CAN1TDB1 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x3C))
870	#define CAN1TFI2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x40))
871	#define CAN1TID2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x44))
872	#define CAN1TDA2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x48))
873	#define CAN1TDB2 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x4C))
874	#define CAN1TFI3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x50))
875	#define CAN1TID3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x54))
876	#define CAN1TDA3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x58))
877	#define CAN1TDB3 ((volatile uint32_t ) (CAN1_BASE_ADDR + 0x5C))
878
879	#define CAN2_BASE_ADDR 0xE0048000
880	#define CAN2MOD ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x00))
881	#define CAN2CMR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x04))
882	#define CAN2GSR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x08))
883	#define CAN2ICR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x0C))
884	#define CAN2IER ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x10))
885	#define CAN2BTR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x14))
886	#define CAN2EWL ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x18))
887	#define CAN2SR ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x1C))
888	#define CAN2RFS ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x20))
889	#define CAN2RID ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x24))
890	#define CAN2RDA ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x28))
891	#define CAN2RDB ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x2C))
892
893	#define CAN2TFI1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x30))
894	#define CAN2TID1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x34))
895	#define CAN2TDA1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x38))
896	#define CAN2TDB1 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x3C))
897	#define CAN2TFI2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x40))
898	#define CAN2TID2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x44))
899	#define CAN2TDA2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x48))
900	#define CAN2TDB2 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x4C))
901	#define CAN2TFI3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x50))
902	#define CAN2TID3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x54))
903	#define CAN2TDA3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x58))
904	#define CAN2TDB3 ((volatile uint32_t ) (CAN2_BASE_ADDR + 0x5C))
905
906
907	/* MultiMedia Card Interface(MCI) Controller */
908	#define MCI_BASE_ADDR 0xE008C000
909	#define MCI_POWER ((volatile uint32_t ) (MCI_BASE_ADDR + 0x00))
910	#define MCI_CLOCK ((volatile uint32_t ) (MCI_BASE_ADDR + 0x04))
911	#define MCI_ARGUMENT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x08))
912	#define MCI_COMMAND ((volatile uint32_t ) (MCI_BASE_ADDR + 0x0C))
913	#define MCI_RESP_CMD ((volatile uint32_t ) (MCI_BASE_ADDR + 0x10))
914	#define MCI_RESP0 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x14))
915	#define MCI_RESP1 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x18))
916	#define MCI_RESP2 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x1C))
917	#define MCI_RESP3 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x20))
918	#define MCI_DATA_TMR ((volatile uint32_t ) (MCI_BASE_ADDR + 0x24))
919	#define MCI_DATA_LEN ((volatile uint32_t ) (MCI_BASE_ADDR + 0x28))
920	#define MCI_DATA_CTRL ((volatile uint32_t ) (MCI_BASE_ADDR + 0x2C))
921	#define MCI_DATA_CNT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x30))
922	#define MCI_STATUS ((volatile uint32_t ) (MCI_BASE_ADDR + 0x34))
923	#define MCI_CLEAR ((volatile uint32_t ) (MCI_BASE_ADDR + 0x38))
924	#define MCI_MASK0 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x3C))
925	#define MCI_MASK1 ((volatile uint32_t ) (MCI_BASE_ADDR + 0x40))
926	#define MCI_FIFO_CNT ((volatile uint32_t ) (MCI_BASE_ADDR + 0x48))
927	#define MCI_FIFO ((volatile uint32_t ) (MCI_BASE_ADDR + 0x80))
928
929
930	/* I2S Interface Controller (I2S) */
931	#define I2S_BASE_ADDR 0xE0088000
932	#define I2S_DAO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x00))
933	#define I2S_DAI ((volatile uint32_t ) (I2S_BASE_ADDR + 0x04))
934	#define I2S_TX_FIFO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x08))
935	#define I2S_RX_FIFO ((volatile uint32_t ) (I2S_BASE_ADDR + 0x0C))
936	#define I2S_STATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x10))
937	#define I2S_DMA1 ((volatile uint32_t ) (I2S_BASE_ADDR + 0x14))
938	#define I2S_DMA2 ((volatile uint32_t ) (I2S_BASE_ADDR + 0x18))
939	#define I2S_IRQ ((volatile uint32_t ) (I2S_BASE_ADDR + 0x1C))
940	#define I2S_TXRATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x20))
941	#define I2S_RXRATE ((volatile uint32_t ) (I2S_BASE_ADDR + 0x24))
942
943
944	/* General-purpose DMA Controller */
945	#define DMA_BASE_ADDR 0xFFE04000
946	#define GPDMA_INT_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x000))
947	#define GPDMA_INT_TCSTAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x004))
948	#define GPDMA_INT_TCCLR ((volatile uint32_t ) (DMA_BASE_ADDR + 0x008))
949	#define GPDMA_INT_ERR_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x00C))
950	#define GPDMA_INT_ERR_CLR ((volatile uint32_t ) (DMA_BASE_ADDR + 0x010))
951	#define GPDMA_RAW_INT_TCSTAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x014))
952	#define GPDMA_RAW_INT_ERR_STAT ((volatile uint32_t ) (DMA_BASE_ADDR + 0x018))
953	#define GPDMA_ENABLED_CHNS ((volatile uint32_t ) (DMA_BASE_ADDR + 0x01C))
954	#define GPDMA_SOFT_BREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x020))
955	#define GPDMA_SOFT_SREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x024))
956	#define GPDMA_SOFT_LBREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x028))
957	#define GPDMA_SOFT_LSREQ ((volatile uint32_t ) (DMA_BASE_ADDR + 0x02C))
958	#define GPDMA_CONFIG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x030))
959	#define GPDMA_SYNC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x034))
960
961	/* DMA channel 0 registers */
962	#define GPDMA_CH0_BASE_ADDR (DMA_BASE_ADDR + 0x100)
963	#define GPDMA_CH0_SRC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x100))
964	#define GPDMA_CH0_DEST ((volatile uint32_t ) (DMA_BASE_ADDR + 0x104))
965	#define GPDMA_CH0_LLI ((volatile uint32_t ) (DMA_BASE_ADDR + 0x108))
966	#define GPDMA_CH0_CTRL ((volatile uint32_t ) (DMA_BASE_ADDR + 0x10C))
967	#define GPDMA_CH0_CFG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x110))
968
969	/* DMA channel 1 registers */
970	#define GPDMA_CH1_BASE_ADDR (DMA_BASE_ADDR + 0x120)
971	#define GPDMA_CH1_SRC ((volatile uint32_t ) (DMA_BASE_ADDR + 0x120))
972	#define GPDMA_CH1_DEST ((volatile uint32_t ) (DMA_BASE_ADDR + 0x124))
973	#define GPDMA_CH1_LLI ((volatile uint32_t ) (DMA_BASE_ADDR + 0x128))
974	#define GPDMA_CH1_CTRL ((volatile uint32_t ) (DMA_BASE_ADDR + 0x12C))
975	#define GPDMA_CH1_CFG ((volatile uint32_t ) (DMA_BASE_ADDR + 0x130))
976
977
978	/* USB Controller */
979	#define USB_INT_BASE_ADDR 0xE01FC1C0
980	#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
981
982	#define USB_INT_STAT ((volatile uint32_t ) (USB_INT_BASE_ADDR + 0x00))
983
984	/* USB Device Interrupt Registers */
985	#define DEV_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x00))
986	#define DEV_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x04))
987	#define DEV_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x08))
988	#define DEV_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x0C))
989	#define DEV_INT_PRIO ((volatile uint32_t ) (USB_BASE_ADDR + 0x2C))
990
991	/* USB Device Endpoint Interrupt Registers */
992	#define EP_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x30))
993	#define EP_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x34))
994	#define EP_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x38))
995	#define EP_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x3C))
996	#define EP_INT_PRIO ((volatile uint32_t ) (USB_BASE_ADDR + 0x40))
997
998	/* USB Device Endpoint Realization Registers */
999	#define REALIZE_EP ((volatile uint32_t ) (USB_BASE_ADDR + 0x44))
1000	#define EP_INDEX ((volatile uint32_t ) (USB_BASE_ADDR + 0x48))
1001	#define MAXPACKET_SIZE ((volatile uint32_t ) (USB_BASE_ADDR + 0x4C))
1002
1003	/* USB Device Command Reagisters */
1004	#define CMD_CODE ((volatile uint32_t ) (USB_BASE_ADDR + 0x10))
1005	#define CMD_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x14))
1006
1007	/* USB Device Data Transfer Registers */
1008	#define RX_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x18))
1009	#define TX_DATA ((volatile uint32_t ) (USB_BASE_ADDR + 0x1C))
1010	#define RX_PLENGTH ((volatile uint32_t ) (USB_BASE_ADDR + 0x20))
1011	#define TX_PLENGTH ((volatile uint32_t ) (USB_BASE_ADDR + 0x24))
1012	#define USB_CTRL ((volatile uint32_t ) (USB_BASE_ADDR + 0x28))
1013
1014	/* USB Device DMA Registers */
1015	#define DMA_REQ_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x50))
1016	#define DMA_REQ_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0x54))
1017	#define DMA_REQ_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0x58))
1018	#define UDCA_HEAD ((volatile uint32_t ) (USB_BASE_ADDR + 0x80))
1019	#define EP_DMA_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x84))
1020	#define EP_DMA_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x88))
1021	#define EP_DMA_DIS ((volatile uint32_t ) (USB_BASE_ADDR + 0x8C))
1022	#define DMA_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0x90))
1023	#define DMA_INT_EN ((volatile uint32_t ) (USB_BASE_ADDR + 0x94))
1024	#define EOT_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xA0))
1025	#define EOT_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xA4))
1026	#define EOT_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xA8))
1027	#define NDD_REQ_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xAC))
1028	#define NDD_REQ_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xB0))
1029	#define NDD_REQ_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xB4))
1030	#define SYS_ERR_INT_STAT ((volatile uint32_t ) (USB_BASE_ADDR + 0xB8))
1031	#define SYS_ERR_INT_CLR ((volatile uint32_t ) (USB_BASE_ADDR + 0xBC))
1032	#define SYS_ERR_INT_SET ((volatile uint32_t ) (USB_BASE_ADDR + 0xC0))
1033
1034
1035	/* USB Host Controller */
1036	#define USBHC_BASE_ADDR 0xFFE0C000
1037	#define HC_REVISION ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x00))
1038	#define HC_CONTROL ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x04))
1039	#define HC_CMD_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x08))
1040	#define HC_INT_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x0C))
1041	#define HC_INT_EN ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x10))
1042	#define HC_INT_DIS ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x14))
1043	#define HC_HCCA ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x18))
1044	#define HC_PERIOD_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x1C))
1045	#define HC_CTRL_HEAD_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x20))
1046	#define HC_CTRL_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x24))
1047	#define HC_BULK_HEAD_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x28))
1048	#define HC_BULK_CUR_ED ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x2C))
1049	#define HC_DONE_HEAD ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x30))
1050	#define HC_FM_INTERVAL ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x34))
1051	#define HC_FM_REMAINING ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x38))
1052	#define HC_FM_NUMBER ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x3C))
1053	#define HC_PERIOD_START ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x40))
1054	#define HC_LS_THRHLD ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x44))
1055	#define HC_RH_DESCA ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x48))
1056	#define HC_RH_DESCB ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x4C))
1057	#define HC_RH_STAT ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x50))
1058	#define HC_RH_PORT_STAT1 ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x54))
1059	#define HC_RH_PORT_STAT2 ((volatile uint32_t ) (USBHC_BASE_ADDR + 0x58))
1060
1061	/* USB OTG Controller */
1062	#define USBOTG_BASE_ADDR 0xFFE0C100
1063	#define OTG_INT_STAT ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x00))
1064	#define OTG_INT_EN ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x04))
1065	#define OTG_INT_SET ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x08))
1066	#define OTG_INT_CLR ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x0C))
1067	#define OTG_STAT_CTRL ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x10))
1068	#define OTG_TIMER ((volatile uint32_t ) (USBOTG_BASE_ADDR + 0x14))
1069
1070	#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1071	#define OTG_I2C_RX ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x00))
1072	#define OTG_I2C_TX ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x00))
1073	#define OTG_I2C_STS ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x04))
1074	#define OTG_I2C_CTL ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x08))
1075	#define OTG_I2C_CLKHI ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x0C))
1076	#define OTG_I2C_CLKLO ((volatile uint32_t ) (USBOTG_I2C_BASE_ADDR + 0x10))
1077
1078	#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1079	#define OTG_CLK_CTRL ((volatile uint32_t ) (USBOTG_CLK_BASE_ADDR + 0x04))
1080	#define OTG_CLK_STAT ((volatile uint32_t ) (USBOTG_CLK_BASE_ADDR + 0x08))
1081
1082
1083	/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1084	#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
1085	#define MAC_MAC1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1086	#define MAC_MAC2 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1087	#define MAC_IPGT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1088	#define MAC_IPGR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1089	#define MAC_CLRT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1090	#define MAC_MAXF ((volatile uint32_t ) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1091	#define MAC_SUPP ((volatile uint32_t ) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1092	#define MAC_TEST ((volatile uint32_t ) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1093	#define MAC_MCFG ((volatile uint32_t ) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1094	#define MAC_MCMD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1095	#define MAC_MADR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1096	#define MAC_MWTD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1097	#define MAC_MRDD ((volatile uint32_t ) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1098	#define MAC_MIND ((volatile uint32_t ) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1099
1100	#define MAC_SA0 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1101	#define MAC_SA1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1102	#define MAC_SA2 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1103
1104	#define MAC_COMMAND ((volatile uint32_t ) (MAC_BASE_ADDR + 0x100)) /* Command reg */
1105	#define MAC_STATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1106	#define MAC_RXDESCRIPTOR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1107	#define MAC_RXSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1108	#define MAC_RXDESCRIPTORNUM ((volatile uint32_t ) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1109	#define MAC_RXPRODUCEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1110	#define MAC_RXCONSUMEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1111	#define MAC_TXDESCRIPTOR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1112	#define MAC_TXSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1113	#define MAC_TXDESCRIPTORNUM ((volatile uint32_t ) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1114	#define MAC_TXPRODUCEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1115	#define MAC_TXCONSUMEINDEX ((volatile uint32_t ) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1116
1117	#define MAC_TSV0 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1118	#define MAC_TSV1 ((volatile uint32_t ) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1119	#define MAC_RSV ((volatile uint32_t ) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1120
1121	#define MAC_FLOWCONTROLCNT ((volatile uint32_t ) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1122	#define MAC_FLOWCONTROLSTS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1123
1124	#define MAC_RXFILTERCTRL ((volatile uint32_t ) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1125	#define MAC_RXFILTERWOLSTS ((volatile uint32_t ) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1126	#define MAC_RXFILTERWOLCLR ((volatile uint32_t ) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1127
1128	#define MAC_HASHFILTERL ((volatile uint32_t ) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1129	#define MAC_HASHFILTERH ((volatile uint32_t ) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1130
1131	#define MAC_INTSTATUS ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1132	#define MAC_INTENABLE ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
1133	#define MAC_INTCLEAR ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1134	#define MAC_INTSET ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1135
1136	#define MAC_POWERDOWN ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1137	#define MAC_MODULEID ((volatile uint32_t ) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1138
1139	/* LCD Controller */
1140
1141	#define LCD_BASE_ADDR 0xFFE10000
1142	#define LCD_CFG ((volatile uint32_t ) 0xE01FC1B8)
1143	#define LCD_TIMH ((volatile uint32_t ) (LCD_BASE_ADDR + 0x000))
1144	#define LCD_TIMV ((volatile uint32_t ) (LCD_BASE_ADDR + 0x004))
1145	#define LCD_POL ((volatile uint32_t ) (LCD_BASE_ADDR + 0x008))
1146	#define LCD_LE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x00C))
1147	#define LCD_UPBASE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x010))
1148	#define LCD_LPBASE ((volatile uint32_t ) (LCD_BASE_ADDR + 0x014))
1149	#define LCD_CTRL ((volatile uint32_t ) (LCD_BASE_ADDR + 0x018))
1150	#define LCD_INTMSK ((volatile uint32_t ) (LCD_BASE_ADDR + 0x01C))
1151	#define LCD_INTRAW ((volatile uint32_t ) (LCD_BASE_ADDR + 0x020))
1152	#define LCD_INTSTAT ((volatile uint32_t ) (LCD_BASE_ADDR + 0x024))
1153	#define LCD_INTCLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x028))
1154	#define LCD_UPCURR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x02C))
1155	#define LCD_LPCURR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x030))
1156	#define LCD_PAL_ADDR ((volatile uint32_t ) (LCD_BASE_ADDR + 0x200))
1157	#define CRSR_IMG ((volatile uint32_t ) (LCD_BASE_ADDR + 0x800))
1158	#define CRSR_CTLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC00))
1159	#define CRSR_CFG ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC04))
1160	#define CRSR_PAL0 ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC08))
1161	#define CRSR_PAL1 ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC0C))
1162	#define CRSR_XY ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC10))
1163	#define CRSR_CLIP ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC14))
1164	#define CRSR_INTMSK ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC20))
1165	#define CRSR_INTCLR ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC24))
1166	#define CRSR_INTRAW ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC28))
1167	#define CRSR_INTSTAT ((volatile uint32_t ) (LCD_BASE_ADDR + 0xC2C))
1168
1169	/* Register Fields */
1170
1171	/* CLKSRCSEL */
1172
1173	#define CLKSRCSEL_CLKSRC_MASK 0x00000003U
1174
1175	#define GET_CLKSRCSEL_CLKSRC( reg) \
1176	GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
1177
1178	#define SET_CLKSRCSEL_CLKSRC( reg, val) \
1179	SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
1180
1181	/* PLLCON */
1182
1183	#define PLLCON_PLLE 0x00000001U
1184
1185	#define PLLCON_PLLC 0x00000002U
1186
1187	/* PLLCFG */
1188
1189	#define PLLCFG_MSEL_MASK 0x00007fffU
1190
1191	#define GET_PLLCFG_MSEL( reg) \
1192	GET_FIELD( reg, PLLCFG_MSEL_MASK, 0)
1193
1194	#define SET_PLLCFG_MSEL( reg, val) \
1195	SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
1196
1197	#define PLLCFG_NSEL_MASK 0x00ff0000U
1198
1199	#define GET_PLLCFG_NSEL( reg) \
1200	GET_FIELD( reg, PLLCFG_NSEL_MASK, 16)
1201
1202	#define SET_PLLCFG_NSEL( reg, val) \
1203	SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
1204
1205	/* PLLSTAT */
1206
1207	#define PLLSTAT_MSEL_MASK 0x00007fffU
1208
1209	#define GET_PLLSTAT_MSEL( reg) \
1210	GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
1211
1212	#define SET_PLLSTAT_MSEL( reg, val) \
1213	SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
1214
1215	#define PLLSTAT_NSEL_MASK 0x00ff0000U
1216
1217	#define GET_PLLSTAT_NSEL( reg) \
1218	GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
1219
1220	#define SET_PLLSTAT_NSEL( reg, val) \
1221	SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
1222
1223	#define PLLSTAT_PLLE 0x01000000U
1224
1225	#define PLLSTAT_PLLC 0x02000000U
1226
1227	#define PLLSTAT_PLOCK 0x04000000U
1228
1229	/* CCLKCFG */
1230
1231	#define CCLKCFG_CCLKSEL_MASK 0x000000ffU
1232
1233	#define GET_CCLKCFG_CCLKSEL( reg) \
1234	GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
1235
1236	#define SET_CCLKCFG_CCLKSEL( reg, val) \
1237	SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
1238
1239	/* MEMMAP */
1240
1241	#define MEMMAP_MAP_MASK 0x00000003U
1242
1243	#define GET_MEMMAP_MAP( reg) \
1244	GET_FIELD( reg, MEMMAP_MAP_MASK, 0)
1245
1246	#define SET_MEMMAP_MAP( reg, val) \
1247	SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
1248
1249	/* TIR */
1250
1251	#define TIR_MR0 0x00000001U
1252
1253	#define TIR_MR1 0x00000002U
1254
1255	#define TIR_MR2 0x00000004U
1256
1257	#define TIR_MR3 0x00000008U
1258
1259	#define TIR_CR0 0x00000010U
1260
1261	#define TIR_CR1 0x00000020U
1262
1263	#define TIR_CR2 0x00000040U
1264
1265	#define TIR_CR3 0x00000080U
1266
1267	/* TCR */
1268
1269	#define TCR_EN 0x00000001U
1270
1271	#define TCR_RST 0x00000002U
1272
1273	/* TMCR */
1274
1275	#define TMCR_MR0I 0x00000001U
1276
1277	#define TMCR_MR0R 0x00000002U
1278
1279	#define TMCR_MR0S 0x00000004U
1280
1281	#define TMCR_MR1I 0x00000008U
1282
1283	#define TMCR_MR1R 0x00000010U
1284
1285	#define TMCR_MR1S 0x00000020U
1286
1287	#define TMCR_MR2I 0x00000040U
1288
1289	#define TMCR_MR2R 0x00000080U
1290
1291	#define TMCR_MR2S 0x00000100U
1292
1293	#define TMCR_MR3I 0x00000200U
1294
1295	#define TMCR_MR3R 0x00000400U
1296
1297	#define TMCR_MR3S 0x00000800U
1298
1299	/* PCLKSEL0 */
1300
1301	#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
1302
1303	#define GET_PCLKSEL0_PCLK_WDT( reg) \
1304	GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
1305
1306	#define SET_PCLKSEL0_PCLK_WDT( reg, val) \
1307	SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
1308
1309	#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
1310
1311	#define GET_PCLKSEL0_PCLK_TIMER0( reg) \
1312	GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1313
1314	#define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
1315	SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
1316
1317	#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
1318
1319	#define GET_PCLKSEL0_PCLK_TIMER1( reg) \
1320	GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1321
1322	#define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
1323	SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
1324
1325	#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
1326
1327	#define GET_PCLKSEL0_PCLK_UART0( reg) \
1328	GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
1329
1330	#define SET_PCLKSEL0_PCLK_UART0( reg, val) \
1331	SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
1332
1333	#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
1334
1335	#define GET_PCLKSEL0_PCLK_UART1( reg) \
1336	GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
1337
1338	#define SET_PCLKSEL0_PCLK_UART1( reg, val) \
1339	SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
1340
1341	#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
1342
1343	#define GET_PCLKSEL0_PCLK_PWM0( reg) \
1344	GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
1345
1346	#define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
1347	SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
1348
1349	#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
1350
1351	#define GET_PCLKSEL0_PCLK_PWM1( reg) \
1352	GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
1353
1354	#define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
1355	SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
1356
1357	#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
1358
1359	#define GET_PCLKSEL0_PCLK_I2C0( reg) \
1360	GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
1361
1362	#define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
1363	SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
1364
1365	#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
1366
1367	#define GET_PCLKSEL0_PCLK_SPI( reg) \
1368	GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
1369
1370	#define SET_PCLKSEL0_PCLK_SPI( reg, val) \
1371	SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
1372
1373	#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
1374
1375	#define GET_PCLKSEL0_PCLK_RTC( reg) \
1376	GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
1377
1378	#define SET_PCLKSEL0_PCLK_RTC( reg, val) \
1379	SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
1380
1381	#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
1382
1383	#define GET_PCLKSEL0_PCLK_SSP1( reg) \
1384	GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
1385
1386	#define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
1387	SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
1388
1389	#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
1390
1391	#define GET_PCLKSEL0_PCLK_DAC( reg) \
1392	GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
1393
1394	#define SET_PCLKSEL0_PCLK_DAC( reg, val) \
1395	SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
1396
1397	#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
1398
1399	#define GET_PCLKSEL0_PCLK_ADC( reg) \
1400	GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
1401
1402	#define SET_PCLKSEL0_PCLK_ADC( reg, val) \
1403	SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
1404
1405	#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
1406
1407	#define GET_PCLKSEL0_PCLK_CAN1( reg) \
1408	GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
1409
1410	#define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
1411	SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
1412
1413	#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
1414
1415	#define GET_PCLKSEL0_PCLK_CAN2( reg) \
1416	GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
1417
1418	#define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
1419	SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
1420
1421	/* PCLKSEL1 */
1422
1423	#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
1424
1425	#define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
1426	GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1427
1428	#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
1429	SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
1430
1431	#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
1432
1433	#define GET_PCLKSEL1_PCLK_GPIO( reg) \
1434	GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
1435
1436	#define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
1437	SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
1438
1439	#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
1440
1441	#define GET_PCLKSEL1_PCLK_PCB( reg) \
1442	GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
1443
1444	#define SET_PCLKSEL1_PCLK_PCB( reg, val) \
1445	SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
1446
1447	#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
1448
1449	#define GET_PCLKSEL1_PCLK_I2C1( reg) \
1450	GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
1451
1452	#define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
1453	SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
1454
1455	#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
1456
1457	#define GET_PCLKSEL1_PCLK_SSP0( reg) \
1458	GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
1459
1460	#define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
1461	SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
1462
1463	#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
1464
1465	#define GET_PCLKSEL1_PCLK_TIMER2( reg) \
1466	GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1467
1468	#define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
1469	SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
1470
1471	#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
1472
1473	#define GET_PCLKSEL1_PCLK_TIMER3( reg) \
1474	GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1475
1476	#define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
1477	SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
1478
1479	#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
1480
1481	#define GET_PCLKSEL1_PCLK_UART2( reg) \
1482	GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
1483
1484	#define SET_PCLKSEL1_PCLK_UART2( reg, val) \
1485	SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
1486
1487	#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
1488
1489	#define GET_PCLKSEL1_PCLK_UART3( reg) \
1490	GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
1491
1492	#define SET_PCLKSEL1_PCLK_UART3( reg, val) \
1493	SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
1494
1495	#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
1496
1497	#define GET_PCLKSEL1_PCLK_I2C2( reg) \
1498	GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
1499
1500	#define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
1501	SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
1502
1503	#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
1504
1505	#define GET_PCLKSEL1_PCLK_I2S( reg) \
1506	GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
1507
1508	#define SET_PCLKSEL1_PCLK_I2S( reg, val) \
1509	SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
1510
1511	#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
1512
1513	#define GET_PCLKSEL1_PCLK_MCI( reg) \
1514	GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
1515
1516	#define SET_PCLKSEL1_PCLK_MCI( reg, val) \
1517	SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
1518
1519	#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
1520
1521	#define GET_PCLKSEL1_PCLK_SYSCON( reg) \
1522	GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1523
1524	#define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
1525	SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
1526
1527	/* RTC_ILR */
1528
1529	#define RTC_ILR_RTCCIF 0x00000001U
1530
1531	#define RTC_ILR_RTCALF 0x00000002U
1532
1533	#define RTC_ILR_RTSSF 0x00000004U
1534
1535	/* RTC_CCR */
1536
1537	#define RTC_CCR_CLKEN 0x00000001U
1538
1539	#define RTC_CCR_CTCRST 0x00000002U
1540
1541	#define RTC_CCR_CLKSRC 0x00000010U
1542
1543	/* SSP */
1544
1545	typedef struct {
1546	uint32_t cr0;
1547	uint32_t cr1;
1548	uint32_t dr;
1549	uint32_t sr;
1550	uint32_t cpsr;
1551	uint32_t imsc;
1552	uint32_t ris;
1553	uint32_t mis;
1554	uint32_t icr;
1555	uint32_t dmacr;
1556	} lpc24xx_ssp;
1557
1558	/* SSP_CR0 */
1559
1560	#define SSP_CR0_DSS_MASK 0x0000000fU
1561
1562	#define GET_SSP_CR0_DSS( reg) \
1563	GET_FIELD( reg, SSP_CR0_DSS_MASK, 0)
1564
1565	#define SET_SSP_CR0_DSS( reg, val) \
1566	SET_FIELD( reg, val, SSP_CR0_DSS_MASK, 0)
1567
1568	#define SSP_CR0_FRF_MASK 0x00000030U
1569
1570	#define GET_SSP_CR0_FRF( reg) \
1571	GET_FIELD( reg, SSP_CR0_FRF_MASK, 4)
1572
1573	#define SET_SSP_CR0_FRF( reg, val) \
1574	SET_FIELD( reg, val, SSP_CR0_FRF_MASK, 4)
1575
1576	#define SSP_CR0_CPOL 0x00000040U
1577
1578	#define SSP_CR0_CPHA 0x00000080U
1579
1580	#define SSP_CR0_SCR_MASK 0x0000ff00U
1581
1582	#define GET_SSP_CR0_SCR( reg) \
1583	GET_FIELD( reg, SSP_CR0_SCR_MASK, 8)
1584
1585	#define SET_SSP_CR0_SCR( reg, val) \
1586	SET_FIELD( reg, val, SSP_CR0_SCR_MASK, 8)
1587
1588	/* SSP_CR1 */
1589
1590	#define SSP_CR1_LBM 0x00000001U
1591
1592	#define SSP_CR1_SSE 0x00000002U
1593
1594	#define SSP_CR1_MS 0x00000004U
1595
1596	#define SSP_CR1_SOD 0x00000008U
1597
1598	/* SSP_SR */
1599
1600	#define SSP_SR_TFE 0x00000001U
1601
1602	#define SSP_SR_TNF 0x00000002U
1603
1604	#define SSP_SR_RNE 0x00000004U
1605
1606	#define SSP_SR_RFF 0x00000008U
1607
1608	#define SSP_SR_BSY 0x00000010U
1609
1610	/* SSP_IMSC */
1611
1612	#define SSP_IMSC_RORIM 0x00000001U
1613
1614	#define SSP_IMSC_RTIM 0x00000002U
1615
1616	#define SSP_IMSC_RXIM 0x00000004U
1617
1618	#define SSP_IMSC_TXIM 0x00000008U
1619
1620	/* SSP_RIS */
1621
1622	#define SSP_RIS_RORRIS 0x00000001U
1623
1624	#define SSP_RIS_RTRIS 0x00000002U
1625
1626	#define SSP_RIS_RXRIS 0x00000004U
1627
1628	#define SSP_RIS_TXRIS 0x00000008U
1629
1630	/* SSP_MIS */
1631
1632	#define SSP_MIS_RORRIS 0x00000001U
1633
1634	#define SSP_MIS_RTRIS 0x00000002U
1635
1636	#define SSP_MIS_RXRIS 0x00000004U
1637
1638	#define SSP_MIS_TXRIS 0x00000008U
1639
1640	/* SSP_ICR */
1641
1642	#define SSP_ICR_RORRIS 0x00000001U
1643
1644	#define SSP_ICR_RTRIS 0x00000002U
1645
1646	#define SSP_ICR_RXRIS 0x00000004U
1647
1648	#define SSP_ICR_TXRIS 0x00000008U
1649
1650	/* SSP_DMACR */
1651
1652	#define SSP_DMACR_RXDMAE 0x00000001U
1653
1654	#define SSP_DMACR_TXDMAE 0x00000002U
1655
1656	/* GPDMA */
1657
1658	typedef struct {
1659	uint32_t src;
1660	uint32_t dest;
1661	uint32_t lli;
1662	uint32_t ctrl;
1663	} lpc24xx_dma_descriptor;
1664
1665	typedef struct {
1666	lpc24xx_dma_descriptor desc;
1667	uint32_t cfg;
1668	} lpc24xx_dma_channel;
1669
1670	#define GPDMA_CH_NUMBER 2
1671
1672	#define GPDMA_STATUS_CH_0 0x00000001U
1673
1674	#define GPDMA_STATUS_CH_1 0x00000002U
1675
1676	#define GPDMA_CH_BASE_ADDR( i) \
1677	((volatile lpc24xx_dma_channel *) \
1678	((i) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR))
1679
1680	/* GPDMA_CONFIG */
1681
1682	#define GPDMA_CONFIG_EN 0x00000001U
1683
1684	#define GPDMA_CONFIG_MODE 0x00000002U
1685
1686	/* GPDMA_ENABLED_CHNS */
1687
1688	#define GPDMA_ENABLED_CHNS_CH0 0x00000001U
1689
1690	#define GPDMA_ENABLED_CHNS_CH1 0x00000002U
1691
1692	/* GPDMA_CH_CTRL */
1693
1694	#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU
1695
1696	#define GET_GPDMA_CH_CTRL_TSZ( reg) \
1697	GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0)
1698
1699	#define SET_GPDMA_CH_CTRL_TSZ( reg, val) \
1700	SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0)
1701
1702	#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU
1703
1704	#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U
1705
1706	#define GET_GPDMA_CH_CTRL_SBSZ( reg) \
1707	GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1708
1709	#define SET_GPDMA_CH_CTRL_SBSZ( reg, val) \
1710	SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12)
1711
1712	#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U
1713
1714	#define GET_GPDMA_CH_CTRL_DBSZ( reg) \
1715	GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1716
1717	#define SET_GPDMA_CH_CTRL_DBSZ( reg, val) \
1718	SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15)
1719
1720	#define GPDMA_CH_CTRL_BSZ_1 0x00000000U
1721
1722	#define GPDMA_CH_CTRL_BSZ_4 0x00000001U
1723
1724	#define GPDMA_CH_CTRL_BSZ_8 0x00000002U
1725
1726	#define GPDMA_CH_CTRL_BSZ_16 0x00000003U
1727
1728	#define GPDMA_CH_CTRL_BSZ_32 0x00000004U
1729
1730	#define GPDMA_CH_CTRL_BSZ_64 0x00000005U
1731
1732	#define GPDMA_CH_CTRL_BSZ_128 0x00000006U
1733
1734	#define GPDMA_CH_CTRL_BSZ_256 0x00000007U
1735
1736	#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U
1737
1738	#define GET_GPDMA_CH_CTRL_SW( reg) \
1739	GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18)
1740
1741	#define SET_GPDMA_CH_CTRL_SW( reg, val) \
1742	SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18)
1743
1744	#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U
1745
1746	#define GET_GPDMA_CH_CTRL_DW( reg) \
1747	GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21)
1748
1749	#define SET_GPDMA_CH_CTRL_DW( reg, val) \
1750	SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21)
1751
1752	#define GPDMA_CH_CTRL_W_8 0x00000000U
1753
1754	#define GPDMA_CH_CTRL_W_16 0x00000001U
1755
1756	#define GPDMA_CH_CTRL_W_32 0x00000002U
1757
1758	#define GPDMA_CH_CTRL_SI 0x04000000U
1759
1760	#define GPDMA_CH_CTRL_DI 0x08000000U
1761
1762	#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U
1763
1764	#define GET_GPDMA_CH_CTRL_PROT( reg) \
1765	GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28)
1766
1767	#define SET_GPDMA_CH_CTRL_PROT( reg, val) \
1768	SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28)
1769
1770	#define GPDMA_CH_CTRL_ITC 0x80000000U
1771
1772	/* GPDMA_CH_CFG */
1773
1774	#define GPDMA_CH_CFG_EN 0x00000001U
1775
1776	#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU
1777
1778	#define GET_GPDMA_CH_CFG_SRCPER( reg) \
1779	GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1)
1780
1781	#define SET_GPDMA_CH_CFG_SRCPER( reg, val) \
1782	SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1)
1783
1784	#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U
1785
1786	#define GET_GPDMA_CH_CFG_DESTPER( reg) \
1787	GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6)
1788
1789	#define SET_GPDMA_CH_CFG_DESTPER( reg, val) \
1790	SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6)
1791
1792	#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U
1793
1794	#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U
1795
1796	#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U
1797
1798	#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U
1799
1800	#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U
1801
1802	#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U
1803
1804	#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U
1805
1806	#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U
1807
1808	#define GET_GPDMA_CH_CFG_FLOW( reg) \
1809	GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11)
1810
1811	#define SET_GPDMA_CH_CFG_FLOW( reg, val) \
1812	SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11)
1813
1814	#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U
1815
1816	#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U
1817
1818	#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U
1819
1820	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U
1821
1822	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U
1823
1824	#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U
1825
1826	#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U
1827
1828	#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U
1829
1830	#define GPDMA_CH_CFG_IE 0x00004000U
1831
1832	#define GPDMA_CH_CFG_ITC 0x00008000U
1833
1834	#define GPDMA_CH_CFG_LOCK 0x00010000U
1835
1836	#define GPDMA_CH_CFG_ACTIVE 0x00020000U
1837
1838	#define GPDMA_CH_CFG_HALT 0x00040000U
1839
1840	/* Ethernet (MAC) */
1841
1842	typedef struct {
1843	uint32_t start;
1844	uint32_t control;
1845	} lpc24xx_eth_transfer_descriptor;
1846
1847	typedef struct {
1848	uint32_t status;
1849	uint32_t hash_crc;
1850	} lpc24xx_eth_receive_info;
1851
1852	#define ETH_TRANSFER_DESCRIPTOR_SIZE 8
1853
1854	#define ETH_RECEIVE_INFO_SIZE 8
1855
1856	#define ETH_TRANSMIT_STATUS_SIZE 4
1857
1858	/* ETH_RX_CTRL */
1859
1860	#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
1861
1862	#define GET_ETH_RX_CTRL_SIZE( reg) \
1863	GET_FIELD( reg, ETH_RX_CTRL_SIZE_MASK, 0)
1864
1865	#define SET_ETH_RX_CTRL_SIZE( reg, val) \
1866	SET_FIELD( reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
1867
1868	#define ETH_RX_CTRL_INTERRUPT 0x80000000U
1869
1870	/* ETH_RX_STAT */
1871
1872	#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
1873
1874	#define GET_ETH_RX_STAT_RXSIZE( reg) \
1875	GET_FIELD( reg, ETH_RX_STAT_RXSIZE_MASK, 0)
1876
1877	#define SET_ETH_RX_STAT_RXSIZE( reg, val) \
1878	SET_FIELD( reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
1879
1880	#define ETH_RX_STAT_BYTES 0x00000100U
1881
1882	#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
1883
1884	#define ETH_RX_STAT_VLAN 0x00080000U
1885
1886	#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
1887
1888	#define ETH_RX_STAT_MULTICAST 0x00200000U
1889
1890	#define ETH_RX_STAT_BROADCAST 0x00400000U
1891
1892	#define ETH_RX_STAT_CRC_ERROR 0x00800000U
1893
1894	#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
1895
1896	#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
1897
1898	#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
1899
1900	#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
1901
1902	#define ETH_RX_STAT_OVERRUN 0x10000000U
1903
1904	#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
1905
1906	#define ETH_RX_STAT_LAST_FLAG 0x40000000U
1907
1908	#define ETH_RX_STAT_ERROR 0x80000000U
1909
1910	/* ETH_TX_CTRL */
1911
1912	#define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
1913
1914	#define GET_ETH_TX_CTRL_SIZE( reg) \
1915	GET_FIELD( reg, ETH_TX_CTRL_SIZE_MASK, 0)
1916
1917	#define SET_ETH_TX_CTRL_SIZE( reg, val) \
1918	SET_FIELD( reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
1919
1920	#define ETH_TX_CTRL_OVERRIDE 0x04000000U
1921
1922	#define ETH_TX_CTRL_HUGE 0x08000000U
1923
1924	#define ETH_TX_CTRL_PAD 0x10000000U
1925
1926	#define ETH_TX_CTRL_CRC 0x20000000U
1927
1928	#define ETH_TX_CTRL_LAST 0x40000000U
1929
1930	#define ETH_TX_CTRL_INTERRUPT 0x80000000U
1931
1932	/* ETH_TX_STAT */
1933
1934	#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
1935
1936	#define GET_ETH_TX_STAT_COLLISION_COUNT( reg) \
1937	GET_FIELD( reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
1938
1939	#define SET_ETH_TX_STAT_COLLISION_COUNT( reg, val) \
1940	SET_FIELD( reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
1941
1942	#define ETH_TX_STAT_DEFER 0x02000000U
1943
1944	#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
1945
1946	#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
1947
1948	#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
1949
1950	#define ETH_TX_STAT_UNDERRUN 0x20000000U
1951
1952	#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
1953
1954	#define ETH_TX_STAT_ERROR 0x80000000U
1955
1956	/* ETH_INT */
1957
1958	#define ETH_INT_RX_OVERRUN 0x00000001U
1959
1960	#define ETH_INT_RX_ERROR 0x00000002U
1961
1962	#define ETH_INT_RX_FINISHED 0x00000004U
1963
1964	#define ETH_INT_RX_DONE 0x00000008U
1965
1966	#define ETH_INT_TX_UNDERRUN 0x00000010U
1967
1968	#define ETH_INT_TX_ERROR 0x00000020U
1969
1970	#define ETH_INT_TX_FINISHED 0x00000040U
1971
1972	#define ETH_INT_TX_DONE 0x00000080U
1973
1974	#define ETH_INT_SOFT 0x00001000U
1975
1976	#define ETH_INT_WAKEUP 0x00002000U
1977
1978	/* ETH_RX_FIL_CTRL */
1979
1980	#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
1981
1982	#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
1983
1984	#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
1985
1986	#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
1987
1988	#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
1989
1990	#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
1991
1992	#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
1993
1994	#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
1995
1996	/* ETH_CMD */
1997
1998	#define ETH_CMD_RX_ENABLE 0x00000001U
1999
2000	#define ETH_CMD_TX_ENABLE 0x00000002U
2001
2002	#define ETH_CMD_REG_RESET 0x00000008U
2003
2004	#define ETH_CMD_TX_RESET 0x00000010U
2005
2006	#define ETH_CMD_RX_RESET 0x00000020U
2007
2008	#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
2009
2010	#define ETH_CMD_PASS_RX_FILTER 0X00000080U
2011
2012	#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
2013
2014	#define ETH_CMD_RMII 0x00000200U
2015
2016	#define ETH_CMD_FULL_DUPLEX 0x00000400U
2017
2018	/* ETH_STAT */
2019
2020	#define ETH_STAT_RX_ACTIVE 0x00000001U
2021
2022	#define ETH_STAT_TX_ACTIVE 0x00000002U
2023
2024	/* AHBCFG */
2025
2026	#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U
2027
2028	#define AHBCFG_BREAK_BURST_MASK 0x00000006U
2029
2030	#define GET_AHBCFG_BREAK_BURST( reg) \
2031	GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1)
2032
2033	#define SET_AHBCFG_BREAK_BURST( reg, val) \
2034	SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1)
2035
2036	#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U
2037
2038	#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U
2039
2040	#define GET_AHBCFG_QUANTUM_SIZE( reg) \
2041	GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4)
2042
2043	#define SET_AHBCFG_QUANTUM_SIZE( reg, val) \
2044	SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4)
2045
2046	#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U
2047
2048	#define GET_AHBCFG_DEFAULT_MASTER( reg) \
2049	GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8)
2050
2051	#define SET_AHBCFG_DEFAULT_MASTER( reg, val) \
2052	SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8)
2053
2054	#define AHBCFG_EP1_MASK 0x00007000U
2055
2056	#define GET_AHBCFG_EP1( reg) \
2057	GET_FIELD( reg, AHBCFG_EP1_MASK, 12)
2058
2059	#define SET_AHBCFG_EP1( reg, val) \
2060	SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12)
2061
2062	#define AHBCFG_EP2_MASK 0x00070000U
2063
2064	#define GET_AHBCFG_EP2( reg) \
2065	GET_FIELD( reg, AHBCFG_EP2_MASK, 16)
2066
2067	#define SET_AHBCFG_EP2( reg, val) \
2068	SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16)
2069
2070	#define AHBCFG_EP3_MASK 0x00700000U
2071
2072	#define GET_AHBCFG_EP3( reg) \
2073	GET_FIELD( reg, AHBCFG_EP3_MASK, 20)
2074
2075	#define SET_AHBCFG_EP3( reg, val) \
2076	SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20)
2077
2078	#define AHBCFG_EP4_MASK 0x07000000U
2079
2080	#define GET_AHBCFG_EP4( reg) \
2081	GET_FIELD( reg, AHBCFG_EP4_MASK, 24)
2082
2083	#define SET_AHBCFG_EP4( reg, val) \
2084	SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24)
2085
2086	#define AHBCFG_EP5_MASK 0x70000000U
2087
2088	#define GET_AHBCFG_EP5( reg) \
2089	GET_FIELD( reg, AHBCFG_EP5_MASK, 28)
2090
2091	#define SET_AHBCFG_EP5( reg, val) \
2092	SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28)
2093
2094	/* EMC */
2095
2096	#define EMC_DYN_CTRL_CE 0x00000001U
2097
2098	#define EMC_DYN_CTRL_CS 0x00000002U
2099
2100	#define EMC_DYN_CTRL_CMD_NORMAL 0x00000000U
2101
2102	#define EMC_DYN_CTRL_CMD_MODE 0x00000080U
2103
2104	#define EMC_DYN_CTRL_CMD_PALL 0x00000100U
2105
2106	#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
2107
2108	typedef struct {
2109	uint32_t cfg;
2110	uint32_t waitwen;
2111	uint32_t waitoen;
2112	uint32_t waitrd;
2113	uint32_t waitpage;
2114	uint32_t waitwr;
2115	uint32_t waitrun;
2116	} lpc24xx_emc_static;
2117
2118	/* I2C */
2119
2120	typedef struct {
2121	uint32_t conset;
2122	uint32_t stat;
2123	uint32_t dat;
2124	uint32_t adr;
2125	uint32_t sclh;
2126	uint32_t scll;
2127	uint32_t conclr;
2128	} lpc24xx_i2c;
2129
2130	#define LPC24XX_I2C_AA (1U << 2U)
2131
2132	#define LPC24XX_I2C_SI (1U << 3U)
2133
2134	#define LPC24XX_I2C_STO (1U << 4U)
2135
2136	#define LPC24XX_I2C_STA (1U << 5U)
2137
2138	#define LPC24XX_I2C_EN (1U << 6U)
2139
2140	/* IO */
2141
2142	typedef struct {
2143	uint32_t dir;
2144	uint32_t reserved [3];
2145	uint32_t mask;
2146	uint32_t pin;
2147	uint32_t set;
2148	uint32_t clr;
2149	} lpc24xx_fio;
2150
2151	#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
2152
2153	#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
2154
2155	#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
2156
2157	/** @} */
2158
2159	#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */

Note: See TracBrowser for help on using the repository browser.

Download in other formats: