[5aeed17] | 1 | /**
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| 2 | * @file
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| 3 | *
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| 4 | * @ingroup lpc24xx
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| 5 | *
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| 6 | * @brief Register definitions.
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| 7 | */
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| 8 |
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| 9 | /*
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| 10 | * Copyright (c) 2008
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| 11 | * Embedded Brains GmbH
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| 12 | * Obere Lagerstr. 30
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| 13 | * D-82178 Puchheim
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| 14 | * Germany
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| 15 | * rtems@embedded-brains.de
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| 16 | *
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| 17 | * The license and distribution terms for this file may be found in the file
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| 18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
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| 19 | */
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| 20 |
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| 21 | #ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
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| 22 | #define LIBBSP_ARM_LPC24XX_LPC24XX_H
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| 23 |
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| 24 | #include <stdint.h>
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| 25 |
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| 26 | #include <libcpu/utility.h>
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| 27 |
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| 28 | /* Vectored Interrupt Controller (VIC) */
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| 29 | #define VIC_BASE_ADDR 0xFFFFF000
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| 30 | #define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
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| 31 | #define VICFIQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x004))
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| 32 | #define VICRawIntr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x008))
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| 33 | #define VICIntSelect (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x00C))
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| 34 | #define VICIntEnable (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x010))
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| 35 | #define VICIntEnClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x014))
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| 36 | #define VICSoftInt (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x018))
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| 37 | #define VICSoftIntClear (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x01C))
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| 38 | #define VICProtection (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x020))
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| 39 | #define VICSWPrioMask (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
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| 40 |
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| 41 | #define VICVectAddrBase ((uint32_t *) (VIC_BASE_ADDR + 0x100))
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| 42 | #define VICVectAddr0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
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| 43 | #define VICVectAddr1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
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| 44 | #define VICVectAddr2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x108))
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| 45 | #define VICVectAddr3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x10C))
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| 46 | #define VICVectAddr4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x110))
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| 47 | #define VICVectAddr5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x114))
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| 48 | #define VICVectAddr6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x118))
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| 49 | #define VICVectAddr7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x11C))
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| 50 | #define VICVectAddr8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x120))
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| 51 | #define VICVectAddr9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x124))
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| 52 | #define VICVectAddr10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x128))
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| 53 | #define VICVectAddr11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x12C))
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| 54 | #define VICVectAddr12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x130))
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| 55 | #define VICVectAddr13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x134))
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| 56 | #define VICVectAddr14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x138))
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| 57 | #define VICVectAddr15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x13C))
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| 58 | #define VICVectAddr16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x140))
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| 59 | #define VICVectAddr17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x144))
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| 60 | #define VICVectAddr18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x148))
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| 61 | #define VICVectAddr19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x14C))
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| 62 | #define VICVectAddr20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x150))
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| 63 | #define VICVectAddr21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x154))
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| 64 | #define VICVectAddr22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x158))
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| 65 | #define VICVectAddr23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x15C))
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| 66 | #define VICVectAddr24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x160))
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| 67 | #define VICVectAddr25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x164))
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| 68 | #define VICVectAddr26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x168))
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| 69 | #define VICVectAddr27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x16C))
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| 70 | #define VICVectAddr28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x170))
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| 71 | #define VICVectAddr29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x174))
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| 72 | #define VICVectAddr30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x178))
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| 73 | #define VICVectAddr31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
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| 74 |
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| 75 | #define VICVectPriorityBase ((uint32_t *) (VIC_BASE_ADDR + 0x200))
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| 76 | #define VICVectPriority( i) (*((volatile uint32_t *) (VIC_BASE_ADDR + 0x200) + (i)))
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| 77 | #define VICVectPriority0 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
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| 78 | #define VICVectPriority1 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
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| 79 | #define VICVectPriority2 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x208))
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| 80 | #define VICVectPriority3 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x20C))
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| 81 | #define VICVectPriority4 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x210))
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| 82 | #define VICVectPriority5 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x214))
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| 83 | #define VICVectPriority6 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x218))
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| 84 | #define VICVectPriority7 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x21C))
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| 85 | #define VICVectPriority8 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x220))
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| 86 | #define VICVectPriority9 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x224))
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| 87 | #define VICVectPriority10 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x228))
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| 88 | #define VICVectPriority11 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x22C))
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| 89 | #define VICVectPriority12 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x230))
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| 90 | #define VICVectPriority13 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x234))
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| 91 | #define VICVectPriority14 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x238))
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| 92 | #define VICVectPriority15 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x23C))
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| 93 | #define VICVectPriority16 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x240))
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| 94 | #define VICVectPriority17 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x244))
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| 95 | #define VICVectPriority18 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x248))
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| 96 | #define VICVectPriority19 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x24C))
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| 97 | #define VICVectPriority20 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x250))
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| 98 | #define VICVectPriority21 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x254))
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| 99 | #define VICVectPriority22 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x258))
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| 100 | #define VICVectPriority23 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x25C))
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| 101 | #define VICVectPriority24 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x260))
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| 102 | #define VICVectPriority25 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x264))
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| 103 | #define VICVectPriority26 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x268))
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| 104 | #define VICVectPriority27 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x26C))
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| 105 | #define VICVectPriority28 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x270))
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| 106 | #define VICVectPriority29 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x274))
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| 107 | #define VICVectPriority30 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x278))
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| 108 | #define VICVectPriority31 (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x27C))
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| 109 |
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| 110 | #define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
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| 111 |
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| 112 |
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| 113 | /* Pin Connect Block */
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| 114 | #define PINSEL_BASE_ADDR 0xE002C000
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| 115 | #define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
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| 116 | #define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
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| 117 | #define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
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| 118 | #define PINSEL3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x0C))
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| 119 | #define PINSEL4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x10))
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| 120 | #define PINSEL5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x14))
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| 121 | #define PINSEL6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x18))
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| 122 | #define PINSEL7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x1C))
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| 123 | #define PINSEL8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x20))
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| 124 | #define PINSEL9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
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| 125 | #define PINSEL10 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
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| 126 |
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| 127 | #define PINMODE0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
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| 128 | #define PINMODE1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x44))
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| 129 | #define PINMODE2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x48))
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| 130 | #define PINMODE3 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x4C))
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| 131 | #define PINMODE4 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x50))
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| 132 | #define PINMODE5 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x54))
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| 133 | #define PINMODE6 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x58))
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| 134 | #define PINMODE7 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x5C))
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| 135 | #define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
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| 136 | #define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
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| 137 |
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| 138 | /* General Purpose Input/Output (GPIO) */
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| 139 | #define GPIO_BASE_ADDR 0xE0028000
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| 140 | #define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
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| 141 | #define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
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| 142 | #define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
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| 143 | #define IOCLR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x0C))
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| 144 | #define IOPIN1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x10))
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| 145 | #define IOSET1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x14))
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| 146 | #define IODIR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x18))
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| 147 | #define IOCLR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
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| 148 |
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| 149 | /* GPIO Interrupt Registers */
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| 150 | #define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
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| 151 | #define IO0_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
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| 152 | #define IO0_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
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| 153 | #define IO0_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
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| 154 | #define IO0_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
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| 155 |
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| 156 | #define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
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| 157 | #define IO2_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
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| 158 | #define IO2_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
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| 159 | #define IO2_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
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| 160 | #define IO2_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xAC))
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| 161 |
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| 162 | #define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
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| 163 |
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| 164 | #define PARTCFG_BASE_ADDR 0x3FFF8000
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| 165 | #define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
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| 166 |
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| 167 | /* Fast I/O setup */
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| 168 | #define FIO_BASE_ADDR 0x3FFFC000
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| 169 | #define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
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| 170 | #define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
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| 171 | #define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
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| 172 | #define FIO0SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
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| 173 | #define FIO0CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
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| 174 |
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| 175 | #define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
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| 176 | #define FIO1MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
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| 177 | #define FIO1PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
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| 178 | #define FIO1SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
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| 179 | #define FIO1CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
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| 180 |
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| 181 | #define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
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| 182 | #define FIO2MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
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| 183 | #define FIO2PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
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| 184 | #define FIO2SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
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| 185 | #define FIO2CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
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| 186 |
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| 187 | #define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
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| 188 | #define FIO3MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
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| 189 | #define FIO3PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
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| 190 | #define FIO3SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
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| 191 | #define FIO3CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
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| 192 |
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| 193 | #define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
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| 194 | #define FIO4MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
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| 195 | #define FIO4PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
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| 196 | #define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
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| 197 | #define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
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| 198 |
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| 199 | /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
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| 200 | #define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
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| 201 | #define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
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| 202 | #define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
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| 203 | #define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
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| 204 | #define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
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| 205 |
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| 206 | #define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
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| 207 | #define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
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| 208 | #define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
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| 209 | #define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
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| 210 | #define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
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| 211 |
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| 212 | #define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
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| 213 | #define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
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| 214 | #define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
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| 215 | #define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
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| 216 | #define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
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| 217 |
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| 218 | #define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x04))
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| 219 | #define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x24))
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| 220 | #define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x44))
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| 221 | #define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x64))
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| 222 | #define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x84))
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| 223 |
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| 224 | #define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
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| 225 | #define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
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| 226 | #define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
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| 227 | #define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
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| 228 | #define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
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| 229 |
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| 230 | #define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
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| 231 | #define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
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| 232 | #define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
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| 233 | #define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
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| 234 | #define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
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| 235 |
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| 236 | #define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
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| 237 | #define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
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| 238 | #define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
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| 239 | #define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
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| 240 | #define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
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| 241 |
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| 242 | #define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
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| 243 | #define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
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| 244 | #define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
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| 245 | #define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
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| 246 | #define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
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| 247 |
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| 248 | #define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
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| 249 | #define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
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| 250 | #define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
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| 251 | #define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
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| 252 | #define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
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| 253 |
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| 254 | #define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
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| 255 | #define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
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| 256 | #define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
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| 257 | #define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
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| 258 | #define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
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| 259 |
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| 260 | #define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
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| 261 | #define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
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| 262 | #define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
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| 263 | #define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
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| 264 | #define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
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| 265 |
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| 266 | #define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
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| 267 | #define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
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| 268 | #define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
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| 269 | #define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
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| 270 | #define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
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| 271 |
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| 272 | #define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
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| 273 | #define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
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| 274 | #define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
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| 275 | #define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
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| 276 | #define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
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| 277 |
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| 278 | #define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
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| 279 | #define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
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| 280 | #define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
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| 281 | #define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
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| 282 | #define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
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| 283 |
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| 284 | #define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
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| 285 | #define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
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| 286 | #define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
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| 287 | #define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
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| 288 | #define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
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| 289 |
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| 290 | #define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
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| 291 | #define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
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| 292 | #define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
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| 293 | #define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
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| 294 | #define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
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| 295 |
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| 296 | #define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
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| 297 | #define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
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| 298 | #define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
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| 299 | #define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
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| 300 | #define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
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| 301 |
|
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| 302 | #define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
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| 303 | #define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
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| 304 | #define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
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| 305 | #define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
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| 306 | #define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
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| 307 |
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| 308 | #define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
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| 309 | #define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
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| 310 | #define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
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| 311 | #define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
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| 312 | #define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
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| 313 |
|
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| 314 | #define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
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| 315 | #define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
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| 316 | #define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
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| 317 | #define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
|
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| 318 | #define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
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| 319 |
|
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| 320 | #define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
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| 321 | #define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
|
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| 322 | #define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
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| 323 | #define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
|
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| 324 | #define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
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| 325 |
|
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| 326 | #define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
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| 327 | #define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
|
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| 328 | #define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
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| 329 | #define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
|
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| 330 | #define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
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| 331 |
|
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| 332 | #define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
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| 333 | #define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
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| 334 | #define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
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| 335 | #define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
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| 336 | #define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
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| 337 |
|
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| 338 | #define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
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| 339 | #define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
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| 340 | #define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
|
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| 341 | #define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
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| 342 | #define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
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| 343 |
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| 344 | #define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
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| 345 | #define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
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| 346 | #define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
|
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| 347 | #define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
|
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| 348 | #define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
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| 349 |
|
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| 350 | #define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
|
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| 351 | #define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
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| 352 | #define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
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| 353 | #define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
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| 354 | #define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
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| 355 |
|
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| 356 | #define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
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| 357 | #define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
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| 358 | #define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
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| 359 | #define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
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| 360 | #define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
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| 361 |
|
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| 362 | #define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
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| 363 | #define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
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| 364 | #define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
|
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| 365 | #define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
|
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| 366 | #define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
|
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| 367 |
|
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| 368 | #define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
|
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| 369 | #define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
|
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| 370 | #define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
|
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| 371 | #define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
|
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| 372 | #define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
|
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| 373 |
|
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| 374 | #define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
|
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| 375 | #define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
|
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| 376 | #define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
|
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| 377 | #define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
|
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| 378 | #define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
|
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| 379 |
|
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| 380 |
|
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| 381 | /* System Control Block(SCB) modules include Memory Accelerator Module,
|
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| 382 | Phase Locked Loop, VPB divider, Power Control, External Interrupt,
|
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| 383 | Reset, and Code Security/Debugging */
|
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| 384 | #define SCB_BASE_ADDR 0xE01FC000
|
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| 385 |
|
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| 386 | /* Memory Accelerator Module (MAM) */
|
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| 387 | #define MAMCR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x000))
|
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| 388 | #define MAMTIM (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x004))
|
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| 389 | #define MEMMAP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x040))
|
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| 390 |
|
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| 391 | /* Phase Locked Loop (PLL) */
|
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| 392 | #define PLLCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x080))
|
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| 393 | #define PLLCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x084))
|
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| 394 | #define PLLSTAT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x088))
|
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| 395 | #define PLLFEED (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x08C))
|
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| 396 |
|
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| 397 | /* Power Control */
|
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| 398 | #define PCON (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C0))
|
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| 399 | #define PCONP (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x0C4))
|
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| 400 |
|
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| 401 | /* Clock Divider */
|
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| 402 | // #define APBDIV (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x100))
|
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| 403 | #define CCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x104))
|
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| 404 | #define USBCLKCFG (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x108))
|
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| 405 | #define CLKSRCSEL (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
|
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| 406 | #define PCLKSEL0 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
|
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| 407 | #define PCLKSEL1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
|
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| 408 |
|
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| 409 | /* External Interrupts */
|
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| 410 | #define EXTINT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
|
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| 411 | #define INTWAKE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
|
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| 412 | #define EXTMODE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x148))
|
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| 413 | #define EXTPOLAR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x14C))
|
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| 414 |
|
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| 415 | /* Reset, reset source identification */
|
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| 416 | #define RSIR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x180))
|
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| 417 |
|
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| 418 | /* RSID, code security protection */
|
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| 419 | #define CSPR (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x184))
|
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| 420 |
|
---|
| 421 | /* AHB configuration */
|
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| 422 | #define AHBCFG1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x188))
|
---|
| 423 | #define AHBCFG2 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
|
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| 424 |
|
---|
| 425 | /* System Controls and Status */
|
---|
| 426 | #define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
|
---|
| 427 |
|
---|
| 428 |
|
---|
| 429 | /* External Memory Controller (EMC) */
|
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| 430 | #define EMC_BASE_ADDR 0xFFE08000
|
---|
| 431 | #define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
|
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| 432 | #define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
|
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| 433 | #define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
|
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| 434 |
|
---|
| 435 | /* Dynamic RAM access registers */
|
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| 436 | #define EMC_DYN_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x020))
|
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| 437 | #define EMC_DYN_RFSH (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x024))
|
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| 438 | #define EMC_DYN_RD_CFG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x028))
|
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| 439 | #define EMC_DYN_RP (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x030))
|
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| 440 | #define EMC_DYN_RAS (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x034))
|
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| 441 | #define EMC_DYN_SREX (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x038))
|
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| 442 | #define EMC_DYN_APR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x03C))
|
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| 443 | #define EMC_DYN_DAL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x040))
|
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| 444 | #define EMC_DYN_WR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x044))
|
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| 445 | #define EMC_DYN_RC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x048))
|
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| 446 | #define EMC_DYN_RFC (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x04C))
|
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| 447 | #define EMC_DYN_XSR (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x050))
|
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| 448 | #define EMC_DYN_RRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x054))
|
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| 449 | #define EMC_DYN_MRD (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x058))
|
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| 450 |
|
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| 451 | #define EMC_DYN_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x100))
|
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| 452 | #define EMC_DYN_RASCAS0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x104))
|
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| 453 | #define EMC_DYN_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x140))
|
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| 454 | #define EMC_DYN_RASCAS1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x144))
|
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| 455 | #define EMC_DYN_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x160))
|
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| 456 | #define EMC_DYN_RASCAS2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x164))
|
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| 457 | #define EMC_DYN_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x180))
|
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| 458 | #define EMC_DYN_RASCAS3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x184))
|
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| 459 |
|
---|
| 460 | /* static RAM access registers */
|
---|
| 461 | #define EMC_STA_CFG0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x200))
|
---|
| 462 | #define EMC_STA_WAITWEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x204))
|
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| 463 | #define EMC_STA_WAITOEN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x208))
|
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| 464 | #define EMC_STA_WAITRD0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x20C))
|
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| 465 | #define EMC_STA_WAITPAGE0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x210))
|
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| 466 | #define EMC_STA_WAITWR0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x214))
|
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| 467 | #define EMC_STA_WAITTURN0 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x218))
|
---|
| 468 |
|
---|
| 469 | #define EMC_STA_CFG1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x220))
|
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| 470 | #define EMC_STA_WAITWEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x224))
|
---|
| 471 | #define EMC_STA_WAITOEN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x228))
|
---|
| 472 | #define EMC_STA_WAITRD1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x22C))
|
---|
| 473 | #define EMC_STA_WAITPAGE1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x230))
|
---|
| 474 | #define EMC_STA_WAITWR1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x234))
|
---|
| 475 | #define EMC_STA_WAITTURN1 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x238))
|
---|
| 476 |
|
---|
| 477 | #define EMC_STA_CFG2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x240))
|
---|
| 478 | #define EMC_STA_WAITWEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x244))
|
---|
| 479 | #define EMC_STA_WAITOEN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x248))
|
---|
| 480 | #define EMC_STA_WAITRD2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x24C))
|
---|
| 481 | #define EMC_STA_WAITPAGE2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x250))
|
---|
| 482 | #define EMC_STA_WAITWR2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x254))
|
---|
| 483 | #define EMC_STA_WAITTURN2 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x258))
|
---|
| 484 |
|
---|
| 485 | #define EMC_STA_CFG3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x260))
|
---|
| 486 | #define EMC_STA_WAITWEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x264))
|
---|
| 487 | #define EMC_STA_WAITOEN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x268))
|
---|
| 488 | #define EMC_STA_WAITRD3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x26C))
|
---|
| 489 | #define EMC_STA_WAITPAGE3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x270))
|
---|
| 490 | #define EMC_STA_WAITWR3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x274))
|
---|
| 491 | #define EMC_STA_WAITTURN3 (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x278))
|
---|
| 492 |
|
---|
| 493 | #define EMC_STA_EXT_WAIT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
|
---|
| 494 |
|
---|
| 495 |
|
---|
| 496 | /* Timer 0 */
|
---|
| 497 | #define TMR0_BASE_ADDR 0xE0004000
|
---|
| 498 | #define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
|
---|
| 499 | #define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
|
---|
| 500 | #define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
|
---|
| 501 | #define T0PR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x0C))
|
---|
| 502 | #define T0PC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x10))
|
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| 503 | #define T0MCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x14))
|
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| 504 | #define T0MR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x18))
|
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| 505 | #define T0MR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x1C))
|
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| 506 | #define T0MR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x20))
|
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| 507 | #define T0MR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x24))
|
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| 508 | #define T0CCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x28))
|
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| 509 | #define T0CR0 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x2C))
|
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| 510 | #define T0CR1 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x30))
|
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| 511 | #define T0CR2 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x34))
|
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| 512 | #define T0CR3 (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x38))
|
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| 513 | #define T0EMR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x3C))
|
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| 514 | #define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
|
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| 515 |
|
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| 516 | /* Timer 1 */
|
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| 517 | #define TMR1_BASE_ADDR 0xE0008000
|
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| 518 | #define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
|
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| 519 | #define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
|
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| 520 | #define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
|
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| 521 | #define T1PR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x0C))
|
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| 522 | #define T1PC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x10))
|
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| 523 | #define T1MCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x14))
|
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| 524 | #define T1MR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x18))
|
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| 525 | #define T1MR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x1C))
|
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| 526 | #define T1MR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x20))
|
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| 527 | #define T1MR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x24))
|
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| 528 | #define T1CCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x28))
|
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| 529 | #define T1CR0 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x2C))
|
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| 530 | #define T1CR1 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x30))
|
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| 531 | #define T1CR2 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x34))
|
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| 532 | #define T1CR3 (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x38))
|
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| 533 | #define T1EMR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x3C))
|
---|
| 534 | #define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
|
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| 535 |
|
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| 536 | /* Timer 2 */
|
---|
| 537 | #define TMR2_BASE_ADDR 0xE0070000
|
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| 538 | #define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
|
---|
| 539 | #define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
|
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| 540 | #define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
|
---|
| 541 | #define T2PR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x0C))
|
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| 542 | #define T2PC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x10))
|
---|
| 543 | #define T2MCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x14))
|
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| 544 | #define T2MR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x18))
|
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| 545 | #define T2MR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x1C))
|
---|
| 546 | #define T2MR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x20))
|
---|
| 547 | #define T2MR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x24))
|
---|
| 548 | #define T2CCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x28))
|
---|
| 549 | #define T2CR0 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x2C))
|
---|
| 550 | #define T2CR1 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x30))
|
---|
| 551 | #define T2CR2 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x34))
|
---|
| 552 | #define T2CR3 (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x38))
|
---|
| 553 | #define T2EMR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x3C))
|
---|
| 554 | #define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
|
---|
| 555 |
|
---|
| 556 | /* Timer 3 */
|
---|
| 557 | #define TMR3_BASE_ADDR 0xE0074000
|
---|
| 558 | #define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
|
---|
| 559 | #define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
|
---|
| 560 | #define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
|
---|
| 561 | #define T3PR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x0C))
|
---|
| 562 | #define T3PC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x10))
|
---|
| 563 | #define T3MCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x14))
|
---|
| 564 | #define T3MR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x18))
|
---|
| 565 | #define T3MR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x1C))
|
---|
| 566 | #define T3MR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x20))
|
---|
| 567 | #define T3MR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x24))
|
---|
| 568 | #define T3CCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x28))
|
---|
| 569 | #define T3CR0 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x2C))
|
---|
| 570 | #define T3CR1 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x30))
|
---|
| 571 | #define T3CR2 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x34))
|
---|
| 572 | #define T3CR3 (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x38))
|
---|
| 573 | #define T3EMR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x3C))
|
---|
| 574 | #define T3CTCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x70))
|
---|
| 575 |
|
---|
| 576 |
|
---|
| 577 | /* Pulse Width Modulator (PWM) */
|
---|
| 578 | #define PWM0_BASE_ADDR 0xE0014000
|
---|
| 579 | #define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
|
---|
| 580 | #define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
|
---|
| 581 | #define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
|
---|
| 582 | #define PWM0PR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x0C))
|
---|
| 583 | #define PWM0PC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x10))
|
---|
| 584 | #define PWM0MCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x14))
|
---|
| 585 | #define PWM0MR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x18))
|
---|
| 586 | #define PWM0MR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x1C))
|
---|
| 587 | #define PWM0MR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x20))
|
---|
| 588 | #define PWM0MR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x24))
|
---|
| 589 | #define PWM0CCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x28))
|
---|
| 590 | #define PWM0CR0 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x2C))
|
---|
| 591 | #define PWM0CR1 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x30))
|
---|
| 592 | #define PWM0CR2 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x34))
|
---|
| 593 | #define PWM0CR3 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x38))
|
---|
| 594 | #define PWM0EMR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x3C))
|
---|
| 595 | #define PWM0MR4 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x40))
|
---|
| 596 | #define PWM0MR5 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x44))
|
---|
| 597 | #define PWM0MR6 (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x48))
|
---|
| 598 | #define PWM0PCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x4C))
|
---|
| 599 | #define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
|
---|
| 600 | #define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
|
---|
| 601 |
|
---|
| 602 | #define PWM1_BASE_ADDR 0xE0018000
|
---|
| 603 | #define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
|
---|
| 604 | #define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
|
---|
| 605 | #define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
|
---|
| 606 | #define PWM1PR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x0C))
|
---|
| 607 | #define PWM1PC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x10))
|
---|
| 608 | #define PWM1MCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x14))
|
---|
| 609 | #define PWM1MR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x18))
|
---|
| 610 | #define PWM1MR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x1C))
|
---|
| 611 | #define PWM1MR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x20))
|
---|
| 612 | #define PWM1MR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x24))
|
---|
| 613 | #define PWM1CCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x28))
|
---|
| 614 | #define PWM1CR0 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x2C))
|
---|
| 615 | #define PWM1CR1 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x30))
|
---|
| 616 | #define PWM1CR2 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x34))
|
---|
| 617 | #define PWM1CR3 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x38))
|
---|
| 618 | #define PWM1EMR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x3C))
|
---|
| 619 | #define PWM1MR4 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x40))
|
---|
| 620 | #define PWM1MR5 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x44))
|
---|
| 621 | #define PWM1MR6 (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x48))
|
---|
| 622 | #define PWM1PCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x4C))
|
---|
| 623 | #define PWM1LER (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x50))
|
---|
| 624 | #define PWM1CTCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x70))
|
---|
| 625 |
|
---|
| 626 |
|
---|
| 627 | /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
|
---|
| 628 | #define UART0_BASE_ADDR 0xE000C000
|
---|
| 629 | #define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
|
---|
| 630 | #define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
|
---|
| 631 | #define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
|
---|
| 632 | #define U0DLM (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
|
---|
| 633 | #define U0IER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x04))
|
---|
| 634 | #define U0IIR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
|
---|
| 635 | #define U0FCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x08))
|
---|
| 636 | #define U0LCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x0C))
|
---|
| 637 | #define U0LSR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x14))
|
---|
| 638 | #define U0SCR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x1C))
|
---|
| 639 | #define U0ACR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x20))
|
---|
| 640 | #define U0ICR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x24))
|
---|
| 641 | #define U0FDR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x28))
|
---|
| 642 | #define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
|
---|
| 643 |
|
---|
| 644 | /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
|
---|
| 645 | #define UART1_BASE_ADDR 0xE0010000
|
---|
| 646 | #define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
|
---|
| 647 | #define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
|
---|
| 648 | #define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
|
---|
| 649 | #define U1DLM (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
|
---|
| 650 | #define U1IER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x04))
|
---|
| 651 | #define U1IIR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
|
---|
| 652 | #define U1FCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x08))
|
---|
| 653 | #define U1LCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x0C))
|
---|
| 654 | #define U1MCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x10))
|
---|
| 655 | #define U1LSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x14))
|
---|
| 656 | #define U1MSR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x18))
|
---|
| 657 | #define U1SCR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x1C))
|
---|
| 658 | #define U1ACR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x20))
|
---|
| 659 | #define U1FDR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x28))
|
---|
| 660 | #define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
|
---|
| 661 |
|
---|
| 662 | /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
|
---|
| 663 | #define UART2_BASE_ADDR 0xE0078000
|
---|
| 664 | #define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
|
---|
| 665 | #define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
|
---|
| 666 | #define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
|
---|
| 667 | #define U2DLM (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
|
---|
| 668 | #define U2IER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x04))
|
---|
| 669 | #define U2IIR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
|
---|
| 670 | #define U2FCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x08))
|
---|
| 671 | #define U2LCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x0C))
|
---|
| 672 | #define U2LSR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x14))
|
---|
| 673 | #define U2SCR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x1C))
|
---|
| 674 | #define U2ACR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x20))
|
---|
| 675 | #define U2ICR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x24))
|
---|
| 676 | #define U2FDR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x28))
|
---|
| 677 | #define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
|
---|
| 678 |
|
---|
| 679 | /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
|
---|
| 680 | #define UART3_BASE_ADDR 0xE007C000
|
---|
| 681 | #define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
|
---|
| 682 | #define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
|
---|
| 683 | #define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
|
---|
| 684 | #define U3DLM (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
|
---|
| 685 | #define U3IER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x04))
|
---|
| 686 | #define U3IIR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
|
---|
| 687 | #define U3FCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x08))
|
---|
| 688 | #define U3LCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x0C))
|
---|
| 689 | #define U3LSR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x14))
|
---|
| 690 | #define U3SCR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x1C))
|
---|
| 691 | #define U3ACR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x20))
|
---|
| 692 | #define U3ICR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x24))
|
---|
| 693 | #define U3FDR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x28))
|
---|
| 694 | #define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
|
---|
| 695 |
|
---|
| 696 | /* I2C Interface 0 */
|
---|
| 697 | #define I2C0_BASE_ADDR 0xE001C000
|
---|
| 698 | #define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
|
---|
| 699 | #define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
|
---|
| 700 | #define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
|
---|
| 701 | #define I20ADR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x0C))
|
---|
| 702 | #define I20SCLH (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x10))
|
---|
| 703 | #define I20SCLL (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x14))
|
---|
| 704 | #define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
|
---|
| 705 |
|
---|
| 706 | /* I2C Interface 1 */
|
---|
| 707 | #define I2C1_BASE_ADDR 0xE005C000
|
---|
| 708 | #define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
|
---|
| 709 | #define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
|
---|
| 710 | #define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
|
---|
| 711 | #define I21ADR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x0C))
|
---|
| 712 | #define I21SCLH (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x10))
|
---|
| 713 | #define I21SCLL (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x14))
|
---|
| 714 | #define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
|
---|
| 715 |
|
---|
| 716 | /* I2C Interface 2 */
|
---|
| 717 | #define I2C2_BASE_ADDR 0xE0080000
|
---|
| 718 | #define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
|
---|
| 719 | #define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
|
---|
| 720 | #define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
|
---|
| 721 | #define I22ADR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x0C))
|
---|
| 722 | #define I22SCLH (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x10))
|
---|
| 723 | #define I22SCLL (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x14))
|
---|
| 724 | #define I22CONCLR (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x18))
|
---|
| 725 |
|
---|
| 726 | /* SPI0 (Serial Peripheral Interface 0) */
|
---|
| 727 | #define SPI0_BASE_ADDR 0xE0020000
|
---|
| 728 | #define S0SPCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x00))
|
---|
| 729 | #define S0SPSR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x04))
|
---|
| 730 | #define S0SPDR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x08))
|
---|
| 731 | #define S0SPCCR (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x0C))
|
---|
| 732 | #define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
|
---|
| 733 |
|
---|
| 734 | /* SSP0 Controller */
|
---|
| 735 | #define SSP0_BASE_ADDR 0xE0068000
|
---|
| 736 | #define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
|
---|
| 737 | #define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
|
---|
| 738 | #define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
|
---|
| 739 | #define SSP0SR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x0C))
|
---|
| 740 | #define SSP0CPSR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x10))
|
---|
| 741 | #define SSP0IMSC (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x14))
|
---|
| 742 | #define SSP0RIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x18))
|
---|
| 743 | #define SSP0MIS (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x1C))
|
---|
| 744 | #define SSP0ICR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x20))
|
---|
| 745 | #define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
|
---|
| 746 |
|
---|
| 747 | /* SSP1 Controller */
|
---|
| 748 | #define SSP1_BASE_ADDR 0xE0030000
|
---|
| 749 | #define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
|
---|
| 750 | #define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
|
---|
| 751 | #define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
|
---|
| 752 | #define SSP1SR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x0C))
|
---|
| 753 | #define SSP1CPSR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x10))
|
---|
| 754 | #define SSP1IMSC (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x14))
|
---|
| 755 | #define SSP1RIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x18))
|
---|
| 756 | #define SSP1MIS (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x1C))
|
---|
| 757 | #define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
|
---|
| 758 | #define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
|
---|
| 759 |
|
---|
| 760 |
|
---|
| 761 | /* Real Time Clock */
|
---|
| 762 | #define RTC_BASE_ADDR 0xE0024000
|
---|
| 763 | #define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
|
---|
| 764 | #define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
|
---|
| 765 | #define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
|
---|
| 766 | #define RTC_CIIR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x0C))
|
---|
| 767 | #define RTC_AMR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x10))
|
---|
| 768 | #define RTC_CTIME0 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x14))
|
---|
| 769 | #define RTC_CTIME1 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x18))
|
---|
| 770 | #define RTC_CTIME2 (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x1C))
|
---|
| 771 | #define RTC_SEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x20))
|
---|
| 772 | #define RTC_MIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x24))
|
---|
| 773 | #define RTC_HOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x28))
|
---|
| 774 | #define RTC_DOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x2C))
|
---|
| 775 | #define RTC_DOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x30))
|
---|
| 776 | #define RTC_DOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x34))
|
---|
| 777 | #define RTC_MONTH (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x38))
|
---|
| 778 | #define RTC_YEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x3C))
|
---|
| 779 | #define RTC_CISS (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x40))
|
---|
| 780 | #define RTC_ALSEC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x60))
|
---|
| 781 | #define RTC_ALMIN (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x64))
|
---|
| 782 | #define RTC_ALHOUR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x68))
|
---|
| 783 | #define RTC_ALDOM (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x6C))
|
---|
| 784 | #define RTC_ALDOW (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x70))
|
---|
| 785 | #define RTC_ALDOY (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x74))
|
---|
| 786 | #define RTC_ALMON (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x78))
|
---|
| 787 | #define RTC_ALYEAR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x7C))
|
---|
| 788 | #define RTC_PREINT (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x80))
|
---|
| 789 | #define RTC_PREFRAC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x84))
|
---|
| 790 |
|
---|
| 791 |
|
---|
| 792 | /* A/D Converter 0 (AD0) */
|
---|
| 793 | #define AD0_BASE_ADDR 0xE0034000
|
---|
| 794 | #define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
|
---|
| 795 | #define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
|
---|
| 796 | #define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
|
---|
| 797 | #define AD0DR0 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
|
---|
| 798 | #define AD0DR1 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
|
---|
| 799 | #define AD0DR2 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x18))
|
---|
| 800 | #define AD0DR3 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x1C))
|
---|
| 801 | #define AD0DR4 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x20))
|
---|
| 802 | #define AD0DR5 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x24))
|
---|
| 803 | #define AD0DR6 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x28))
|
---|
| 804 | #define AD0DR7 (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x2C))
|
---|
| 805 | #define AD0STAT (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x30))
|
---|
| 806 |
|
---|
| 807 |
|
---|
| 808 | /* D/A Converter */
|
---|
| 809 | #define DAC_BASE_ADDR 0xE006C000
|
---|
| 810 | #define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
|
---|
| 811 |
|
---|
| 812 |
|
---|
| 813 | /* Watchdog */
|
---|
| 814 | #define WDG_BASE_ADDR 0xE0000000
|
---|
| 815 | #define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
|
---|
| 816 | #define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
|
---|
| 817 | #define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
|
---|
| 818 | #define WDTV (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x0C))
|
---|
| 819 | #define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
|
---|
| 820 |
|
---|
| 821 | /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
|
---|
| 822 | #define CAN_ACCEPT_BASE_ADDR 0xE003C000
|
---|
| 823 | #define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
|
---|
| 824 | #define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
|
---|
| 825 | #define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
|
---|
| 826 | #define CAN_EFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
|
---|
| 827 | #define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
|
---|
| 828 | #define CAN_EOT (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
|
---|
| 829 | #define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
|
---|
| 830 | #define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
|
---|
| 831 |
|
---|
| 832 | #define CAN_CENTRAL_BASE_ADDR 0xE0040000
|
---|
| 833 | #define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
|
---|
| 834 | #define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
|
---|
| 835 | #define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
|
---|
| 836 |
|
---|
| 837 | #define CAN1_BASE_ADDR 0xE0044000
|
---|
| 838 | #define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
|
---|
| 839 | #define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
|
---|
| 840 | #define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
|
---|
| 841 | #define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
|
---|
| 842 | #define CAN1IER (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
|
---|
| 843 | #define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
|
---|
| 844 | #define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
|
---|
| 845 | #define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
|
---|
| 846 | #define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
|
---|
| 847 | #define CAN1RID (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
|
---|
| 848 | #define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
|
---|
| 849 | #define CAN1RDB (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
|
---|
| 850 |
|
---|
| 851 | #define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
|
---|
| 852 | #define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
|
---|
| 853 | #define CAN1TDA1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
|
---|
| 854 | #define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
|
---|
| 855 | #define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
|
---|
| 856 | #define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
|
---|
| 857 | #define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
|
---|
| 858 | #define CAN1TDB2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
|
---|
| 859 | #define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
|
---|
| 860 | #define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
|
---|
| 861 | #define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
|
---|
| 862 | #define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
|
---|
| 863 |
|
---|
| 864 | #define CAN2_BASE_ADDR 0xE0048000
|
---|
| 865 | #define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
|
---|
| 866 | #define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
|
---|
| 867 | #define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
|
---|
| 868 | #define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
|
---|
| 869 | #define CAN2IER (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
|
---|
| 870 | #define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
|
---|
| 871 | #define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
|
---|
| 872 | #define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
|
---|
| 873 | #define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
|
---|
| 874 | #define CAN2RID (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
|
---|
| 875 | #define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
|
---|
| 876 | #define CAN2RDB (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
|
---|
| 877 |
|
---|
| 878 | #define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
|
---|
| 879 | #define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
|
---|
| 880 | #define CAN2TDA1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
|
---|
| 881 | #define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
|
---|
| 882 | #define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
|
---|
| 883 | #define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
|
---|
| 884 | #define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
|
---|
| 885 | #define CAN2TDB2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
|
---|
| 886 | #define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
|
---|
| 887 | #define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
|
---|
| 888 | #define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
|
---|
| 889 | #define CAN2TDB3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
|
---|
| 890 |
|
---|
| 891 |
|
---|
| 892 | /* MultiMedia Card Interface(MCI) Controller */
|
---|
| 893 | #define MCI_BASE_ADDR 0xE008C000
|
---|
| 894 | #define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
|
---|
| 895 | #define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
|
---|
| 896 | #define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
|
---|
| 897 | #define MCI_COMMAND (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x0C))
|
---|
| 898 | #define MCI_RESP_CMD (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x10))
|
---|
| 899 | #define MCI_RESP0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x14))
|
---|
| 900 | #define MCI_RESP1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x18))
|
---|
| 901 | #define MCI_RESP2 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x1C))
|
---|
| 902 | #define MCI_RESP3 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x20))
|
---|
| 903 | #define MCI_DATA_TMR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x24))
|
---|
| 904 | #define MCI_DATA_LEN (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x28))
|
---|
| 905 | #define MCI_DATA_CTRL (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x2C))
|
---|
| 906 | #define MCI_DATA_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x30))
|
---|
| 907 | #define MCI_STATUS (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x34))
|
---|
| 908 | #define MCI_CLEAR (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x38))
|
---|
| 909 | #define MCI_MASK0 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x3C))
|
---|
| 910 | #define MCI_MASK1 (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x40))
|
---|
| 911 | #define MCI_FIFO_CNT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x48))
|
---|
| 912 | #define MCI_FIFO (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x80))
|
---|
| 913 |
|
---|
| 914 |
|
---|
| 915 | /* I2S Interface Controller (I2S) */
|
---|
| 916 | #define I2S_BASE_ADDR 0xE0088000
|
---|
| 917 | #define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
|
---|
| 918 | #define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
|
---|
| 919 | #define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
|
---|
| 920 | #define I2S_RX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x0C))
|
---|
| 921 | #define I2S_STATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x10))
|
---|
| 922 | #define I2S_DMA1 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x14))
|
---|
| 923 | #define I2S_DMA2 (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x18))
|
---|
| 924 | #define I2S_IRQ (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x1C))
|
---|
| 925 | #define I2S_TXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x20))
|
---|
| 926 | #define I2S_RXRATE (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x24))
|
---|
| 927 |
|
---|
| 928 |
|
---|
| 929 | /* General-purpose DMA Controller */
|
---|
| 930 | #define DMA_BASE_ADDR 0xFFE04000
|
---|
| 931 | #define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
|
---|
| 932 | #define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
|
---|
| 933 | #define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
|
---|
| 934 | #define GPDMA_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x00C))
|
---|
| 935 | #define GPDMA_INT_ERR_CLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x010))
|
---|
| 936 | #define GPDMA_RAW_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x014))
|
---|
| 937 | #define GPDMA_RAW_INT_ERR_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x018))
|
---|
| 938 | #define GPDMA_ENABLED_CHNS (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x01C))
|
---|
| 939 | #define GPDMA_SOFT_BREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x020))
|
---|
| 940 | #define GPDMA_SOFT_SREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x024))
|
---|
| 941 | #define GPDMA_SOFT_LBREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x028))
|
---|
| 942 | #define GPDMA_SOFT_LSREQ (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x02C))
|
---|
| 943 | #define GPDMA_CONFIG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x030))
|
---|
| 944 | #define GPDMA_SYNC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x034))
|
---|
| 945 |
|
---|
| 946 | /* DMA channel 0 registers */
|
---|
| 947 | #define GPDMA_CH0_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x100))
|
---|
| 948 | #define GPDMA_CH0_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x104))
|
---|
| 949 | #define GPDMA_CH0_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x108))
|
---|
| 950 | #define GPDMA_CH0_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x10C))
|
---|
| 951 | #define GPDMA_CH0_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x110))
|
---|
| 952 |
|
---|
| 953 | /* DMA channel 1 registers */
|
---|
| 954 | #define GPDMA_CH1_SRC (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x120))
|
---|
| 955 | #define GPDMA_CH1_DEST (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x124))
|
---|
| 956 | #define GPDMA_CH1_LLI (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x128))
|
---|
| 957 | #define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
|
---|
| 958 | #define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
|
---|
| 959 |
|
---|
| 960 |
|
---|
| 961 | /* USB Controller */
|
---|
| 962 | #define USB_INT_BASE_ADDR 0xE01FC1C0
|
---|
| 963 | #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
|
---|
| 964 |
|
---|
| 965 | #define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
|
---|
| 966 |
|
---|
| 967 | /* USB Device Interrupt Registers */
|
---|
| 968 | #define DEV_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x00))
|
---|
| 969 | #define DEV_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x04))
|
---|
| 970 | #define DEV_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x08))
|
---|
| 971 | #define DEV_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x0C))
|
---|
| 972 | #define DEV_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x2C))
|
---|
| 973 |
|
---|
| 974 | /* USB Device Endpoint Interrupt Registers */
|
---|
| 975 | #define EP_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x30))
|
---|
| 976 | #define EP_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x34))
|
---|
| 977 | #define EP_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x38))
|
---|
| 978 | #define EP_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x3C))
|
---|
| 979 | #define EP_INT_PRIO (*(volatile uint32_t *) (USB_BASE_ADDR + 0x40))
|
---|
| 980 |
|
---|
| 981 | /* USB Device Endpoint Realization Registers */
|
---|
| 982 | #define REALIZE_EP (*(volatile uint32_t *) (USB_BASE_ADDR + 0x44))
|
---|
| 983 | #define EP_INDEX (*(volatile uint32_t *) (USB_BASE_ADDR + 0x48))
|
---|
| 984 | #define MAXPACKET_SIZE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x4C))
|
---|
| 985 |
|
---|
| 986 | /* USB Device Command Reagisters */
|
---|
| 987 | #define CMD_CODE (*(volatile uint32_t *) (USB_BASE_ADDR + 0x10))
|
---|
| 988 | #define CMD_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x14))
|
---|
| 989 |
|
---|
| 990 | /* USB Device Data Transfer Registers */
|
---|
| 991 | #define RX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x18))
|
---|
| 992 | #define TX_DATA (*(volatile uint32_t *) (USB_BASE_ADDR + 0x1C))
|
---|
| 993 | #define RX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x20))
|
---|
| 994 | #define TX_PLENGTH (*(volatile uint32_t *) (USB_BASE_ADDR + 0x24))
|
---|
| 995 | #define USB_CTRL (*(volatile uint32_t *) (USB_BASE_ADDR + 0x28))
|
---|
| 996 |
|
---|
| 997 | /* USB Device DMA Registers */
|
---|
| 998 | #define DMA_REQ_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x50))
|
---|
| 999 | #define DMA_REQ_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0x54))
|
---|
| 1000 | #define DMA_REQ_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0x58))
|
---|
| 1001 | #define UDCA_HEAD (*(volatile uint32_t *) (USB_BASE_ADDR + 0x80))
|
---|
| 1002 | #define EP_DMA_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x84))
|
---|
| 1003 | #define EP_DMA_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x88))
|
---|
| 1004 | #define EP_DMA_DIS (*(volatile uint32_t *) (USB_BASE_ADDR + 0x8C))
|
---|
| 1005 | #define DMA_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0x90))
|
---|
| 1006 | #define DMA_INT_EN (*(volatile uint32_t *) (USB_BASE_ADDR + 0x94))
|
---|
| 1007 | #define EOT_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA0))
|
---|
| 1008 | #define EOT_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA4))
|
---|
| 1009 | #define EOT_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xA8))
|
---|
| 1010 | #define NDD_REQ_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xAC))
|
---|
| 1011 | #define NDD_REQ_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB0))
|
---|
| 1012 | #define NDD_REQ_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB4))
|
---|
| 1013 | #define SYS_ERR_INT_STAT (*(volatile uint32_t *) (USB_BASE_ADDR + 0xB8))
|
---|
| 1014 | #define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
|
---|
| 1015 | #define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
|
---|
| 1016 |
|
---|
| 1017 |
|
---|
| 1018 | /* USB Host Controller */
|
---|
| 1019 | #define USBHC_BASE_ADDR 0xFFE0C000
|
---|
| 1020 | #define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
|
---|
| 1021 | #define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
|
---|
| 1022 | #define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
|
---|
| 1023 | #define HC_INT_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x0C))
|
---|
| 1024 | #define HC_INT_EN (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x10))
|
---|
| 1025 | #define HC_INT_DIS (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x14))
|
---|
| 1026 | #define HC_HCCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x18))
|
---|
| 1027 | #define HC_PERIOD_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x1C))
|
---|
| 1028 | #define HC_CTRL_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x20))
|
---|
| 1029 | #define HC_CTRL_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x24))
|
---|
| 1030 | #define HC_BULK_HEAD_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x28))
|
---|
| 1031 | #define HC_BULK_CUR_ED (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x2C))
|
---|
| 1032 | #define HC_DONE_HEAD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x30))
|
---|
| 1033 | #define HC_FM_INTERVAL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x34))
|
---|
| 1034 | #define HC_FM_REMAINING (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x38))
|
---|
| 1035 | #define HC_FM_NUMBER (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x3C))
|
---|
| 1036 | #define HC_PERIOD_START (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x40))
|
---|
| 1037 | #define HC_LS_THRHLD (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x44))
|
---|
| 1038 | #define HC_RH_DESCA (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x48))
|
---|
| 1039 | #define HC_RH_DESCB (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x4C))
|
---|
| 1040 | #define HC_RH_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x50))
|
---|
| 1041 | #define HC_RH_PORT_STAT1 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x54))
|
---|
| 1042 | #define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
|
---|
| 1043 |
|
---|
| 1044 | /* USB OTG Controller */
|
---|
| 1045 | #define USBOTG_BASE_ADDR 0xFFE0C100
|
---|
| 1046 | #define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
|
---|
| 1047 | #define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
|
---|
| 1048 | #define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
|
---|
| 1049 | #define OTG_INT_CLR (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x0C))
|
---|
| 1050 | #define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
|
---|
| 1051 | #define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
|
---|
| 1052 |
|
---|
| 1053 | #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
|
---|
| 1054 | #define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
|
---|
| 1055 | #define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
|
---|
| 1056 | #define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
|
---|
| 1057 | #define OTG_I2C_CTL (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x08))
|
---|
| 1058 | #define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
|
---|
| 1059 | #define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
|
---|
| 1060 |
|
---|
| 1061 | #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
|
---|
| 1062 | #define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
|
---|
| 1063 | #define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
|
---|
| 1064 |
|
---|
| 1065 |
|
---|
| 1066 | /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
|
---|
| 1067 | #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
|
---|
| 1068 | #define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
|
---|
| 1069 | #define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
|
---|
| 1070 | #define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
|
---|
| 1071 | #define MAC_IPGR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
|
---|
| 1072 | #define MAC_CLRT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
|
---|
| 1073 | #define MAC_MAXF (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
|
---|
| 1074 | #define MAC_SUPP (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
|
---|
| 1075 | #define MAC_TEST (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x01C)) /* TEST reg */
|
---|
| 1076 | #define MAC_MCFG (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
|
---|
| 1077 | #define MAC_MCMD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
|
---|
| 1078 | #define MAC_MADR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
|
---|
| 1079 | #define MAC_MWTD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
|
---|
| 1080 | #define MAC_MRDD (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
|
---|
| 1081 | #define MAC_MIND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
|
---|
| 1082 |
|
---|
| 1083 | #define MAC_SA0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
|
---|
| 1084 | #define MAC_SA1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
|
---|
| 1085 | #define MAC_SA2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
|
---|
| 1086 |
|
---|
| 1087 | #define MAC_COMMAND (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x100)) /* Command reg */
|
---|
| 1088 | #define MAC_STATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
|
---|
| 1089 | #define MAC_RXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
|
---|
| 1090 | #define MAC_RXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
|
---|
| 1091 | #define MAC_RXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
|
---|
| 1092 | #define MAC_RXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
|
---|
| 1093 | #define MAC_RXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
|
---|
| 1094 | #define MAC_TXDESCRIPTOR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
|
---|
| 1095 | #define MAC_TXSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
|
---|
| 1096 | #define MAC_TXDESCRIPTORNUM (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
|
---|
| 1097 | #define MAC_TXPRODUCEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
|
---|
| 1098 | #define MAC_TXCONSUMEINDEX (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
|
---|
| 1099 |
|
---|
| 1100 | #define MAC_TSV0 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
|
---|
| 1101 | #define MAC_TSV1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
|
---|
| 1102 | #define MAC_RSV (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
|
---|
| 1103 |
|
---|
| 1104 | #define MAC_FLOWCONTROLCNT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
|
---|
| 1105 | #define MAC_FLOWCONTROLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
|
---|
| 1106 |
|
---|
| 1107 | #define MAC_RXFILTERCTRL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
|
---|
| 1108 | #define MAC_RXFILTERWOLSTS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
|
---|
| 1109 | #define MAC_RXFILTERWOLCLR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
|
---|
| 1110 |
|
---|
| 1111 | #define MAC_HASHFILTERL (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
|
---|
| 1112 | #define MAC_HASHFILTERH (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
|
---|
| 1113 |
|
---|
| 1114 | #define MAC_INTSTATUS (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
|
---|
| 1115 | #define MAC_INTENABLE (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
|
---|
| 1116 | #define MAC_INTCLEAR (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
|
---|
| 1117 | #define MAC_INTSET (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
|
---|
| 1118 |
|
---|
| 1119 | #define MAC_POWERDOWN (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
|
---|
| 1120 | #define MAC_MODULEID (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
|
---|
| 1121 |
|
---|
| 1122 | /* Register Fields */
|
---|
| 1123 |
|
---|
| 1124 | /* CLKSRCSEL */
|
---|
| 1125 |
|
---|
| 1126 | #define CLKSRCSEL_CLKSRC_MASK 0x00000003U
|
---|
| 1127 |
|
---|
| 1128 | #define GET_CLKSRCSEL_CLKSRC( reg) \
|
---|
| 1129 | GET_REG_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0)
|
---|
| 1130 |
|
---|
| 1131 | #define SET_CLKSRCSEL_CLKSRC( reg, val) \
|
---|
| 1132 | SET_REG_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0)
|
---|
| 1133 |
|
---|
| 1134 | /* PLLCON */
|
---|
| 1135 |
|
---|
| 1136 | #define PLLCON_PLLE 0x00000001U
|
---|
| 1137 |
|
---|
| 1138 | #define PLLCON_PLLC 0x00000002U
|
---|
| 1139 |
|
---|
| 1140 | /* PLLCFG */
|
---|
| 1141 |
|
---|
| 1142 | #define PLLCFG_MSEL_MASK 0x00007fffU
|
---|
| 1143 |
|
---|
| 1144 | #define GET_PLLCFG_MSEL( reg) \
|
---|
| 1145 | GET_REG_FIELD( reg, PLLCFG_MSEL_MASK, 0)
|
---|
| 1146 |
|
---|
| 1147 | #define SET_PLLCFG_MSEL( reg, val) \
|
---|
| 1148 | SET_REG_FIELD( reg, val, PLLCFG_MSEL_MASK, 0)
|
---|
| 1149 |
|
---|
| 1150 | #define PLLCFG_NSEL_MASK 0x00ff0000U
|
---|
| 1151 |
|
---|
| 1152 | #define GET_PLLCFG_NSEL( reg) \
|
---|
| 1153 | GET_REG_FIELD( reg, PLLCFG_NSEL_MASK, 16)
|
---|
| 1154 |
|
---|
| 1155 | #define SET_PLLCFG_NSEL( reg, val) \
|
---|
| 1156 | SET_REG_FIELD( reg, val, PLLCFG_NSEL_MASK, 16)
|
---|
| 1157 |
|
---|
| 1158 | /* PLLSTAT */
|
---|
| 1159 |
|
---|
| 1160 | #define PLLSTAT_MSEL_MASK 0x00007fffU
|
---|
| 1161 |
|
---|
| 1162 | #define GET_PLLSTAT_MSEL( reg) \
|
---|
| 1163 | GET_REG_FIELD( reg, PLLSTAT_MSEL_MASK, 0)
|
---|
| 1164 |
|
---|
| 1165 | #define SET_PLLSTAT_MSEL( reg, val) \
|
---|
| 1166 | SET_REG_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0)
|
---|
| 1167 |
|
---|
| 1168 | #define PLLSTAT_NSEL_MASK 0x00ff0000U
|
---|
| 1169 |
|
---|
| 1170 | #define GET_PLLSTAT_NSEL( reg) \
|
---|
| 1171 | GET_REG_FIELD( reg, PLLSTAT_NSEL_MASK, 16)
|
---|
| 1172 |
|
---|
| 1173 | #define SET_PLLSTAT_NSEL( reg, val) \
|
---|
| 1174 | SET_REG_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16)
|
---|
| 1175 |
|
---|
| 1176 | #define PLLSTAT_PLLE 0x01000000U
|
---|
| 1177 |
|
---|
| 1178 | #define PLLSTAT_PLLC 0x02000000U
|
---|
| 1179 |
|
---|
| 1180 | #define PLLSTAT_PLOCK 0x04000000U
|
---|
| 1181 |
|
---|
| 1182 | /* CCLKCFG */
|
---|
| 1183 |
|
---|
| 1184 | #define CCLKCFG_CCLKSEL_MASK 0x000000ffU
|
---|
| 1185 |
|
---|
| 1186 | #define GET_CCLKCFG_CCLKSEL( reg) \
|
---|
| 1187 | GET_REG_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0)
|
---|
| 1188 |
|
---|
| 1189 | #define SET_CCLKCFG_CCLKSEL( reg, val) \
|
---|
| 1190 | SET_REG_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0)
|
---|
| 1191 |
|
---|
| 1192 | /* MEMMAP */
|
---|
| 1193 |
|
---|
| 1194 | #define MEMMAP_MAP_MASK 0x00000003U
|
---|
| 1195 |
|
---|
| 1196 | #define GET_MEMMAP_MAP( reg) \
|
---|
| 1197 | GET_REG_FIELD( reg, MEMMAP_MAP_MASK, 0)
|
---|
| 1198 |
|
---|
| 1199 | #define SET_MEMMAP_MAP( reg, val) \
|
---|
| 1200 | SET_REG_FIELD( reg, val, MEMMAP_MAP_MASK, 0)
|
---|
| 1201 |
|
---|
| 1202 | /* TIR */
|
---|
| 1203 |
|
---|
| 1204 | #define TIR_MR0 0x00000001U
|
---|
| 1205 |
|
---|
| 1206 | #define TIR_MR1 0x00000002U
|
---|
| 1207 |
|
---|
| 1208 | #define TIR_MR2 0x00000004U
|
---|
| 1209 |
|
---|
| 1210 | #define TIR_MR3 0x00000008U
|
---|
| 1211 |
|
---|
| 1212 | #define TIR_CR0 0x00000010U
|
---|
| 1213 |
|
---|
| 1214 | #define TIR_CR1 0x00000020U
|
---|
| 1215 |
|
---|
| 1216 | #define TIR_CR2 0x00000040U
|
---|
| 1217 |
|
---|
| 1218 | #define TIR_CR3 0x00000080U
|
---|
| 1219 |
|
---|
| 1220 | /* TCR */
|
---|
| 1221 |
|
---|
| 1222 | #define TCR_EN 0x00000001U
|
---|
| 1223 |
|
---|
| 1224 | #define TCR_RST 0x00000002U
|
---|
| 1225 |
|
---|
| 1226 | /* TMCR */
|
---|
| 1227 |
|
---|
| 1228 | #define TMCR_MR0I 0x00000001U
|
---|
| 1229 |
|
---|
| 1230 | #define TMCR_MR0R 0x00000002U
|
---|
| 1231 |
|
---|
| 1232 | #define TMCR_MR0S 0x00000004U
|
---|
| 1233 |
|
---|
| 1234 | #define TMCR_MR1I 0x00000008U
|
---|
| 1235 |
|
---|
| 1236 | #define TMCR_MR1R 0x00000010U
|
---|
| 1237 |
|
---|
| 1238 | #define TMCR_MR1S 0x00000020U
|
---|
| 1239 |
|
---|
| 1240 | #define TMCR_MR2I 0x00000040U
|
---|
| 1241 |
|
---|
| 1242 | #define TMCR_MR2R 0x00000080U
|
---|
| 1243 |
|
---|
| 1244 | #define TMCR_MR2S 0x00000100U
|
---|
| 1245 |
|
---|
| 1246 | #define TMCR_MR3I 0x00000200U
|
---|
| 1247 |
|
---|
| 1248 | #define TMCR_MR3R 0x00000400U
|
---|
| 1249 |
|
---|
| 1250 | #define TMCR_MR3S 0x00000800U
|
---|
| 1251 |
|
---|
| 1252 | /* PCLKSEL0 */
|
---|
| 1253 |
|
---|
| 1254 | #define PCLKSEL0_PCLK_WDT_MASK 0x00000003U
|
---|
| 1255 |
|
---|
| 1256 | #define GET_PCLKSEL0_PCLK_WDT( reg) \
|
---|
| 1257 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0)
|
---|
| 1258 |
|
---|
| 1259 | #define SET_PCLKSEL0_PCLK_WDT( reg, val) \
|
---|
| 1260 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0)
|
---|
| 1261 |
|
---|
| 1262 | #define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU
|
---|
| 1263 |
|
---|
| 1264 | #define GET_PCLKSEL0_PCLK_TIMER0( reg) \
|
---|
| 1265 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2)
|
---|
| 1266 |
|
---|
| 1267 | #define SET_PCLKSEL0_PCLK_TIMER0( reg, val) \
|
---|
| 1268 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2)
|
---|
| 1269 |
|
---|
| 1270 | #define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U
|
---|
| 1271 |
|
---|
| 1272 | #define GET_PCLKSEL0_PCLK_TIMER1( reg) \
|
---|
| 1273 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4)
|
---|
| 1274 |
|
---|
| 1275 | #define SET_PCLKSEL0_PCLK_TIMER1( reg, val) \
|
---|
| 1276 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4)
|
---|
| 1277 |
|
---|
| 1278 | #define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U
|
---|
| 1279 |
|
---|
| 1280 | #define GET_PCLKSEL0_PCLK_UART0( reg) \
|
---|
| 1281 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6)
|
---|
| 1282 |
|
---|
| 1283 | #define SET_PCLKSEL0_PCLK_UART0( reg, val) \
|
---|
| 1284 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6)
|
---|
| 1285 |
|
---|
| 1286 | #define PCLKSEL0_PCLK_UART1_MASK 0x00000300U
|
---|
| 1287 |
|
---|
| 1288 | #define GET_PCLKSEL0_PCLK_UART1( reg) \
|
---|
| 1289 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8)
|
---|
| 1290 |
|
---|
| 1291 | #define SET_PCLKSEL0_PCLK_UART1( reg, val) \
|
---|
| 1292 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8)
|
---|
| 1293 |
|
---|
| 1294 | #define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U
|
---|
| 1295 |
|
---|
| 1296 | #define GET_PCLKSEL0_PCLK_PWM0( reg) \
|
---|
| 1297 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10)
|
---|
| 1298 |
|
---|
| 1299 | #define SET_PCLKSEL0_PCLK_PWM0( reg, val) \
|
---|
| 1300 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10)
|
---|
| 1301 |
|
---|
| 1302 | #define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U
|
---|
| 1303 |
|
---|
| 1304 | #define GET_PCLKSEL0_PCLK_PWM1( reg) \
|
---|
| 1305 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
---|
| 1306 |
|
---|
| 1307 | #define SET_PCLKSEL0_PCLK_PWM1( reg, val) \
|
---|
| 1308 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12)
|
---|
| 1309 |
|
---|
| 1310 | #define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U
|
---|
| 1311 |
|
---|
| 1312 | #define GET_PCLKSEL0_PCLK_I2C0( reg) \
|
---|
| 1313 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
---|
| 1314 |
|
---|
| 1315 | #define SET_PCLKSEL0_PCLK_I2C0( reg, val) \
|
---|
| 1316 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14)
|
---|
| 1317 |
|
---|
| 1318 | #define PCLKSEL0_PCLK_SPI_MASK 0x00030000U
|
---|
| 1319 |
|
---|
| 1320 | #define GET_PCLKSEL0_PCLK_SPI( reg) \
|
---|
| 1321 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16)
|
---|
| 1322 |
|
---|
| 1323 | #define SET_PCLKSEL0_PCLK_SPI( reg, val) \
|
---|
| 1324 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16)
|
---|
| 1325 |
|
---|
| 1326 | #define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U
|
---|
| 1327 |
|
---|
| 1328 | #define GET_PCLKSEL0_PCLK_RTC( reg) \
|
---|
| 1329 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18)
|
---|
| 1330 |
|
---|
| 1331 | #define SET_PCLKSEL0_PCLK_RTC( reg, val) \
|
---|
| 1332 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18)
|
---|
| 1333 |
|
---|
| 1334 | #define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U
|
---|
| 1335 |
|
---|
| 1336 | #define GET_PCLKSEL0_PCLK_SSP1( reg) \
|
---|
| 1337 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
---|
| 1338 |
|
---|
| 1339 | #define SET_PCLKSEL0_PCLK_SSP1( reg, val) \
|
---|
| 1340 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20)
|
---|
| 1341 |
|
---|
| 1342 | #define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U
|
---|
| 1343 |
|
---|
| 1344 | #define GET_PCLKSEL0_PCLK_DAC( reg) \
|
---|
| 1345 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22)
|
---|
| 1346 |
|
---|
| 1347 | #define SET_PCLKSEL0_PCLK_DAC( reg, val) \
|
---|
| 1348 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22)
|
---|
| 1349 |
|
---|
| 1350 | #define PCLKSEL0_PCLK_ADC_MASK 0x03000000U
|
---|
| 1351 |
|
---|
| 1352 | #define GET_PCLKSEL0_PCLK_ADC( reg) \
|
---|
| 1353 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24)
|
---|
| 1354 |
|
---|
| 1355 | #define SET_PCLKSEL0_PCLK_ADC( reg, val) \
|
---|
| 1356 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24)
|
---|
| 1357 |
|
---|
| 1358 | #define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U
|
---|
| 1359 |
|
---|
| 1360 | #define GET_PCLKSEL0_PCLK_CAN1( reg) \
|
---|
| 1361 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
---|
| 1362 |
|
---|
| 1363 | #define SET_PCLKSEL0_PCLK_CAN1( reg, val) \
|
---|
| 1364 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26)
|
---|
| 1365 |
|
---|
| 1366 | #define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U
|
---|
| 1367 |
|
---|
| 1368 | #define GET_PCLKSEL0_PCLK_CAN2( reg) \
|
---|
| 1369 | GET_REG_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
---|
| 1370 |
|
---|
| 1371 | #define SET_PCLKSEL0_PCLK_CAN2( reg, val) \
|
---|
| 1372 | SET_REG_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28)
|
---|
| 1373 |
|
---|
| 1374 | /* PCLKSEL1 */
|
---|
| 1375 |
|
---|
| 1376 | #define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U
|
---|
| 1377 |
|
---|
| 1378 | #define GET_PCLKSEL1_PCLK_BAT_RAM( reg) \
|
---|
| 1379 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
---|
| 1380 |
|
---|
| 1381 | #define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val) \
|
---|
| 1382 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0)
|
---|
| 1383 |
|
---|
| 1384 | #define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU
|
---|
| 1385 |
|
---|
| 1386 | #define GET_PCLKSEL1_PCLK_GPIO( reg) \
|
---|
| 1387 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
---|
| 1388 |
|
---|
| 1389 | #define SET_PCLKSEL1_PCLK_GPIO( reg, val) \
|
---|
| 1390 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2)
|
---|
| 1391 |
|
---|
| 1392 | #define PCLKSEL1_PCLK_PCB_MASK 0x00000030U
|
---|
| 1393 |
|
---|
| 1394 | #define GET_PCLKSEL1_PCLK_PCB( reg) \
|
---|
| 1395 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4)
|
---|
| 1396 |
|
---|
| 1397 | #define SET_PCLKSEL1_PCLK_PCB( reg, val) \
|
---|
| 1398 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4)
|
---|
| 1399 |
|
---|
| 1400 | #define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U
|
---|
| 1401 |
|
---|
| 1402 | #define GET_PCLKSEL1_PCLK_I2C1( reg) \
|
---|
| 1403 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
---|
| 1404 |
|
---|
| 1405 | #define SET_PCLKSEL1_PCLK_I2C1( reg, val) \
|
---|
| 1406 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6)
|
---|
| 1407 |
|
---|
| 1408 | #define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U
|
---|
| 1409 |
|
---|
| 1410 | #define GET_PCLKSEL1_PCLK_SSP0( reg) \
|
---|
| 1411 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
---|
| 1412 |
|
---|
| 1413 | #define SET_PCLKSEL1_PCLK_SSP0( reg, val) \
|
---|
| 1414 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10)
|
---|
| 1415 |
|
---|
| 1416 | #define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U
|
---|
| 1417 |
|
---|
| 1418 | #define GET_PCLKSEL1_PCLK_TIMER2( reg) \
|
---|
| 1419 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
---|
| 1420 |
|
---|
| 1421 | #define SET_PCLKSEL1_PCLK_TIMER2( reg, val) \
|
---|
| 1422 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12)
|
---|
| 1423 |
|
---|
| 1424 | #define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U
|
---|
| 1425 |
|
---|
| 1426 | #define GET_PCLKSEL1_PCLK_TIMER3( reg) \
|
---|
| 1427 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
---|
| 1428 |
|
---|
| 1429 | #define SET_PCLKSEL1_PCLK_TIMER3( reg, val) \
|
---|
| 1430 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14)
|
---|
| 1431 |
|
---|
| 1432 | #define PCLKSEL1_PCLK_UART2_MASK 0x00030000U
|
---|
| 1433 |
|
---|
| 1434 | #define GET_PCLKSEL1_PCLK_UART2( reg) \
|
---|
| 1435 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16)
|
---|
| 1436 |
|
---|
| 1437 | #define SET_PCLKSEL1_PCLK_UART2( reg, val) \
|
---|
| 1438 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16)
|
---|
| 1439 |
|
---|
| 1440 | #define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U
|
---|
| 1441 |
|
---|
| 1442 | #define GET_PCLKSEL1_PCLK_UART3( reg) \
|
---|
| 1443 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18)
|
---|
| 1444 |
|
---|
| 1445 | #define SET_PCLKSEL1_PCLK_UART3( reg, val) \
|
---|
| 1446 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18)
|
---|
| 1447 |
|
---|
| 1448 | #define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U
|
---|
| 1449 |
|
---|
| 1450 | #define GET_PCLKSEL1_PCLK_I2C2( reg) \
|
---|
| 1451 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
---|
| 1452 |
|
---|
| 1453 | #define SET_PCLKSEL1_PCLK_I2C2( reg, val) \
|
---|
| 1454 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20)
|
---|
| 1455 |
|
---|
| 1456 | #define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U
|
---|
| 1457 |
|
---|
| 1458 | #define GET_PCLKSEL1_PCLK_I2S( reg) \
|
---|
| 1459 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22)
|
---|
| 1460 |
|
---|
| 1461 | #define SET_PCLKSEL1_PCLK_I2S( reg, val) \
|
---|
| 1462 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22)
|
---|
| 1463 |
|
---|
| 1464 | #define PCLKSEL1_PCLK_MCI_MASK 0x03000000U
|
---|
| 1465 |
|
---|
| 1466 | #define GET_PCLKSEL1_PCLK_MCI( reg) \
|
---|
| 1467 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24)
|
---|
| 1468 |
|
---|
| 1469 | #define SET_PCLKSEL1_PCLK_MCI( reg, val) \
|
---|
| 1470 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24)
|
---|
| 1471 |
|
---|
| 1472 | #define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U
|
---|
| 1473 |
|
---|
| 1474 | #define GET_PCLKSEL1_PCLK_SYSCON( reg) \
|
---|
| 1475 | GET_REG_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
---|
| 1476 |
|
---|
| 1477 | #define SET_PCLKSEL1_PCLK_SYSCON( reg, val) \
|
---|
| 1478 | SET_REG_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28)
|
---|
| 1479 |
|
---|
| 1480 | /* RTC_ILR */
|
---|
| 1481 |
|
---|
| 1482 | #define RTC_ILR_RTCCIF 0x00000001U
|
---|
| 1483 |
|
---|
| 1484 | #define RTC_ILR_RTCALF 0x00000002U
|
---|
| 1485 |
|
---|
| 1486 | #define RTC_ILR_RTSSF 0x00000004U
|
---|
| 1487 |
|
---|
| 1488 | /* RTC_CCR */
|
---|
| 1489 |
|
---|
| 1490 | #define RTC_CCR_CLKEN 0x00000001U
|
---|
| 1491 |
|
---|
| 1492 | #define RTC_CCR_CTCRST 0x00000002U
|
---|
| 1493 |
|
---|
| 1494 | #define RTC_CCR_CLKSRC 0x00000010U
|
---|
| 1495 |
|
---|
| 1496 | #endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
|
---|