1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx_regs |
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5 | * |
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6 | * @brief Register definitions. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | * |
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22 | * $Id$ |
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23 | */ |
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24 | |
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25 | #ifndef LPC17XX_REGS_H |
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26 | #define LPC17XX_REGS_H |
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27 | |
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28 | #include <bsp/utility.h> |
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29 | |
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30 | #define LPC17XX_BASE 0x00 |
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31 | |
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32 | typedef struct { |
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33 | #define LPC17XX_PLL_CON_PLLE BSP_BIT32(0) |
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34 | #define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4) |
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35 | #define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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36 | #define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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37 | #define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6) |
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38 | #define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6) |
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39 | #define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) |
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40 | #define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8) |
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41 | #define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10) |
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42 | uint32_t con; |
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43 | uint32_t cfg; |
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44 | uint32_t stat; |
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45 | uint32_t feed; |
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46 | } lpc17xx_pll; |
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47 | |
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48 | typedef struct { |
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49 | uint32_t flashcfg; |
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50 | #define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15) |
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51 | #define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15) |
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52 | #define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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53 | uint32_t reserved_04 [15]; |
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54 | uint32_t memmap; |
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55 | #define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0) |
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56 | uint32_t reserved_44 [15]; |
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57 | lpc17xx_pll pll_0; |
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58 | uint32_t reserved_90 [4]; |
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59 | lpc17xx_pll pll_1; |
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60 | uint32_t reserved_b0 [4]; |
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61 | uint32_t pcon; |
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62 | #define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0) |
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63 | #define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1) |
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64 | #define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2) |
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65 | #define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3) |
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66 | #define LPC17XX_SCB_PCON_BORD BSP_BIT32(4) |
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67 | #define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8) |
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68 | #define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9) |
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69 | #define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10) |
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70 | #define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11) |
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71 | uint32_t pconp; |
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72 | #define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0) |
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73 | #define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1) |
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74 | #define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2) |
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75 | #define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3) |
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76 | #define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4) |
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77 | #define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5) |
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78 | #define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6) |
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79 | #define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7) |
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80 | #define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8) |
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81 | #define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9) |
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82 | #define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10) |
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83 | #define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11) |
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84 | #define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12) |
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85 | #define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13) |
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86 | #define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14) |
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87 | #define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15) |
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88 | #define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17) |
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89 | #define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18) |
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90 | #define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19) |
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91 | #define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20) |
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92 | #define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21) |
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93 | #define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22) |
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94 | #define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23) |
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95 | #define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24) |
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96 | #define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25) |
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97 | #define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26) |
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98 | #define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27) |
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99 | #define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28) |
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100 | #define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29) |
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101 | #define LPC17XX_SCB_PCONP_USB BSP_BIT32(30) |
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102 | #define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31) |
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103 | uint32_t reserved_c8 [14]; |
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104 | uint32_t emcclksel; |
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105 | #define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0) |
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106 | uint32_t cclksel; |
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107 | #define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4) |
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108 | #define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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109 | #define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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110 | #define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8) |
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111 | uint32_t usbclksel; |
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112 | #define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4) |
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113 | #define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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114 | #define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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115 | #define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9) |
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116 | #define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9) |
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117 | #define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) |
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118 | uint32_t clksrcsel; |
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119 | #define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0) |
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120 | uint32_t reserved_110 [12]; |
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121 | uint32_t extint; |
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122 | uint32_t reserved_144; |
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123 | uint32_t extmode; |
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124 | uint32_t extpolar; |
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125 | uint32_t reserved_150 [12]; |
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126 | uint32_t rsid; |
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127 | uint32_t reserved_184 [7]; |
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128 | uint32_t scs; |
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129 | #define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0) |
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130 | #define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1) |
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131 | #define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2) |
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132 | #define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3) |
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133 | #define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4) |
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134 | #define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5) |
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135 | #define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6) |
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136 | uint32_t reserved_1a4; |
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137 | uint32_t pclksel; |
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138 | #define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4) |
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139 | #define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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140 | #define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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141 | uint32_t reserved_1ac; |
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142 | uint32_t pboost; |
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143 | #define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0) |
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144 | uint32_t reserved_1b4 [5]; |
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145 | uint32_t clkoutcfg; |
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146 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0) |
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147 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0) |
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148 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0) |
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149 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4) |
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150 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4) |
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151 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4) |
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152 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8) |
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153 | #define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9) |
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154 | uint32_t rstcon0; |
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155 | uint32_t rstcon1; |
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156 | uint32_t reserved_1d4 [2]; |
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157 | uint32_t emcdlyctl; |
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158 | #define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4) |
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159 | #define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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160 | #define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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161 | #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12) |
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162 | #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12) |
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163 | #define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12) |
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164 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20) |
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165 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20) |
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166 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) |
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167 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28) |
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168 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28) |
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169 | #define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28) |
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170 | uint32_t emccal; |
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171 | #define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7) |
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172 | #define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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173 | #define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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174 | #define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14) |
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175 | #define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15) |
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176 | } lpc17xx_scb; |
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177 | |
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178 | #define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000)) |
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179 | |
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180 | typedef struct { |
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181 | uint32_t reserved_00 [268693504]; |
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182 | lpc17xx_scb scb; |
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183 | } lpc17xx; |
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184 | |
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185 | #define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE)) |
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186 | |
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187 | #endif /* LPC17XX_REGS_H */ |
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