source: rtems/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h @ 4a6cc2a

4.115
Last change on this file since 4a6cc2a was 4a6cc2a, checked in by Sebastian Huber <sebastian.huber@…>, on 11/08/11 at 10:39:46

2011-11-08 Sebastian Huber <sebastian.huber@…>

  • include/lpc17xx.h: New file.
  • Makefile.am, preinstall.am: Reflect change above. Update due to API changes.
  • configure.ac, console/console-config.c, include/bsp.h, include/io.h, include/irq.h, include/lcd.h, include/lpc-clock-config.h, include/lpc24xx.h, include/start-config.h, irq/irq-dispatch.c, irq/irq.c, misc/bspidle.c, misc/io.c, misc/lcd.c, misc/restart.c, misc/system-clocks.c, ssp/ssp.c, startup/bspreset.c, startup/bspstart.c, startup/bspstarthooks.c, startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c, startup/start-config-pinsel.c: Basic support for LPC17XX. New memory configurations for W9825G2JB75I, IS42S32800B, and SST39VF3201.
  • Property mode set to 100644
File size: 7.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc24xx_regs
5 *
6 * @brief Register definitions.
7 */
8
9/*
10 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 *
22 * $Id$
23 */
24
25#ifndef LPC17XX_REGS_H
26#define LPC17XX_REGS_H
27
28#include <bsp/utility.h>
29
30#define LPC17XX_BASE 0x00
31
32typedef struct {
33#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
34#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
35#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4)
36#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
37#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6)
38#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6)
39#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
40#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8)
41#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10)
42        uint32_t con;
43        uint32_t cfg;
44        uint32_t stat;
45        uint32_t feed;
46} lpc17xx_pll;
47
48typedef struct {
49        uint32_t flashcfg;
50#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15)
51#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15)
52#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
53        uint32_t reserved_04 [15];
54        uint32_t memmap;
55#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0)
56        uint32_t reserved_44 [15];
57        lpc17xx_pll pll_0;
58        uint32_t reserved_90 [4];
59        lpc17xx_pll pll_1;
60        uint32_t reserved_b0 [4];
61        uint32_t pcon;
62#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0)
63#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1)
64#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2)
65#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3)
66#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4)
67#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8)
68#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9)
69#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10)
70#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11)
71        uint32_t pconp;
72#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0)
73#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1)
74#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2)
75#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3)
76#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4)
77#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5)
78#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6)
79#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7)
80#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8)
81#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9)
82#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10)
83#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11)
84#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12)
85#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13)
86#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14)
87#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15)
88#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17)
89#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18)
90#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19)
91#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20)
92#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21)
93#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22)
94#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23)
95#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24)
96#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25)
97#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26)
98#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27)
99#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28)
100#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29)
101#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30)
102#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31)
103        uint32_t reserved_c8 [14];
104        uint32_t emcclksel;
105#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0)
106        uint32_t cclksel;
107#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4)
108#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
109#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
110#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8)
111        uint32_t usbclksel;
112#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4)
113#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
114#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
115#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9)
116#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9)
117#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
118        uint32_t clksrcsel;
119#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0)
120        uint32_t reserved_110 [12];
121        uint32_t extint;
122        uint32_t reserved_144;
123        uint32_t extmode;
124        uint32_t extpolar;
125        uint32_t reserved_150 [12];
126        uint32_t rsid;
127        uint32_t reserved_184 [7];
128        uint32_t scs;
129#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0)
130#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1)
131#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2)
132#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3)
133#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4)
134#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5)
135#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6)
136        uint32_t reserved_1a4;
137        uint32_t pclksel;
138#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4)
139#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
140#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
141        uint32_t reserved_1ac;
142        uint32_t pboost;
143#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0)
144        uint32_t reserved_1b4 [5];
145        uint32_t clkoutcfg;
146#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0)
147#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0)
148#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0)
149#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4)
150#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4)
151#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4)
152#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8)
153#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9)
154        uint32_t rstcon0;
155        uint32_t rstcon1;
156        uint32_t reserved_1d4 [2];
157        uint32_t emcdlyctl;
158#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4)
159#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4)
160#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
161#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12)
162#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12)
163#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
164#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20)
165#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20)
166#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
167#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28)
168#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28)
169#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28)
170        uint32_t emccal;
171#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7)
172#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7)
173#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
174#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14)
175#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15)
176} lpc17xx_scb;
177
178#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
179
180typedef struct {
181        uint32_t reserved_00 [268693504];
182        lpc17xx_scb scb;
183} lpc17xx;
184
185#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE))
186
187#endif /* LPC17XX_REGS_H */
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