1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc24xx_libi2c |
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5 | * |
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6 | * @brief LibI2C bus driver for the I2C modules. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #include <rtems.h> |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <bsp/i2c.h> |
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26 | #include <bsp/io.h> |
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27 | #include <bsp/irq.h> |
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28 | #include <bsp/irq-generic.h> |
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29 | #include <bsp/lpc24xx.h> |
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30 | #include <bsp/system-clocks.h> |
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31 | |
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32 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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33 | |
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34 | #include <rtems/status-checks.h> |
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35 | |
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36 | typedef struct { |
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37 | rtems_libi2c_bus_t bus; |
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38 | volatile lpc24xx_i2c *regs; |
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39 | unsigned index; |
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40 | unsigned config; |
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41 | rtems_vector_number vector; |
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42 | rtems_id state_update; |
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43 | uint8_t * volatile data; |
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44 | uint8_t * volatile end; |
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45 | } lpc24xx_i2c_bus_entry; |
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46 | |
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47 | static void lpc24xx_i2c_handler(void *arg) |
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48 | { |
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49 | lpc24xx_i2c_bus_entry *e = arg; |
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50 | volatile lpc24xx_i2c *regs = e->regs; |
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51 | unsigned state = regs->stat; |
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52 | uint8_t *data = e->data; |
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53 | uint8_t *end = e->end; |
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54 | bool notify = true; |
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55 | |
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56 | switch (state) { |
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57 | case 0x28U: |
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58 | /* Data has been transmitted successfully */ |
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59 | if (data != end) { |
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60 | regs->dat = *data; |
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61 | ++data; |
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62 | regs->conset = LPC24XX_I2C_AA; |
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63 | regs->conclr = LPC24XX_I2C_SI; |
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64 | notify = false; |
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65 | e->data = data; |
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66 | } |
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67 | break; |
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68 | case 0x50U: |
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69 | /* Data has been received */ |
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70 | if (data != end) { |
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71 | *data = (uint8_t) regs->dat; |
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72 | ++data; |
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73 | if (data != end) { |
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74 | if (data + 1 != end) { |
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75 | regs->conset = LPC24XX_I2C_AA; |
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76 | } else { |
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77 | regs->conclr = LPC24XX_I2C_AA; |
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78 | } |
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79 | regs->conclr = LPC24XX_I2C_SI; |
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80 | notify = false; |
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81 | e->data = data; |
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82 | } else { |
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83 | /* This is an error and should never happen */ |
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84 | } |
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85 | } |
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86 | break; |
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87 | case 0x58U: |
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88 | /* Last data has been received */ |
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89 | if (data != end) { |
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90 | *data = (uint8_t) regs->dat; |
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91 | } |
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92 | break; |
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93 | default: |
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94 | /* Do nothing */ |
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95 | break; |
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96 | } |
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97 | |
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98 | /* Notify task if necessary */ |
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99 | if (notify) { |
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100 | bsp_interrupt_vector_disable(e->vector); |
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101 | |
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102 | rtems_semaphore_release(e->state_update); |
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103 | } |
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104 | } |
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105 | |
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106 | static rtems_status_code lpc24xx_i2c_wait(lpc24xx_i2c_bus_entry *e) |
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107 | { |
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108 | bsp_interrupt_vector_enable(e->vector); |
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109 | |
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110 | return rtems_semaphore_obtain(e->state_update, RTEMS_WAIT, RTEMS_NO_TIMEOUT); |
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111 | } |
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112 | |
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113 | static rtems_status_code lpc24xx_i2c_init(rtems_libi2c_bus_t *bus) |
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114 | { |
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115 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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116 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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117 | volatile lpc24xx_i2c *regs = e->regs; |
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118 | unsigned cycles = LPC24XX_CCLK / (8U * 100000U * 2U); |
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119 | |
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120 | /* Create semaphore */ |
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121 | sc = rtems_semaphore_create ( |
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122 | rtems_build_name ('I', '2', 'C', '0' + e->index), |
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123 | 0, |
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124 | RTEMS_SIMPLE_BINARY_SEMAPHORE, |
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125 | 0, |
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126 | &e->state_update |
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127 | ); |
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128 | RTEMS_CHECK_SC(sc, "create status update semaphore"); |
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129 | |
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130 | /* Enable module power */ |
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131 | sc = lpc24xx_module_enable(LPC24XX_MODULE_I2C_0 + e->index, LPC24XX_MODULE_CCLK_8); |
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132 | RTEMS_CHECK_SC(sc, "enable module"); |
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133 | |
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134 | /* IO configuration */ |
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135 | sc = lpc24xx_io_config(LPC24XX_MODULE_I2C_0 + e->index, e->config); |
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136 | RTEMS_CHECK_SC(sc, "IO configuration"); |
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137 | |
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138 | /* Clock high and low duty cycles */ |
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139 | regs->sclh = cycles; |
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140 | regs->scll = cycles; |
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141 | |
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142 | /* Disable module */ |
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143 | regs->conclr = LPC24XX_I2C_EN; |
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144 | |
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145 | /* Install interrupt handler and disable this vector */ |
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146 | sc = rtems_interrupt_handler_install( |
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147 | e->vector, |
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148 | "I2C", |
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149 | RTEMS_INTERRUPT_UNIQUE, |
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150 | lpc24xx_i2c_handler, |
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151 | e |
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152 | ); |
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153 | RTEMS_CHECK_SC(sc, "install interrupt handler"); |
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154 | bsp_interrupt_vector_disable(e->vector); |
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155 | |
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156 | /* Enable module in master mode */ |
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157 | regs->conset = LPC24XX_I2C_EN; |
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158 | |
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159 | /* Set self address */ |
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160 | regs->adr = 0; |
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161 | |
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162 | return RTEMS_SUCCESSFUL; |
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163 | } |
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164 | |
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165 | static rtems_status_code lpc24xx_i2c_send_start(rtems_libi2c_bus_t *bus) |
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166 | { |
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167 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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168 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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169 | volatile lpc24xx_i2c *regs = e->regs; |
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170 | |
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171 | /* Start */ |
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172 | regs->conclr = LPC24XX_I2C_STA | LPC24XX_I2C_AA | LPC24XX_I2C_SI; |
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173 | regs->conset = LPC24XX_I2C_STA; |
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174 | |
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175 | /* Wait */ |
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176 | sc = lpc24xx_i2c_wait(e); |
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177 | RTEMS_CHECK_SC(sc, "wait for state update"); |
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178 | |
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179 | return RTEMS_SUCCESSFUL; |
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180 | } |
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181 | |
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182 | static rtems_status_code lpc24xx_i2c_send_stop(rtems_libi2c_bus_t *bus) |
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183 | { |
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184 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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185 | volatile lpc24xx_i2c *regs = e->regs; |
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186 | |
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187 | /* Stop */ |
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188 | regs->conset = LPC24XX_I2C_STO | LPC24XX_I2C_AA; |
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189 | regs->conclr = LPC24XX_I2C_STA | LPC24XX_I2C_SI; |
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190 | |
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191 | return RTEMS_SUCCESSFUL; |
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192 | } |
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193 | |
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194 | static rtems_status_code lpc24xx_i2c_send_addr( |
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195 | rtems_libi2c_bus_t *bus, |
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196 | uint32_t addr, |
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197 | int rw |
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198 | ) |
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199 | { |
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200 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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201 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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202 | volatile lpc24xx_i2c *regs = e->regs; |
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203 | unsigned state = regs->stat; |
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204 | |
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205 | /* Check state */ |
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206 | if (state != 0x8U && state != 0x10U) { |
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207 | return -RTEMS_IO_ERROR; |
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208 | } |
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209 | |
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210 | /* Send address */ |
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211 | regs->dat = (uint8_t) ((addr << 1U) | ((rw != 0) ? 1U : 0U)); |
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212 | regs->conset = LPC24XX_I2C_AA; |
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213 | regs->conclr = LPC24XX_I2C_STA | LPC24XX_I2C_SI; |
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214 | |
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215 | /* Wait */ |
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216 | sc = lpc24xx_i2c_wait(e); |
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217 | RTEMS_CHECK_SC_RV(sc, "wait for state update"); |
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218 | |
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219 | /* Check state */ |
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220 | state = regs->stat; |
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221 | if (state != 0x18U && state != 0x40U) { |
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222 | return -RTEMS_IO_ERROR; |
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223 | } |
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224 | |
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225 | return RTEMS_SUCCESSFUL; |
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226 | } |
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227 | |
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228 | static int lpc24xx_i2c_read(rtems_libi2c_bus_t *bus, unsigned char *in, int n) |
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229 | { |
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230 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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231 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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232 | volatile lpc24xx_i2c *regs = e->regs; |
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233 | unsigned state = regs->stat; |
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234 | uint8_t *data = in; |
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235 | uint8_t *end = in + n; |
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236 | |
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237 | if (n <= 0) { |
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238 | return n; |
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239 | } else if (state != 0x40U) { |
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240 | return -RTEMS_IO_ERROR; |
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241 | } |
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242 | |
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243 | /* Setup receive buffer */ |
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244 | e->data = data; |
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245 | e->end = end; |
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246 | |
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247 | /* Ready to receive data */ |
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248 | if (data + 1 != end) { |
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249 | regs->conset = LPC24XX_I2C_AA; |
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250 | } else { |
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251 | regs->conclr = LPC24XX_I2C_AA; |
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252 | } |
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253 | regs->conclr = LPC24XX_I2C_SI; |
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254 | |
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255 | /* Wait */ |
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256 | sc = lpc24xx_i2c_wait(e); |
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257 | RTEMS_CHECK_SC_RV(sc, "wait for state update"); |
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258 | |
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259 | /* Check state */ |
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260 | state = regs->stat; |
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261 | if (state != 0x58U) { |
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262 | return -RTEMS_IO_ERROR; |
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263 | } |
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264 | |
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265 | return n; |
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266 | } |
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267 | |
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268 | static int lpc24xx_i2c_write( |
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269 | rtems_libi2c_bus_t *bus, |
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270 | unsigned char *out, |
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271 | int n |
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272 | ) |
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273 | { |
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274 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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275 | lpc24xx_i2c_bus_entry *e = (lpc24xx_i2c_bus_entry *) bus; |
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276 | volatile lpc24xx_i2c *regs = e->regs; |
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277 | unsigned state = 0; |
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278 | |
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279 | if (n <= 0) { |
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280 | return n; |
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281 | } |
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282 | |
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283 | /* Setup transmit buffer */ |
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284 | e->data = out + 1; |
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285 | e->end = out + n; |
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286 | |
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287 | /* Transmit first byte */ |
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288 | regs->dat = *out; |
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289 | regs->conset = LPC24XX_I2C_AA; |
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290 | regs->conclr = LPC24XX_I2C_SI; |
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291 | |
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292 | /* Wait */ |
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293 | sc = lpc24xx_i2c_wait(e); |
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294 | RTEMS_CHECK_SC_RV(sc, "wait for state update"); |
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295 | |
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296 | /* Check state */ |
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297 | state = regs->stat; |
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298 | if (state != 0x28U) { |
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299 | return -RTEMS_IO_ERROR; |
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300 | } |
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301 | |
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302 | return n; |
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303 | } |
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304 | |
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305 | static int lpc24xx_i2c_set_transfer_mode( |
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306 | rtems_libi2c_bus_t *bus, |
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307 | const rtems_libi2c_tfr_mode_t *mode |
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308 | ) |
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309 | { |
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310 | return -RTEMS_NOT_IMPLEMENTED; |
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311 | } |
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312 | |
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313 | static int lpc24xx_i2c_ioctl(rtems_libi2c_bus_t *bus, int cmd, void *arg) |
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314 | { |
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315 | int rv = -1; |
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316 | const rtems_libi2c_tfr_mode_t *tm = (const rtems_libi2c_tfr_mode_t *) arg; |
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317 | |
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318 | switch (cmd) { |
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319 | case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: |
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320 | rv = lpc24xx_i2c_set_transfer_mode(bus, tm); |
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321 | break; |
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322 | default: |
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323 | rv = -RTEMS_NOT_DEFINED; |
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324 | break; |
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325 | } |
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326 | |
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327 | return rv; |
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328 | } |
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329 | |
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330 | static const rtems_libi2c_bus_ops_t lpc24xx_i2c_ops = { |
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331 | .init = lpc24xx_i2c_init, |
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332 | .send_start = lpc24xx_i2c_send_start, |
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333 | .send_stop = lpc24xx_i2c_send_stop, |
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334 | .send_addr = lpc24xx_i2c_send_addr, |
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335 | .read_bytes = lpc24xx_i2c_read, |
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336 | .write_bytes = lpc24xx_i2c_write, |
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337 | .ioctl = lpc24xx_i2c_ioctl |
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338 | }; |
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339 | |
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340 | #ifdef LPC24XX_CONFIG_I2C_0 |
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341 | static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_0 = { |
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342 | .bus = { |
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343 | .ops = &lpc24xx_i2c_ops, |
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344 | .size = sizeof(lpc24xx_i2c_bus_entry) |
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345 | }, |
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346 | .regs = (volatile lpc24xx_i2c *) I2C0_BASE_ADDR, |
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347 | .index = 0, |
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348 | .config = LPC24XX_CONFIG_I2C_0, |
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349 | .vector = LPC24XX_IRQ_I2C_0 |
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350 | }; |
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351 | |
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352 | rtems_libi2c_bus_t * const lpc24xx_i2c_0 = |
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353 | (rtems_libi2c_bus_t *) &lpc24xx_i2c_entry_0; |
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354 | #endif |
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355 | |
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356 | #ifdef LPC24XX_CONFIG_I2C_1 |
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357 | static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_1 = { |
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358 | .bus = { |
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359 | .ops = &lpc24xx_i2c_ops, |
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360 | .size = sizeof(lpc24xx_i2c_bus_entry) |
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361 | }, |
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362 | .regs = (volatile lpc24xx_i2c *) I2C1_BASE_ADDR, |
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363 | .index = 1, |
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364 | .config = LPC24XX_CONFIG_I2C_1, |
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365 | .vector = LPC24XX_IRQ_I2C_1 |
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366 | }; |
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367 | |
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368 | rtems_libi2c_bus_t * const lpc24xx_i2c_1 = |
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369 | (rtems_libi2c_bus_t *) &lpc24xx_i2c_entry_1; |
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370 | #endif |
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371 | |
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372 | #ifdef LPC24XX_CONFIG_I2C_2 |
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373 | static lpc24xx_i2c_bus_entry lpc24xx_i2c_entry_2 = { |
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374 | .bus = { |
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375 | .ops = &lpc24xx_i2c_ops, |
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376 | .size = sizeof(lpc24xx_i2c_bus_entry) |
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377 | }, |
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378 | .regs = (volatile lpc24xx_i2c *) I2C2_BASE_ADDR, |
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379 | .index = 2, |
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380 | .config = LPC24XX_CONFIG_I2C_2, |
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381 | .vector = LPC24XX_IRQ_I2C_2 |
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382 | }; |
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383 | |
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384 | rtems_libi2c_bus_t * const lpc24xx_i2c_2 = |
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385 | (rtems_libi2c_bus_t *) &lpc24xx_i2c_entry_2; |
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386 | #endif |
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