source: rtems/c/src/lib/libbsp/arm/lpc176x/startup/linkcmds.lpc1768_mbed_ahb_ram_eth @ d4edbdbc

4.115
Last change on this file since d4edbdbc was cbc433c7, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2014 at 7:40:20 AM

bsps/arm: Add .nocache section

This section can be use to provide a cache coherent memory area via
rtems_cache_coherent_add_area().

  • Property mode set to 100644
File size: 1.4 KB
Line 
1/* LPC1768 OEM Board from Embedded Artists */
2
3MEMORY {
4        ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 512k
5        RAM_INT (AIW) : ORIGIN = 0x10000000, LENGTH = 32k
6        RAM_AHB1 (AIW) : ORIGIN = 0x2007C000, LENGTH = 16k
7        RAM_AHB2 (AIW) : ORIGIN = 0x20080000, LENGTH = 16k
8}
9
10REGION_ALIAS ("REGION_START", ROM_INT);
11REGION_ALIAS ("REGION_VECTOR", RAM_INT);
12REGION_ALIAS ("REGION_TEXT", ROM_INT);
13REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
14REGION_ALIAS ("REGION_RODATA", ROM_INT);
15REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
16REGION_ALIAS ("REGION_DATA", RAM_INT);
17REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
18REGION_ALIAS ("REGION_FAST_TEXT", RAM_INT);
19REGION_ALIAS ("REGION_FAST_TEXT_LOAD", ROM_INT);
20REGION_ALIAS ("REGION_FAST_DATA", RAM_INT);
21REGION_ALIAS ("REGION_FAST_DATA_LOAD", ROM_INT);
22REGION_ALIAS ("REGION_BSS", RAM_AHB1);
23REGION_ALIAS ("REGION_WORK", RAM_INT);
24REGION_ALIAS ("REGION_STACK", RAM_INT);
25REGION_ALIAS ("REGION_ETH", RAM_AHB2);
26REGION_ALIAS ("REGION_NOCACHE", RAM_INT);
27REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT);
28
29bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 1024;
30bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
31
32SECTIONS {
33    .eth (NOLOAD) : ALIGN_WITH_INPUT {
34        bsp_section_eth_begin = .;
35        *(.eth)
36        bsp_section_eth_end = .;
37    } > REGION_ETH AT > REGION_ETH
38    bsp_section_eth_size = bsp_section_eth_end - bsp_section_eth_begin;
39}
40
41INCLUDE linkcmds.armv7m
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