1 | /** |
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2 | * @file gpio-defs.h |
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3 | * |
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4 | * @ingroup lpc176x |
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5 | * |
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6 | * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2014 Taller Technologies. |
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11 | * |
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12 | * @author Boretto Martin (martin.boretto@tallertechnologies.com) |
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13 | * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) |
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14 | * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) |
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15 | * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H |
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23 | #define LIBBSP_ARM_LPC176X_GPIO_DEFS_H |
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24 | |
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25 | #include <bsp/common-types.h> |
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26 | |
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27 | #ifdef __cplusplus |
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28 | extern "C" { |
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29 | #endif /* __cplusplus */ |
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30 | |
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31 | /* General Purpose Input/Output (GPIO) */ |
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32 | #define LPC176X_GPIO_BASE_ADDR 0x40028000U |
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33 | #define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U |
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34 | |
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35 | #define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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36 | 0x00U ) ) |
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37 | #define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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38 | 0x04U ) ) |
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39 | #define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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40 | 0x08U ) ) |
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41 | #define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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42 | 0x0CU ) ) |
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43 | #define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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44 | 0x10U ) ) |
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45 | #define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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46 | 0x14U ) ) |
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47 | #define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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48 | 0x18U ) ) |
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49 | #define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ |
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50 | 0x1CU ) ) |
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51 | |
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52 | /* GPIO Interrupt Registers */ |
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53 | #define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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54 | + 0x90U ) ) |
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55 | #define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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56 | + 0x94U ) ) |
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57 | #define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \ |
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58 | LPC176X_GPIO_BASE_ADDR \ |
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59 | + 0x84U ) ) |
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60 | #define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \ |
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61 | LPC176X_GPIO_BASE_ADDR \ |
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62 | + 0x88U ) ) |
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63 | #define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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64 | + 0x8CU ) ) |
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65 | #define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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66 | + 0xB0U ) ) |
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67 | #define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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68 | + 0xB4U ) ) |
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69 | #define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \ |
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70 | LPC176X_GPIO_BASE_ADDR \ |
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71 | + 0xA4U ) ) |
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72 | #define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \ |
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73 | LPC176X_GPIO_BASE_ADDR \ |
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74 | + 0xA8U ) ) |
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75 | #define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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76 | + 0xACU ) ) |
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77 | #define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ |
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78 | + 0x80U ) ) |
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79 | |
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80 | #define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U |
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81 | #define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U |
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82 | |
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83 | #define LPC176X_MAX_PORT_NUMBER 160U |
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84 | #define LPC176X_SET_BIT( reg, pin, value ) \ |
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85 | reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin ) |
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86 | |
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87 | #define LPC176X_INT_STATUS ( *(volatile uint32_t *) \ |
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88 | ( LPC176X_GPIO_INTERRUPT_STATUS ) ) |
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89 | #define LPC176X_INT_STATUS_P0 1U |
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90 | #define LPC176X_INT_STATUS_P2 ( 1U << 2U ) |
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91 | #define LPC176X_INT_ENABLE 1U |
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92 | #define LPC176X_INT_DISABLE 0U |
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93 | |
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94 | #define LPC176X_IRQ_EINT_3 21U |
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95 | |
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96 | #define LPC176X_PIN_BIT( pin ) ( 1U << pin ) |
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97 | |
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98 | /** |
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99 | * @brief The direction of the GPIO port (input or output). |
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100 | * |
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101 | * Enumerated type to define the set of function types for a gpio device. |
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102 | */ |
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103 | typedef enum { |
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104 | LPC176X_GPIO_FUNCTION_INPUT, |
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105 | LPC176X_GPIO_FUNCTION_OUTPUT, |
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106 | LPC176X_GPIO_FUNCTION_COUNT |
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107 | } |
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108 | lpc176x_gpio_direction; |
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109 | |
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110 | /** |
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111 | * @brief The interrupt sources edge for a GPIO. |
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112 | * |
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113 | * Enumerated type to define the set of interrupt types for a gpio device. |
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114 | */ |
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115 | typedef enum { |
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116 | LPC176X_GPIO_INTERRUPT_DISABLE, |
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117 | LPC176X_GPIO_INTERRUPT_RISING, |
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118 | LPC176X_GPIO_INTERRUPT_FALLING, |
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119 | LPC176X_GPIO_INTERRUPT_BOTH, |
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120 | LPC176X_GPIO_INTERRUPT_COUNT |
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121 | } lpc176x_gpio_interrupt; |
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122 | |
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123 | /** |
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124 | * @brief The ports for a GPIO. |
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125 | * |
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126 | * Enumerated type to define the set of ports for a gpio device. |
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127 | */ |
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128 | typedef enum { |
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129 | LPC176X_GPIO_PORT_0, |
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130 | LPC176X_GPIO_PORT_1, |
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131 | LPC176X_GPIO_PORT_2, |
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132 | LPC176X_GPIO_PORT_3, |
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133 | LPC176X_GPIO_PORT_4, |
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134 | LPC176X_GPIO_PORTS_COUNT |
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135 | } lpc176x_gpio_ports; |
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136 | |
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137 | /** |
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138 | * @brief Addresses for a GPIO. |
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139 | * |
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140 | * Enumerated type to define the set of fio bases addresses |
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141 | * for a gpio device. |
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142 | */ |
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143 | typedef enum { |
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144 | LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U, |
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145 | LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U, |
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146 | LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U, |
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147 | LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U, |
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148 | LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U, |
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149 | } lpc176x_gpio_address; |
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150 | |
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151 | /** |
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152 | * @brief Addresses for the two interrupts. |
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153 | * |
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154 | * Enumerated type to define the set of interrupt addresses |
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155 | * for a gpio device. |
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156 | */ |
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157 | typedef enum { |
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158 | LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U, |
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159 | LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U, |
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160 | } lpc176x_interrupt_address; |
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161 | |
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162 | /** |
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163 | * @brief GPIO Interrupt register map. |
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164 | */ |
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165 | typedef struct { |
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166 | /** |
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167 | * @brief Interrupt Enable for Rising edge. |
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168 | */ |
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169 | volatile uint32_t StatR; |
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170 | /** |
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171 | * @brief Interrupt Enable for Falling edge. |
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172 | */ |
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173 | volatile uint32_t StatF; |
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174 | /** |
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175 | * @brief Interrupt Clear. |
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176 | */ |
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177 | volatile uint32_t Clr; |
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178 | /** |
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179 | * @brief Interrupt Enable for Rising edge. |
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180 | */ |
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181 | volatile uint32_t EnR; |
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182 | /** |
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183 | * @brief Interrupt Enable for Falling edge. |
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184 | */ |
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185 | volatile uint32_t EnF; |
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186 | } lpc176x_interrupt_control; |
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187 | |
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188 | /** |
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189 | * @brief A function that attends an interrupt for GPIO. |
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190 | * |
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191 | * @param pin Pin number. |
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192 | * @param edge Interrupt. |
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193 | * @return Pointer to the interrupt function. |
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194 | */ |
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195 | typedef void (*lpc176x_gpio_interrupt_function) ( |
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196 | const lpc176x_pin_number pin, |
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197 | const lpc176x_gpio_interrupt edge |
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198 | ); |
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199 | |
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200 | /** |
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201 | * @brief A registered interrupt function for the pin 'pin'. |
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202 | */ |
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203 | typedef struct { |
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204 | /** |
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205 | * @brief Pin board. |
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206 | */ |
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207 | lpc176x_pin_number pin; |
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208 | /** |
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209 | * @brief A function that attends an interrupt for 'pin'. |
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210 | */ |
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211 | lpc176x_gpio_interrupt_function function; |
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212 | } lpc176x_registered_interrupt_function; |
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213 | |
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214 | #ifdef __cplusplus |
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215 | } |
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216 | #endif /* __cplusplus */ |
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217 | |
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218 | #endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */ |
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