source: rtems/c/src/lib/libbsp/arm/lm3s69xx/include/lm3s69xx.h @ 847e2cac

4.115
Last change on this file since 847e2cac was 847e2cac, checked in by Eugeniy Meshcheryakov <eugen@…>, on May 5, 2013 at 10:02:06 PM

bsp/lm3s69xx: More access macros for UART data register

Add mask for receive error bits and getter macro for
the data field.

  • Property mode set to 100644
File size: 10.2 KB
Line 
1/*
2 * Copyright © 2013 Eugeniy Meshcheryakov <eugen@debian.org>
3 *
4 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
5 *
6 *  embedded brains GmbH
7 *  Obere Lagerstr. 30
8 *  82178 Puchheim
9 *  Germany
10 *  <rtems@embedded-brains.de>
11 *
12 * The license and distribution terms for this file may be
13 * found in the file LICENSE in this distribution or at
14 * http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef LIBBSP_ARM_LM3S69XX_LM3S69XX_H
18#define LIBBSP_ARM_LM3S69XX_LM3S69XX_H
19#include <bspopts.h>
20#include <bsp/utility.h>
21
22#define LM3S69XX_SYSCON_BASE 0x400fe000
23
24#define LM3S69XX_UART_0_BASE 0x4000c000
25#define LM3S69XX_UART_1_BASE 0x4000d000
26#define LM3S69XX_UART_2_BASE 0x4000e000
27
28#ifdef LM3S69XX_USE_AHB_FOR_GPIO
29#define LM3S69XX_GPIO_A_BASE 0x40058000
30#define LM3S69XX_GPIO_B_BASE 0x40059000
31#define LM3S69XX_GPIO_C_BASE 0x4005a000
32#define LM3S69XX_GPIO_D_BASE 0x4005b000
33#define LM3S69XX_GPIO_E_BASE 0x4005c000
34#define LM3S69XX_GPIO_F_BASE 0x4005d000
35#define LM3S69XX_GPIO_G_BASE 0x4005e000
36#if LM3S69XX_NUM_GPIO_BLOCKS > 7
37#define LM3S69XX_GPIO_H_BASE 0x4005f000
38#endif
39
40#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(LM3S69XX_GPIO_A_BASE + (port) * 0x1000))
41#else /* LM3S69XX_USE_AHB_FOR_GPIO */
42#define LM3S69XX_GPIO_A_BASE 0x40004000
43#define LM3S69XX_GPIO_B_BASE 0x40005000
44#define LM3S69XX_GPIO_C_BASE 0x40006000
45#define LM3S69XX_GPIO_D_BASE 0x40007000
46#define LM3S69XX_GPIO_E_BASE 0x40024000
47#define LM3S69XX_GPIO_F_BASE 0x40025000
48#define LM3S69XX_GPIO_G_BASE 0x40026000
49#if LM3S69XX_NUM_GPIO_BLOCKS > 7
50#define LM3S69XX_GPIO_H_BASE 0x40027000
51#endif
52
53#define LM3S69XX_GPIO(port) ((volatile lm3s69xx_gpio *)(((port) < 4) ? \
54           (LM3S69XX_GPIO_A_BASE + (port) * 0x1000) : \
55           (LM3S69XX_GPIO_E_BASE + ((port) - 4) * 0x1000)))
56#endif /* LM3S69XX_USE_AHB_FOR_GPIO */
57
58#define LM3S69XX_SSI_0_BASE 0x40008000
59#if LM3S69XX_NUM_SSI_BLOCKS > 1
60#define LM3S69XX_SSI_1_BASE 0x40009000
61#endif
62
63#define LM3S69XX_SYSCON ((volatile lm3s69xx_syscon *)LM3S69XX_SYSCON_BASE)
64
65#define LM3S69XX_PLL_FREQUENCY 400000000U
66
67typedef struct  {
68  uint32_t data[256]; /* Masked data registers are included here. */
69  uint32_t dir;
70  uint32_t is;
71  uint32_t ibe;
72  uint32_t iev;
73  uint32_t im;
74  uint32_t ris;
75  uint32_t mis;
76  uint32_t icr;
77  uint32_t afsel;
78
79  uint32_t reserved_0[55];
80
81  uint32_t dr2r;
82  uint32_t dr4r;
83  uint32_t dr8r;
84  uint32_t odr;
85  uint32_t pur;
86  uint32_t pdr;
87  uint32_t slr;
88  uint32_t den;
89  uint32_t lock;
90  uint32_t cr;
91  uint32_t amsel;
92} lm3s69xx_gpio;
93
94typedef struct {
95  uint32_t did0;
96  uint32_t did1;
97
98  uint32_t dc0;
99  uint32_t reserved_0;
100  uint32_t dc1;
101  uint32_t dc2;
102  uint32_t dc3;
103  uint32_t dc4;
104  uint32_t dc5;
105  uint32_t dc6;
106  uint32_t dc7;
107
108  uint32_t reserved_1;
109
110#define SYSCONPBORCTL_BORIOR BSP_BIT32(1)
111  uint32_t pborctl;
112
113#define SYSCONLDOPCTL_VADJ(val) BSP_FLD32(val, 0, 5)
114#define SYSCONLDOPCTL_VADJ_MASK BSP_MSK32(0, 5)
115  uint32_t ldopctl;
116
117  uint32_t reserved_2[2];
118
119  uint32_t srcr0;
120  uint32_t srcr1;
121  uint32_t srcr2;
122
123  uint32_t reserved_3;
124
125#define SYSCONRIS_MOSCPUPRIS BSP_BIT32(8)
126#define SYSCONRIS_USBPLLRIS BSP_BIT32(7)
127#define SYSCONRIS_PLLLRIS BSP_BIT32(6)
128#define SYSCONRIS_BORRIS BSP_BIT32(1)
129  uint32_t ris;
130
131#define SYSCONIMC_MOSCPUPIM BSP_BIT32(8)
132#define SYSCONIMC_USBPLLLIM BSP_BIT32(7)
133#define SYSCONIMC_PLLLIM BSP_BIT32(6)
134#define SYSCONIMC_BORIM BSP_BIT32(1)
135  uint32_t imc;
136
137#define SYSCONMISC_MOSCPUPMIS BSP_BIT32(8)
138#define SYSCONMISC_USBPLLLMIS BSP_BIT32(7)
139#define SYSCONMISC_PLLLMIS BSP_BIT32(6)
140#define SYSCONMISC_BORMIS BSP_BIT32(1)
141  uint32_t misc;
142
143#define SYSCONRESC_MOSCFAIL BSP_BIT32(16)
144#define SYSCONRESC_SW BSP_BIT32(4)
145#define SYSCONRESC_WDT BSP_BIT32(3)
146#define SYSCONRESC_BOR BSP_BIT32(2)
147#define SYSCONRESC_POR BSP_BIT32(1)
148#define SYSCONRESC_EXT BSP_BIT32(0)
149  uint32_t resc;
150
151#define SYSCONRCC_AGC BSP_BIT32(27)
152#define SYSCONRCC_SYSDIV(val) BSP_FLD32(val, 23, 26)
153#define SYSCONRCC_SYSDIV_MSK BSP_MSK32(23, 26)
154#define SYSCONRCC_USESYSDIV BSP_BIT32(22)
155#define SYSCONRCC_USEPWMDIV BSP_BIT32(20)
156#define SYSCONRCC_PWMDIV(val) BSP_FLD32(val, 17, 19)
157#define SYSCONRCC_PWMDIV_DIV2_VAL 0
158#define SYSCONRCC_PWMDIV_DIV4_VAL 1
159#define SYSCONRCC_PWMDIV_DIV8_VAL 2
160#define SYSCONRCC_PWMDIV_DIV16_VAL 3
161#define SYSCONRCC_PWMDIV_DIV32_VAL 4
162#define SYSCONRCC_PWMDIV_DIV64_VAL 5
163#define SYSCONRCC_PWMDIV_MSK BSP_MSK32(17, 19)
164#define SYSCONRCC_PWRDN BSP_BIT32(13)
165#define SYSCONRCC_BYPASS BSP_BIT32(11)
166#define SYSCONRCC_XTAL(val) BSP_FLD32(val, 6, 10)
167#define SYSCONRCC_XTAL_MSK BSP_MSK32(6, 10)
168#define SYSCONRCC_OSCSRC(val) BSP_FLD32(val, 4, 5)
169#define SYSCONRCC_OSCSRC_MOSC SYSCONRCC_OSCSRC(0x0)
170#define SYSCONRCC_OSCSRC_IOSC SYSCONRCC_OSCSRC(0x1)
171#define SYSCONRCC_OSCSRC_IOSC_DIV_4 SYSCONRCC_OSCSRC(0x2)
172#define SYSCONRCC_OSCSRC_30KHZ SYSCONRCC_OSCSRC(0x3)
173#define SYSCONRCC_OSCSRC_MSK BSP_MSK32(4, 5)
174#define SYSCONRCC_IOSCDIS BSP_BIT32(1)
175#define SYSCONRCC_MOSCDIS BSP_BIT32(0)
176  uint32_t rcc;
177
178#define SYSCONPLLCFG_F(val) BSP_FLD32(val, 5, 13)
179#define SYSCONPLLCFG_F_MSK BSP_MSK32(5, 13)
180#define SYSCONPLLCFG_R(val) BSP_FLD32(val, 0, 4)
181#define SYSCONPLLCFG_R_MSK BSP_MSK32(0, 4)
182  uint32_t pllcfg;
183
184  uint32_t reserved_4;
185
186#define SYSCONGPIOHBCTL_PORTH BSP_BIT32(7)
187#define SYSCONGPIOHBCTL_PORTG BSP_BIT32(6)
188#define SYSCONGPIOHBCTL_PORTF BSP_BIT32(5)
189#define SYSCONGPIOHBCTL_PORTE BSP_BIT32(4)
190#define SYSCONGPIOHBCTL_PORTD BSP_BIT32(3)
191#define SYSCONGPIOHBCTL_PORTC BSP_BIT32(2)
192#define SYSCONGPIOHBCTL_PORTB BSP_BIT32(1)
193#define SYSCONGPIOHBCTL_PORTA BSP_BIT32(0)
194  uint32_t gpiohbctl;
195
196#define SYSCONRCC2_USERCC2 BSP_BIT32(31)
197#define SYSCONRCC2_SYSDIV2(val) BSP_FLD32(val, 23, 28)
198#define SYSCONRCC2_SYSDIV2_MSK(val) BSP_MSK32(23, 28)
199#define SYSCONRCC2_USBPWRDN BSP_BIT32(14)
200#define SYSCONRCC2_PWRDN2 BSP_BIT32(13)
201#define SYSCONRCC2_BYPASS2 BSP_BIT32(11)
202#define SYSCONRCC2_OSCSRC2(val) BSP_FLD32(val, 4, 6)
203#define SYSCONRCC2_OSCSRC2_MSK BSP_MSK32(4, 6)
204  uint32_t rcc2;
205
206  uint32_t reserved_5[2];
207
208#define SYSCONMOSCCTL_CVAL BSP_BIT32(0)
209  uint32_t moscctl;
210
211  uint32_t reserved_6[32];
212
213#define SYSCONRCGC0_PWM BSP_BIT32(20)
214#define SYSCONRCGC0_ADC BSP_BIT32(16)
215#define SYSCONRCGC0_MAXADCSPD(val) BSP_FLD32(val, 8, 9)
216#define SYSCONRCGC0_MAXADCSPD_MSK BSP_MSK32(8, 9)
217#define SYSCONRCGC0_HIB BSP_BIT32(6)
218#define SYSCONRCGC0_WDT BSP_BIT32(3)
219  uint32_t rcgc0;
220
221#define SYSCONRCGC1_COMP1 BSP_BIT32(25)
222#define SYSCONRCGC1_COMP0 BSP_BIT32(24)
223#define SYSCONRCGC1_TIMER3 BSP_BIT32(19)
224#define SYSCONRCGC1_TIMER2 BSP_BIT32(18)
225#define SYSCONRCGC1_TIMER1 BSP_BIT32(17)
226#define SYSCONRCGC1_TIMER0 BSP_BIT32(16)
227#define SYSCONRCGC1_I2C1 BSP_BIT32(14)
228#define SYSCONRCGC1_I2C0 BSP_BIT32(12)
229#define SYSCONRCGC1_QEI0 BSP_BIT32(8)
230#if LM3S69XX_NUM_SSI_BLOCKS > 1
231#define SYSCONRCGC1_SSI1 BSP_BIT32(5)
232#endif
233#define SYSCONRCGC1_SSI0 BSP_BIT32(4)
234#define SYSCONRCGC1_UART2 BSP_BIT32(2)
235#define SYSCONRCGC1_UART1 BSP_BIT32(1)
236#define SYSCONRCGC1_UART0 BSP_BIT32(0)
237  uint32_t rcgc1;
238
239#define SYSCONRCGC2_USB0 BSP_BIT32(16)
240#define SYSCONRCGC2_UDMA BSP_BIT32(13)
241#if LM3S69XX_NUM_GPIO_BLOCKS > 7
242#define SYSCONRCGC2_GPIOH BSP_BIT32(7)
243#endif
244#define SYSCONRCGC2_GPIOG BSP_BIT32(6)
245#define SYSCONRCGC2_GPIOF BSP_BIT32(5)
246#define SYSCONRCGC2_GPIOE BSP_BIT32(4)
247#define SYSCONRCGC2_GPIOD BSP_BIT32(3)
248#define SYSCONRCGC2_GPIOC BSP_BIT32(2)
249#define SYSCONRCGC2_GPIOB BSP_BIT32(1)
250#define SYSCONRCGC2_GPIOA BSP_BIT32(0)
251  uint32_t rcgc2;
252
253  uint32_t reserved_7;
254
255  uint32_t scgc0;
256  uint32_t scgc1;
257  uint32_t scgc2;
258
259  uint32_t reserved_8;
260
261  uint32_t dcgc0;
262  uint32_t dcgc1;
263  uint32_t dcgc2;
264
265  uint32_t reserved_9[6];
266
267#define SYSCONDSLPCLKCFG_DSDIVORIDE(val) BSP_FLD32(val, 23, 28)
268#define SYSCONDSLPCLKCFG_DSDIVORIDE_MSK BSP_MSK32(23, 28)
269#define SYSCONDSLPCLKCFG_DSOSCSRC(val) BSP_FLD32(val, 4, 6)
270#define SYSCONDSLPCLKCFG_DSOSCSRC_MSK BSP_MSK32(4, 6)
271  uint32_t dslpclkcfg;
272} lm3s69xx_syscon;
273
274typedef struct {
275#define UARTDR_OE BSP_BIT32(11)
276#define UARTDR_BE BSP_BIT32(10)
277#define UARTDR_PE BSP_BIT32(9)
278#define UARTDR_FE BSP_BIT32(8)
279#define UARTDR_ERROR_MSK BSP_MSK32(8, 11)
280#define UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
281#define UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
282  uint32_t dr;
283
284  uint32_t rsr_ecr;
285  uint32_t reserved_0[4];
286
287#define UARTFR_TXFE BSP_BIT32(7)
288#define UARTFR_RXFF BSP_BIT32(6)
289#define UARTFR_TXFF BSP_BIT32(5)
290#define UARTFR_RXFE BSP_BIT32(4)
291#define UARTFR_BUSY BSP_BIT32(3)
292  uint32_t fr;
293
294  uint32_t reserved_1;
295
296  uint32_t ilpr;
297  uint32_t ibrd;
298  uint32_t fbrd;
299
300#define UARTLCRH_SPS BSP_BIT32(7)
301#define UARTLCRH_WLEN(val) BSP_FLD32(val, 5, 6)
302#define UARTLCRH_FEN BSP_BIT32(4)
303#define UARTLCRH_STP2 BSP_BIT32(3)
304#define UARTLCRH_EPS BSP_BIT32(2)
305#define UARTLCRH_PEN BSP_BIT32(1)
306#define UARTLCRH_BRK BSP_BIT32(0)
307  uint32_t lcrh;
308
309#define UARTCTL_RXE BSP_BIT32(9)
310#define UARTCTL_TXE BSP_BIT32(8)
311#define UARTCTL_LBE BSP_BIT32(7)
312#define UARTCTL_SIRLP BSP_BIT32(2)
313#define UARTCTL_SIREN BSP_BIT32(1)
314#define UARTCTL_UARTEN BSP_BIT32(0)
315  uint32_t ctl;
316
317#define UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
318#define UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
319  uint32_t ifls;
320
321#define UARTI_OE BSP_BIT32(10)
322#define UARTI_BE BSP_BIT32(9)
323#define UARTI_PE BSP_BIT32(8)
324#define UARTI_FE BSP_BIT32(7)
325#define UARTI_RT BSP_BIT32(6)
326#define UARTI_TX BSP_BIT32(5)
327#define UARTI_RX BSP_BIT32(4)
328  uint32_t im;
329  uint32_t ris;
330  uint32_t mis;
331  uint32_t icr;
332#if LM3S69XX_HAS_UDMA
333  uint32_t dmactl;
334#endif
335} lm3s69xx_uart;
336
337typedef struct {
338#define SSICR0_SCR(val) BSP_FLD32(val, 8, 15)
339#define SSICR0_SPH BSP_BIT32(7)
340#define SSICR0_SPO BSP_BIT32(6)
341#define SSICR0_FRF(val) BSP_FLD32(val, 4, 5)
342#define SSICR0_DSS(val) BSP_FLD32(val, 0, 3)
343  uint32_t cr0;
344
345#define SSICR1_SOD BSP_BIT32(3)
346#define SSICR1_MS BSP_BIT32(2)
347#define SSICR1_SSE BSP_BIT32(1)
348#define SSICR1_LBM BSP_BIT32(0)
349  uint32_t cr1;
350  uint32_t dr;
351
352#define SSISR_BSY BSP_BIT32(4)
353#define SSISR_RFF BSP_BIT32(3)
354#define SSISR_RNE BSP_BIT32(2)
355#define SSISR_TNF BSP_BIT32(1)
356#define SSISR_TFE BSP_BIT32(0)
357  uint32_t sr;
358
359#define SSI_CPSRDIV(val) BSP_FLD32(val, 0, 7)
360  uint32_t cpsr;
361
362#define SSII_TX BSP_BIT32(3)
363#define SSII_RX BSP_BIT32(2)
364#define SSII_RT BSP_BIT32(1)
365#define SSII_ROR BSP_BIT32(0)
366  uint32_t im;
367  uint32_t ris;
368  uint32_t mis;
369  uint32_t icr;
370
371#if LM3S69XX_HAS_UDMA
372#define SSIDMACTL_TXDMAE BSP_BIT32(1)
373#define SSIDMACTL_RXDMAE BSP_BIT32(0)
374  uint32_t dmactl;
375#endif /* LM3S69XX_HAS_UDMA */
376} lm3s69xx_ssi;
377
378#endif /* LIBBSP_ARM_LM3S69XX_LM3S69XX_H */
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