source: rtems/c/src/lib/libbsp/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch @ e1ebfebf

4.115
Last change on this file since e1ebfebf was e1ebfebf, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 11, 2012 at 8:15:06 PM

Patches for Qemu 1.0.50

  • Property mode set to 100644
File size: 2.4 KB
  • cpu-exec.c

    From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
    From: Sebastian Huber <sebastian.huber@embedded-brains.de>
    Date: Fri, 16 Dec 2011 20:12:29 +0100
    Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX
    
    This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
    BASEPRI_MAX feature working.
    
    Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
    ---
     cpu-exec.c          |    4 ++--
     target-arm/helper.c |   12 +++++-------
     2 files changed, 7 insertions(+), 9 deletions(-)
    
    diff --git a/cpu-exec.c b/cpu-exec.c
    index a9fa608..6ca9aab 100644
    a b int cpu_exec(CPUState *env) 
    408408                       We avoid this by disabling interrupts when
    409409                       pc contains a magic address.  */
    410410                    if (interrupt_request & CPU_INTERRUPT_HARD
    411                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
    412                             || !(env->uncached_cpsr & CPSR_I))) {
     411                        && !(env->uncached_cpsr & CPSR_I)
     412                        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
    413413                        env->exception_index = EXCP_IRQ;
    414414                        do_interrupt(env);
    415415                        next_tb = 0;
  • target-arm/helper.c

    diff --git a/target-arm/helper.c b/target-arm/helper.c
    index 65f4fbf..be2e6db 100644
    a b uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg) 
    21632163        return (env->uncached_cpsr & CPSR_I) != 0;
    21642164    case 17: /* BASEPRI */
    21652165    case 18: /* BASEPRI_MAX */
    2166         return env->v7m.basepri;
     2166        return (env->uncached_cpsr & CPSR_I) != 0;
    21672167    case 19: /* FAULTMASK */
    21682168        return (env->uncached_cpsr & CPSR_F) != 0;
    21692169    case 20: /* CONTROL */
    void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) 
    22182218            env->uncached_cpsr &= ~CPSR_I;
    22192219        break;
    22202220    case 17: /* BASEPRI */
    2221         env->v7m.basepri = val & 0xff;
    2222         break;
    22232221    case 18: /* BASEPRI_MAX */
    2224         val &= 0xff;
    2225         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
    2226             env->v7m.basepri = val;
    2227         break;
     2222        if (val)
     2223            env->uncached_cpsr |= CPSR_I;
     2224        else
     2225            env->uncached_cpsr &= ~CPSR_I;
    22282226    case 19: /* FAULTMASK */
    22292227        if (val & 1)
    22302228            env->uncached_cpsr |= CPSR_F;
Note: See TracBrowser for help on using the repository browser.