source: rtems/c/src/lib/libbsp/arm/lm3s69xx/0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch @ 0afac6a

4.115
Last change on this file since 0afac6a was e1ebfebf, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 11, 2012 at 8:15:06 PM

Patches for Qemu 1.0.50

  • Property mode set to 100644
File size: 2.4 KB
RevLine 
[e1ebfebf]1From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
2From: Sebastian Huber <sebastian.huber@embedded-brains.de>
3Date: Fri, 16 Dec 2011 20:12:29 +0100
4Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX
5
6This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
7BASEPRI_MAX feature working.
8
9Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
10---
11 cpu-exec.c          |    4 ++--
12 target-arm/helper.c |   12 +++++-------
13 2 files changed, 7 insertions(+), 9 deletions(-)
14
15diff --git a/cpu-exec.c b/cpu-exec.c
16index a9fa608..6ca9aab 100644
17--- a/cpu-exec.c
18+++ b/cpu-exec.c
19@@ -408,8 +408,8 @@ int cpu_exec(CPUState *env)
20                        We avoid this by disabling interrupts when
21                        pc contains a magic address.  */
22                     if (interrupt_request & CPU_INTERRUPT_HARD
23-                        && ((IS_M(env) && env->regs[15] < 0xfffffff0)
24-                            || !(env->uncached_cpsr & CPSR_I))) {
25+                        && !(env->uncached_cpsr & CPSR_I)
26+                        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
27                         env->exception_index = EXCP_IRQ;
28                         do_interrupt(env);
29                         next_tb = 0;
30diff --git a/target-arm/helper.c b/target-arm/helper.c
31index 65f4fbf..be2e6db 100644
32--- a/target-arm/helper.c
33+++ b/target-arm/helper.c
34@@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
35         return (env->uncached_cpsr & CPSR_I) != 0;
36     case 17: /* BASEPRI */
37     case 18: /* BASEPRI_MAX */
38-        return env->v7m.basepri;
39+        return (env->uncached_cpsr & CPSR_I) != 0;
40     case 19: /* FAULTMASK */
41         return (env->uncached_cpsr & CPSR_F) != 0;
42     case 20: /* CONTROL */
43@@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
44             env->uncached_cpsr &= ~CPSR_I;
45         break;
46     case 17: /* BASEPRI */
47-        env->v7m.basepri = val & 0xff;
48-        break;
49     case 18: /* BASEPRI_MAX */
50-        val &= 0xff;
51-        if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
52-            env->v7m.basepri = val;
53-        break;
54+        if (val)
55+            env->uncached_cpsr |= CPSR_I;
56+        else
57+            env->uncached_cpsr &= ~CPSR_I;
58     case 19: /* FAULTMASK */
59         if (val & 1)
60             env->uncached_cpsr |= CPSR_F;
61--
621.7.1
63
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