source: rtems/c/src/lib/libbsp/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch @ 0afac6a

4.115
Last change on this file since 0afac6a was e1ebfebf, checked in by Sebastian Huber <sebastian.huber@…>, on Feb 11, 2012 at 8:15:06 PM

Patches for Qemu 1.0.50

  • Property mode set to 100644
File size: 4.0 KB
  • hw/arm_gic.c

    From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
    From: Sebastian Huber <sebastian.huber@embedded-brains.de>
    Date: Fri, 16 Dec 2011 19:46:40 +0100
    Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
    
    According to "ARMv7-M Architecture Reference Manual" issue D section
    "B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
    Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
    Register 3, SHPR3".
    
    Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
    ---
     hw/arm_gic.c     |   16 ++++++++++++++--
     hw/armv7m_nvic.c |   19 -------------------
     2 files changed, 14 insertions(+), 21 deletions(-)
    
    diff --git a/hw/arm_gic.c b/hw/arm_gic.c
    index 9b52119..5139d95 100644
    a b static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) 
    356356            if (GIC_TEST_TRIGGER(irq + i))
    357357                res |= (2 << (i * 2));
    358358        }
     359#else
     360    } else if (0xd18 <= offset && offset < 0xd24) {
     361        /* System Handler Priority.  */
     362        irq = offset - 0xd14;
     363        res = GIC_GET_PRIORITY(irq, cpu);
    359364#endif
    360365    } else if (offset < 0xfe0) {
    361366        goto bad_reg;
    static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) 
    387392    gic_state *s = (gic_state *)opaque;
    388393    uint32_t addr;
    389394    addr = offset;
    390     if (addr < 0x100 || addr > 0xd00)
     395    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
     396        && addr != 0xd20))
    391397        return nvic_readl(s, addr);
    392398#endif
    393399    val = gic_dist_readw(opaque, offset);
    static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, 
    528534                GIC_CLEAR_TRIGGER(irq + i);
    529535            }
    530536        }
     537#else
     538    } else if (0xd18 <= offset && offset < 0xd24) {
     539        /* System Handler Priority.  */
     540        irq = offset - 0xd14;
     541        s->priority1[irq][0] = value & 0xff;
    531542#endif
    532543    } else {
    533544        /* 0xf00 is only handled for 32-bit writes.  */
    static void gic_dist_writel(void *opaque, target_phys_addr_t offset, 
    553564#ifdef NVIC
    554565    uint32_t addr;
    555566    addr = offset;
    556     if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
     567    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
     568        && addr != 0xd20 && addr != 0xf00)) {
    557569        nvic_writel(s, addr, value);
    558570        return;
    559571    }
  • hw/armv7m_nvic.c

    diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
    index bf8c3c5..65b575e 100644
    a b static uint32_t nvic_readl(void *opaque, uint32_t offset) 
    195195    case 0xd14: /* Configuration Control.  */
    196196        /* TODO: Implement Configuration Control bits.  */
    197197        return 0;
    198     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
    199         irq = offset - 0xd14;
    200         val = 0;
    201         val |= s->gic.priority1[irq++][0];
    202         val |= s->gic.priority1[irq++][0] << 8;
    203         val |= s->gic.priority1[irq++][0] << 16;
    204         val |= s->gic.priority1[irq][0] << 24;
    205         return val;
    206198    case 0xd24: /* System Handler Status.  */
    207199        val = 0;
    208200        if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
    static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) 
    335327    case 0xd14: /* Configuration Control.  */
    336328        /* TODO: Implement control registers.  */
    337329        goto bad_reg;
    338     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
    339         {
    340             int irq;
    341             irq = offset - 0xd14;
    342             s->gic.priority1[irq++][0] = value & 0xff;
    343             s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
    344             s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
    345             s->gic.priority1[irq][0] = (value >> 24) & 0xff;
    346             gic_update(&s->gic);
    347         }
    348         break;
    349330    case 0xd24: /* System Handler Control.  */
    350331        /* TODO: Real hardware allows you to set/clear the active bits
    351332           under some circumstances.  We don't implement this.  */
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