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1 | /* |
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2 | * Copyright (c) 2017 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems/score/smpimpl.h> |
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16 | |
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17 | #include <arm/freescale/imx/imx_srcreg.h> |
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18 | #include <arm/freescale/imx/imx_gpcreg.h> |
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19 | |
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20 | #include <bsp/start.h> |
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21 | |
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22 | bool _CPU_SMP_Start_processor(uint32_t cpu_index) |
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23 | { |
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24 | bool started; |
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25 | |
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26 | if (cpu_index == 1) { |
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27 | volatile imx_src *src = (volatile imx_src *) 0x30390000; |
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28 | volatile imx_gpc *gpc = (volatile imx_gpc *) 0x303a0000; |
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29 | |
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30 | src->gpr3 = (uint32_t) _start; |
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31 | gpc->pgc_a7core0_ctrl |= IMX_GPC_PGC_CTRL_PCR; |
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32 | gpc->cpu_pgc_sw_pup_req |= IMX_GPC_CPU_PGC_CORE1_A7; |
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33 | |
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34 | while ((gpc->cpu_pgc_pup_status1 & IMX_GPC_CPU_PGC_CORE1_A7) != 0) { |
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35 | /* Wait */ |
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36 | } |
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37 | |
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38 | gpc->pgc_a7core0_ctrl &= ~IMX_GPC_PGC_CTRL_PCR; |
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39 | src->a7rcr1 |= IMX_SRC_A7RCR1_A7_CORE1_ENABLE; |
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40 | |
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41 | started = true; |
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42 | } else { |
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43 | started = false; |
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44 | } |
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45 | |
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46 | return started; |
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47 | } |
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