[6e27be70] | 1 | /* |
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| 2 | * By Yang Xi <hiyangxi@gmail.com>. |
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[89c3f84] | 3 | * Based upon CSB337 |
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[6e27be70] | 4 | * |
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| 5 | * The license and distribution terms for this file may be |
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| 6 | * found in the file LICENSE in this distribution or at |
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[c499856] | 7 | * http://www.rtems.org/license/LICENSE. |
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[6e27be70] | 8 | */ |
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| 9 | |
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[8d992be9] | 10 | #include <bsp/linker-symbols.h> |
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[32b8506] | 11 | |
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[6e27be70] | 12 | /* Some standard definitions...*/ |
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| 13 | .equ PSR_MODE_USR, 0x10 |
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| 14 | .equ PSR_MODE_FIQ, 0x11 |
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| 15 | .equ PSR_MODE_IRQ, 0x12 |
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| 16 | .equ PSR_MODE_SVC, 0x13 |
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| 17 | .equ PSR_MODE_ABT, 0x17 |
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| 18 | .equ PSR_MODE_UNDEF, 0x1B |
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| 19 | .equ PSR_MODE_SYS, 0x1F |
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| 20 | |
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| 21 | .equ PSR_I, 0x80 |
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| 22 | .equ PSR_F, 0x40 |
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| 23 | .equ PSR_T, 0x20 |
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| 24 | |
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| 25 | .text |
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| 26 | .globl _start |
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| 27 | _start: |
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[32b8506] | 28 | /* |
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[6e27be70] | 29 | * Since I don't plan to return to the bootloader, |
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| 30 | * I don't have to save the registers. |
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| 31 | * |
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[32b8506] | 32 | * I'll just set the CPSR for SVC mode, interrupts |
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[6e27be70] | 33 | * off, and ARM instructions. |
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| 34 | */ |
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| 35 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) |
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| 36 | msr cpsr, r0 |
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| 37 | |
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| 38 | |
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| 39 | /* zero the bss */ |
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[8d992be9] | 40 | ldr r1, =bsp_section_bss_end |
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| 41 | ldr r0, =bsp_section_bss_begin |
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[6e27be70] | 42 | |
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[32b8506] | 43 | _bss_init: |
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[6e27be70] | 44 | mov r2, #0 |
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| 45 | cmp r0, r1 |
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| 46 | strlot r2, [r0], #4 |
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[32b8506] | 47 | blo _bss_init /* loop while r0 < r1 */ |
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[6e27be70] | 48 | |
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| 49 | /* --- Initialize stack pointer registers */ |
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| 50 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 51 | mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ |
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| 52 | msr cpsr, r0 |
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[8d992be9] | 53 | ldr r1, =bsp_stack_irq_size |
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| 54 | ldr sp, =bsp_stack_irq_begin |
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[6e27be70] | 55 | add sp, sp, r1 |
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| 56 | |
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| 57 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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| 58 | mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ |
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| 59 | msr cpsr, r0 |
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[8d992be9] | 60 | ldr r1, =bsp_stack_fiq_size |
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| 61 | ldr sp, =bsp_stack_fiq_begin |
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[6e27be70] | 62 | add sp, sp, r1 |
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| 63 | |
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| 64 | /* Enter ABT mode and set up the ABT stack pointer */ |
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| 65 | mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ |
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| 66 | msr cpsr, r0 |
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[8d992be9] | 67 | ldr r1, =bsp_stack_abt_size |
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| 68 | ldr sp, =bsp_stack_abt_begin |
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[6e27be70] | 69 | add sp, sp, r1 |
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[32b8506] | 70 | |
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[6e27be70] | 71 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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| 72 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ |
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| 73 | msr cpsr, r0 |
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[8d992be9] | 74 | ldr r1, =bsp_stack_und_size |
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| 75 | ldr sp, =bsp_stack_und_begin |
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[6e27be70] | 76 | add sp, sp, r1 |
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[32b8506] | 77 | sub sp, sp, #0x64 |
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[6e27be70] | 78 | |
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[32b8506] | 79 | /* |
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[6e27be70] | 80 | * Initialize the MMU. After we return, the MMU is enabled, |
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| 81 | * and memory may be remapped. I hope we don't remap this |
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| 82 | * memory away. |
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| 83 | */ |
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| 84 | |
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| 85 | ldr r0, =mem_map |
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| 86 | bl mmu_init |
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| 87 | |
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| 88 | |
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| 89 | |
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[32b8506] | 90 | /* |
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[6e27be70] | 91 | * Initialize the exception vectors. This includes the |
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[32b8506] | 92 | * exceptions vectors (0x00000000-0x0000001c), and the |
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[6e27be70] | 93 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 94 | */ |
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| 95 | mov r0, #0 |
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| 96 | adr r1, vector_block |
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| 97 | ldmia r1!, {r2-r9} |
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| 98 | stmia r0!, {r2-r9} |
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| 99 | ldmia r1!, {r2-r9} |
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| 100 | stmia r0!, {r2-r9} |
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| 101 | |
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| 102 | |
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| 103 | |
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| 104 | /* Now we are prepared to start the BSP's C code */ |
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[de237f4] | 105 | mov r0, #0 |
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[6e27be70] | 106 | bl boot_card |
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| 107 | |
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[32b8506] | 108 | /* |
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[6e27be70] | 109 | * Theoretically, we could return to what started us up, |
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| 110 | * but we'd have to have saved the registers and stacks. |
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| 111 | * Instead, we'll just reset. |
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| 112 | */ |
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| 113 | bl bsp_reset |
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| 114 | |
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| 115 | /* We shouldn't get here. If we do, hang */ |
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| 116 | _hang: b _hang |
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| 117 | |
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[32b8506] | 118 | |
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| 119 | /* |
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[6e27be70] | 120 | * This is the exception vector table and the pointers to |
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| 121 | * the functions that handle the exceptions. It's a total |
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| 122 | * of 16 words (64 bytes) |
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| 123 | */ |
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[32b8506] | 124 | vector_block: |
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[2433a8ab] | 125 | ldr pc, handler_addr_reset |
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| 126 | ldr pc, handler_addr_undef |
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| 127 | ldr pc, handler_addr_swi |
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| 128 | ldr pc, handler_addr_prefetch |
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| 129 | ldr pc, handler_addr_abort |
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[6e27be70] | 130 | nop |
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[2433a8ab] | 131 | ldr pc, handler_addr_irq |
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| 132 | ldr pc, handler_addr_fiq |
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| 133 | |
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| 134 | handler_addr_reset: |
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| 135 | .word bsp_reset |
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| 136 | |
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| 137 | handler_addr_undef: |
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| 138 | .word _ARMV4_Exception_undef_default |
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| 139 | |
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| 140 | handler_addr_swi: |
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| 141 | .word _ARMV4_Exception_swi_default |
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| 142 | |
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| 143 | handler_addr_prefetch: |
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| 144 | .word _ARMV4_Exception_pref_abort_default |
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| 145 | |
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| 146 | handler_addr_abort: |
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| 147 | .word _ARMV4_Exception_data_abort_default |
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| 148 | |
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| 149 | handler_addr_reserved: |
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| 150 | .word _ARMV4_Exception_reserved_default |
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| 151 | |
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| 152 | handler_addr_irq: |
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| 153 | .word _ARMV4_Exception_interrupt |
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| 154 | |
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| 155 | handler_addr_fiq: |
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| 156 | .word _ARMV4_Exception_fiq_default |
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