source: rtems/c/src/lib/libbsp/arm/gp32/startup/memmap.c @ e8c785c6

4.104.114.84.95
Last change on this file since e8c785c6 was e8c785c6, checked in by Jay Monkman <jtm@…>, on Mar 11, 2005 at 7:27:56 AM

2005-03-11 Philippe Simons <loki_666@…>

  • acinclude.m4: Added gp32 BSP.
  • gp32/.cvsignore, gp32/Makefile.am, gp32/README, gp32/bsp_specs, gp32/configure.ac, gp32/console/.cvsignore, gp32/console/conio.c, gp32/console/console.c, gp32/console/defaultfont.c, gp32/include/.cvsignore, gp32/include/bsp.h, gp32/include/conio.h, gp32/include/tm27.h, gp32/start/.cvsignore, gp32/start/start.S, gp32/startup/.cvsignore, gp32/startup/bspstart.c, gp32/startup/exit.c, gp32/startup/linkcmds, gp32/startup/memmap.c: New files.
  • Property mode set to 100644
File size: 1.0 KB
Line 
1/*
2 *  GP32 Memory Map
3 *
4 *  Copyright (c) 2004 by Cogent Computer Systems
5 *  Written by Jay Monkman <jtm@lopingdog.com>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14#include <rtems.h>
15#include <libcpu/mmu.h>
16
17/* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than
18 * that, you'll have TLB lookups, which could hurt performance.
19 */
20mmu_sect_map_t mem_map[] = {
21/*  <phys addr>  <virt addr> <size> <flags> */
22    {0x0c000000, 0x00000000,   1, MMU_CACHE_NONE},     /* SDRAM for vectors */
23    {0x0c000000, 0x0c000000,   7, MMU_CACHE_WTHROUGH}, /* SDRAM W cache */
24    {0x0c700000, 0x0c700000,   1, MMU_CACHE_NONE},     /* SDRAM W/O cache */
25    {0x14000000, 0x14000000,   16, MMU_CACHE_NONE},    /* Internals Regs - */
26    {0x15000000, 0x15000000,   16, MMU_CACHE_NONE},    /* Internal Regs - */
27    {0x00000000, 0x00000000,   0,    0}                /* The end */
28};
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