source: rtems/c/src/lib/libbsp/arm/gp32/startup/linkcmds @ 0afac6a

4.115
Last change on this file since 0afac6a was cbc433c7, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2014 at 7:40:20 AM

bsps/arm: Add .nocache section

This section can be use to provide a cache coherent memory area via
rtems_cache_coherent_add_area().

  • Property mode set to 100644
File size: 857 bytes
RevLine 
[e8c785c6]1MEMORY {
[dfee787]2        SDRAM_MMU : ORIGIN = 0x0c000000, LENGTH = 16k
3        SDRAM : ORIGIN = 0x0c004000, LENGTH = 7M - 16k
[e8c785c6]4}
5
[dfee787]6REGION_ALIAS ("REGION_START", SDRAM);
7REGION_ALIAS ("REGION_VECTOR", SDRAM);
8REGION_ALIAS ("REGION_TEXT", SDRAM);
9REGION_ALIAS ("REGION_TEXT_LOAD", SDRAM);
10REGION_ALIAS ("REGION_RODATA", SDRAM);
11REGION_ALIAS ("REGION_RODATA_LOAD", SDRAM);
12REGION_ALIAS ("REGION_DATA", SDRAM);
13REGION_ALIAS ("REGION_DATA_LOAD", SDRAM);
14REGION_ALIAS ("REGION_FAST_TEXT", SDRAM);
15REGION_ALIAS ("REGION_FAST_TEXT_LOAD", SDRAM);
16REGION_ALIAS ("REGION_FAST_DATA", SDRAM);
17REGION_ALIAS ("REGION_FAST_DATA_LOAD", SDRAM);
18REGION_ALIAS ("REGION_BSS", SDRAM);
19REGION_ALIAS ("REGION_WORK", SDRAM);
20REGION_ALIAS ("REGION_STACK", SDRAM);
[cbc433c7]21REGION_ALIAS ("REGION_NOCACHE", SDRAM);
22REGION_ALIAS ("REGION_NOCACHE_LOAD", SDRAM);
[dfee787]23
24_ttbl_base = ORIGIN (SDRAM_MMU);
25
26INCLUDE linkcmds.armv4
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