[e8c785c6] | 1 | /* |
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| 2 | * GP32 startup code |
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[183af89] | 3 | */ |
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| 4 | |
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| 5 | /* |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * http://www.rtems.com/license/LICENSE. |
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[e8c785c6] | 9 | */ |
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| 10 | |
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[dfee787] | 11 | #include <bsp/linker-symbols.h> |
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| 12 | |
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[e8c785c6] | 13 | /* Some standard definitions...*/ |
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| 14 | .equ PSR_MODE_USR, 0x10 |
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| 15 | .equ PSR_MODE_FIQ, 0x11 |
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| 16 | .equ PSR_MODE_IRQ, 0x12 |
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| 17 | .equ PSR_MODE_SVC, 0x13 |
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| 18 | .equ PSR_MODE_ABT, 0x17 |
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| 19 | .equ PSR_MODE_UNDEF, 0x1B |
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| 20 | .equ PSR_MODE_SYS, 0x1F |
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| 21 | |
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| 22 | .equ PSR_I, 0x80 |
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| 23 | .equ PSR_F, 0x40 |
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| 24 | .equ PSR_T, 0x20 |
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| 25 | |
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| 26 | .text |
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| 27 | .globl _start |
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| 28 | _start: |
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| 29 | b _start2 |
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| 30 | |
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| 31 | @--------------------------------------------------------------------------------- |
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| 32 | @ AXF addresses |
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| 33 | @--------------------------------------------------------------------------------- |
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[dfee787] | 34 | .word bsp_section_text_begin |
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| 35 | .word bsp_section_rodata_end |
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| 36 | .word bsp_section_data_begin |
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| 37 | .word bsp_section_bss_end |
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| 38 | .word bsp_section_bss_begin |
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| 39 | .word bsp_section_bss_end |
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[e8c785c6] | 40 | |
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| 41 | @--------------------------------------------------------------------------------- |
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| 42 | @ GamePark magic sequence |
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| 43 | @--------------------------------------------------------------------------------- |
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| 44 | .word 0x44450011 |
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| 45 | .word 0x44450011 |
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| 46 | .word 0x01234567 |
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| 47 | .word 0x12345678 |
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| 48 | .word 0x23456789 |
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| 49 | .word 0x34567890 |
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| 50 | .word 0x45678901 |
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| 51 | .word 0x56789012 |
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| 52 | .word 0x23456789 |
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| 53 | .word 0x34567890 |
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| 54 | .word 0x45678901 |
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| 55 | .word 0x56789012 |
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| 56 | .word 0x23456789 |
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| 57 | .word 0x34567890 |
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| 58 | .word 0x45678901 |
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| 59 | .word 0x56789012 |
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| 60 | |
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| 61 | @--------------------------------------------------------------------------------- |
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| 62 | _start2: |
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| 63 | @--------------------------------------------------------------------------------- |
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| 64 | |
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[32b8506] | 65 | /* |
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[e8c785c6] | 66 | * Since I don't plan to return to the bootloader, |
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| 67 | * I don't have to save the registers. |
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| 68 | * |
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[32b8506] | 69 | * I'll just set the CPSR for SVC mode, interrupts |
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[e8c785c6] | 70 | * off, and ARM instructions. |
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| 71 | */ |
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| 72 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) |
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| 73 | msr cpsr, r0 |
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[32b8506] | 74 | |
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[e8c785c6] | 75 | /* --- Initialize stack pointer registers */ |
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| 76 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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| 77 | mov r0, #(PSR_MODE_IRQ | PSR_I | PSR_F) /* No interrupts */ |
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| 78 | msr cpsr, r0 |
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[dfee787] | 79 | ldr r1, =bsp_stack_irq_size |
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| 80 | ldr sp, =bsp_stack_irq_begin |
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[e8c785c6] | 81 | add sp, sp, r1 |
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| 82 | |
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| 83 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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| 84 | mov r0, #(PSR_MODE_FIQ | PSR_I | PSR_F) /* No interrupts */ |
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| 85 | msr cpsr, r0 |
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[dfee787] | 86 | ldr r1, =bsp_stack_fiq_size |
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| 87 | ldr sp, =bsp_stack_fiq_begin |
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[e8c785c6] | 88 | add sp, sp, r1 |
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| 89 | |
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| 90 | /* Enter ABT mode and set up the ABT stack pointer */ |
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| 91 | mov r0, #(PSR_MODE_ABT | PSR_I | PSR_F) /* No interrupts */ |
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| 92 | msr cpsr, r0 |
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[dfee787] | 93 | ldr r1, =bsp_stack_abt_size |
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| 94 | ldr sp, =bsp_stack_abt_begin |
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[e8c785c6] | 95 | add sp, sp, r1 |
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[32b8506] | 96 | |
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[e8c785c6] | 97 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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| 98 | mov r0, #(PSR_MODE_SVC | PSR_I | PSR_F) /* No interrupts */ |
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| 99 | msr cpsr, r0 |
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[dfee787] | 100 | ldr r1, =bsp_stack_svc_size |
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| 101 | ldr sp, =bsp_stack_svc_begin |
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[e8c785c6] | 102 | add sp, sp, r1 |
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| 103 | sub sp, sp, #0x64 |
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[32b8506] | 104 | |
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[e8c785c6] | 105 | |
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| 106 | /* disable mmu, I and D caches*/ |
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| 107 | nop |
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| 108 | nop |
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| 109 | mrc p15, 0, r0, c1, c0, 0 |
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| 110 | bic r0, r0, #0x01 |
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| 111 | bic r0, r0, #0x04 |
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| 112 | bic r0, r0, #0x01000 |
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| 113 | mcr p15, 0, r0, c1, c0, 0 |
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| 114 | nop |
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| 115 | nop |
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| 116 | |
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| 117 | /* clean data cache */ |
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| 118 | mov r1,#0x00 |
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| 119 | Loop1: |
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| 120 | mov r2,#0x00 |
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[32b8506] | 121 | Loop2: |
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[e8c785c6] | 122 | mov r3, r2, lsl#26 |
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| 123 | orr r3, r3, r1, lsl#5 |
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| 124 | mcr p15, 0, r3, c7, c14, 2 |
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| 125 | add r2, r2, #0x01 |
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| 126 | cmp r2, #64 |
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| 127 | bne Loop2 |
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| 128 | add r1, r1, #0x01 |
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| 129 | cmp r1, #8 |
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| 130 | bne Loop1 |
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| 131 | |
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[32b8506] | 132 | |
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| 133 | /* |
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[e8c785c6] | 134 | * Initialize the MMU. After we return, the MMU is enabled, |
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| 135 | * and memory may be remapped. I hope we don't remap this |
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| 136 | * memory away. |
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| 137 | */ |
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| 138 | ldr r0, =mem_map |
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[32b8506] | 139 | bl mmu_init |
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[e8c785c6] | 140 | |
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[32b8506] | 141 | /* |
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[e8c785c6] | 142 | * Initialize the exception vectors. This includes the |
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[32b8506] | 143 | * exceptions vectors (0x00000000-0x0000001c), and the |
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[e8c785c6] | 144 | * pointers to the exception handlers (0x00000020-0x0000003c). |
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| 145 | */ |
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| 146 | mov r0, #0 |
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| 147 | adr r1, vector_block |
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| 148 | ldmia r1!, {r2-r9} |
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| 149 | stmia r0!, {r2-r9} |
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| 150 | ldmia r1!, {r2-r9} |
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| 151 | stmia r0!, {r2-r9} |
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[32b8506] | 152 | |
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[e8c785c6] | 153 | /* Now we are prepared to start the BSP's C code */ |
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[de237f4] | 154 | mov r0, #0 |
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[e8c785c6] | 155 | bl boot_card |
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| 156 | |
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[32b8506] | 157 | /* |
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[e8c785c6] | 158 | * Theoretically, we could return to what started us up, |
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| 159 | * but we'd have to have saved the registers and stacks. |
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| 160 | * Instead, we'll just reset. |
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| 161 | */ |
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| 162 | bl bsp_reset |
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| 163 | |
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| 164 | /* We shouldn't get here. If we do, hang */ |
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| 165 | _hang: b _hang |
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| 166 | |
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[32b8506] | 167 | |
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| 168 | /* |
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[e8c785c6] | 169 | * This is the exception vector table and the pointers to |
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| 170 | * the functions that handle the exceptions. It's a total |
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| 171 | * of 16 words (64 bytes) |
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| 172 | */ |
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[32b8506] | 173 | vector_block: |
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[e8c785c6] | 174 | ldr pc, Reset_Handler |
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| 175 | ldr pc, Undefined_Handler |
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| 176 | ldr pc, SWI_Handler |
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| 177 | ldr pc, Prefetch_Handler |
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| 178 | ldr pc, Abort_Handler |
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| 179 | nop |
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| 180 | ldr pc, IRQ_Handler |
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| 181 | ldr pc, FIQ_Handler |
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| 182 | |
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| 183 | Reset_Handler: b bsp_reset |
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| 184 | Undefined_Handler: b Undefined_Handler |
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[32b8506] | 185 | SWI_Handler: b SWI_Handler |
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[e8c785c6] | 186 | Prefetch_Handler: b Prefetch_Handler |
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| 187 | Abort_Handler: b Abort_Handler |
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| 188 | nop |
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| 189 | IRQ_Handler: b IRQ_Handler |
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| 190 | FIQ_Handler: b FIQ_Handler |
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| 191 | |
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| 192 | .globl Reset_Handler |
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| 193 | .globl Undefined_Handler |
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| 194 | .globl SWI_Handler |
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| 195 | .globl Prefetch_Handler |
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| 196 | .globl Abort_Handler |
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| 197 | .globl IRQ_Handler |
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| 198 | .globl FIQ_Handler |
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