source: rtems/c/src/lib/libbsp/arm/gp32/include/bsp.h @ 5ae1cae

4.104.115
Last change on this file since 5ae1cae was 5ae1cae, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 30, 2010 at 2:30:09 PM

2010-04-30 Sebastian Huber <sebastian.huber@…>

  • Makefile.am, preinstall.am: Added generic interrupt support modules.
  • include/bsp.h: Define BSP_FEATURE_IRQ_EXTENSION.
  • startup/bspstart.c: Interrupt support changes.
  • Property mode set to 100644
File size: 1.9 KB
Line 
1/*-------------------------------------------------------------------------+
2| bsp.h - ARM BSP
3+--------------------------------------------------------------------------+
4| This include file contains definitions related to the ARM BSP.
5+--------------------------------------------------------------------------+
6|
7| Copyright (c) Canon Research France SA.]
8| Emmanuel Raguet, mailto:raguet@crf.canon.fr
9|
10|  The license and distribution terms for this file may be
11|  found in found in the file LICENSE in this distribution or at
12|  http://www.rtems.com/license/LICENSE.
13|
14|  $Id$
15+--------------------------------------------------------------------------*/
16
17
18#ifndef _BSP_H
19#define _BSP_H
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25#include <bspopts.h>
26
27#include <rtems.h>
28#include <rtems/iosupp.h>
29#include <rtems/console.h>
30#include <rtems/clockdrv.h>
31#include <s3c24xx.h>
32
33#define BSP_FEATURE_IRQ_EXTENSION
34
35#define gp32_initButtons() {rPBCON=0x0;}
36#define gp32_getButtons() \
37    ( (((~rPEDAT >> 6) & 0x3 )<<8) | (((~rPBDAT >> 8) & 0xFF)<<0) )
38
39/*functions to get the differents s3c2400 clks*/
40uint32_t get_FCLK(void);
41uint32_t get_HCLK(void);
42uint32_t get_PCLK(void);
43uint32_t get_UCLK(void);
44
45
46void gp32_setPalette( unsigned char pos, uint16_t color);
47
48/* What is the input clock freq in hertz? */
49#define BSP_OSC_FREQ  12000000    /* 12 MHz oscillator */
50#define M_MDIV 81       /* FCLK=133Mhz */
51#define M_PDIV 2
52#define M_SDIV 1
53#define M_CLKDIVN 2     /* HCLK=FCLK/2, PCLK=FCLK/2 */
54
55#define REFEN   0x1     /* enable refresh */
56#define TREFMD  0x0     /* CBR(CAS before RAS)/auto refresh */
57#define Trp     0x0     /* 2 clk */
58#define Trc     0x3     /* 7 clk */
59#define Tchr    0x2     /* 3 clk */
60
61
62/*
63 *  This BSP provides its own IDLE task to override the RTEMS one.
64 *  So we prototype it and define the constant confdefs.h expects
65 *  to configure a BSP specific one.
66 */
67Thread bsp_idle_task(uint32_t);
68
69#define BSP_IDLE_TASK_BODY bsp_idle_task
70
71#ifdef __cplusplus
72}
73#endif
74
75#endif /* _BSP_H */
76
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