[e8c785c6] | 1 | /*-------------------------------------------------------------------------+ |
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[32b8506] | 2 | | bsp.h - ARM BSP |
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[e8c785c6] | 3 | +--------------------------------------------------------------------------+ |
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| 4 | | This include file contains definitions related to the ARM BSP. |
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| 5 | +--------------------------------------------------------------------------+ |
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| 6 | | |
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| 7 | | Copyright (c) Canon Research France SA.] |
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| 8 | | Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 9 | | |
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| 10 | | The license and distribution terms for this file may be |
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| 11 | | found in found in the file LICENSE in this distribution or at |
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| 12 | | http://www.rtems.com/license/LICENSE. |
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[32b8506] | 13 | | |
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[e8c785c6] | 14 | | $Id$ |
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| 15 | +--------------------------------------------------------------------------*/ |
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| 16 | |
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| 17 | |
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[34c4852] | 18 | #ifndef _BSP_H |
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| 19 | #define _BSP_H |
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[e8c785c6] | 20 | |
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| 21 | #ifdef __cplusplus |
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| 22 | extern "C" { |
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| 23 | #endif |
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| 24 | |
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| 25 | #include <bspopts.h> |
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| 26 | |
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| 27 | #include <rtems.h> |
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| 28 | #include <rtems/iosupp.h> |
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| 29 | #include <rtems/console.h> |
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| 30 | #include <rtems/clockdrv.h> |
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[0542a23] | 31 | #include <s3c24xx.h> |
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[e8c785c6] | 32 | |
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[5ae1cae] | 33 | #define BSP_FEATURE_IRQ_EXTENSION |
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| 34 | |
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[32cf23b1] | 35 | #define gp32_initButtons() {rPBCON=0x0;} |
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[4130d8e2] | 36 | #define gp32_getButtons() \ |
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| 37 | ( (((~rPEDAT >> 6) & 0x3 )<<8) | (((~rPBDAT >> 8) & 0xFF)<<0) ) |
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[32cf23b1] | 38 | |
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| 39 | /*functions to get the differents s3c2400 clks*/ |
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| 40 | uint32_t get_FCLK(void); |
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| 41 | uint32_t get_HCLK(void); |
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| 42 | uint32_t get_PCLK(void); |
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| 43 | uint32_t get_UCLK(void); |
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| 44 | |
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| 45 | |
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| 46 | void gp32_setPalette( unsigned char pos, uint16_t color); |
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[e8c785c6] | 47 | |
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| 48 | /* What is the input clock freq in hertz? */ |
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| 49 | #define BSP_OSC_FREQ 12000000 /* 12 MHz oscillator */ |
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[32cf23b1] | 50 | #define M_MDIV 81 /* FCLK=133Mhz */ |
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[e8c785c6] | 51 | #define M_PDIV 2 |
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| 52 | #define M_SDIV 1 |
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[32cf23b1] | 53 | #define M_CLKDIVN 2 /* HCLK=FCLK/2, PCLK=FCLK/2 */ |
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| 54 | |
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| 55 | #define REFEN 0x1 /* enable refresh */ |
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| 56 | #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ |
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| 57 | #define Trp 0x0 /* 2 clk */ |
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| 58 | #define Trc 0x3 /* 7 clk */ |
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| 59 | #define Tchr 0x2 /* 3 clk */ |
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| 60 | |
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[e8c785c6] | 61 | |
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[b5e7018] | 62 | /* |
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| 63 | * This BSP provides its own IDLE task to override the RTEMS one. |
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| 64 | * So we prototype it and define the constant confdefs.h expects |
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| 65 | * to configure a BSP specific one. |
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| 66 | */ |
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[6710d81] | 67 | Thread bsp_idle_task(uint32_t); |
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[b5e7018] | 68 | |
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| 69 | #define BSP_IDLE_TASK_BODY bsp_idle_task |
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| 70 | |
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[e8c785c6] | 71 | #ifdef __cplusplus |
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| 72 | } |
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| 73 | #endif |
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| 74 | |
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[34c4852] | 75 | #endif /* _BSP_H */ |
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[e8c785c6] | 76 | |
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