1 | /** |
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2 | * @file irq_asm.S |
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3 | * |
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4 | * This file contains the implementation of the IRQ handler. |
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5 | */ |
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6 | /* |
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7 | * RTEMS GBA BSP |
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8 | * |
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9 | * Copyright (c) 2002 Advent Networks, Inc. |
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10 | * Jay Monkman <jmonkman@adventnetworks.com> |
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11 | * |
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12 | * Copyright (C) 2000 Canon Research France SA. |
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13 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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14 | * |
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15 | * Modified Andy Dachs <a.dachs@sstl.co.uk> |
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16 | * Copyright (c) 2001 Surrey Satellite Technolgy Limited |
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17 | * |
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18 | * Modified Markku Puro <markku.puro@kopteri.net> |
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19 | * Copyright (c) 2004 |
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20 | * |
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21 | * The license and distribution terms for this file may be |
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22 | * found in found in the file LICENSE in this distribution or at |
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23 | * http://www.rtems.com/license/LICENSE. |
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24 | * |
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25 | * $Id$ |
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26 | */ |
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27 | |
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28 | #define __asm__ |
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29 | #include <rtems/asm.h> |
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30 | #include <asm_macros.h> |
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31 | #include <arm_mode_bits.h> |
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32 | /* @cond INCLUDE_ASM */ |
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33 | |
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34 | /** |
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35 | * Interrupt handler |
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36 | * function void _ISR_Handler(void) |
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37 | * |
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38 | */ |
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39 | .align |
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40 | /* .section .iwram */ |
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41 | |
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42 | PUBLIC_ARM_FUNCTION(_ISR_Handler) |
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43 | stmdb sp!, {r0, r1, r2, r3, r12} /* save regs on INT stack */ |
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44 | stmdb sp!, {lr} /* now safe to call C funcs */ |
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45 | |
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46 | |
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47 | /* one nest level deeper */ |
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48 | ldr r0, =_ISR_Nest_level |
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49 | ldr r1, [r0] |
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50 | add r1, r1,#1 |
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51 | str r1, [r0] |
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52 | |
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53 | /* disable multitasking */ |
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54 | ldr r0, =_Thread_Dispatch_disable_level |
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55 | ldr r1, [r0] |
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56 | add r1, r1,#1 |
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57 | str r1, [r0] |
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58 | |
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59 | /* BSP specific function to INT handler */ |
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60 | bl ExecuteITHandler |
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61 | |
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62 | /* one less nest level */ |
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63 | ldr r0, =_ISR_Nest_level |
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64 | ldr r1, [r0] |
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65 | sub r1, r1,#1 |
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66 | str r1, [r0] |
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67 | |
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68 | /* unnest multitasking */ |
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69 | ldr r0, =_Thread_Dispatch_disable_level |
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70 | ldr r1, [r0] |
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71 | sub r1, r1,#1 |
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72 | str r1, [r0] |
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73 | |
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74 | /* check to see if we interrupted (no FIQ in GBA) */ |
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75 | mrs r0, spsr |
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76 | and r0, r0, #Mode_Bits |
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77 | cmp r0, #Mode_IRQ /* is it INT mode? */ |
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78 | beq exitit |
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79 | |
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80 | /* If thread dispatching is disabled, exit */ |
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81 | cmp r1, #0 |
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82 | bne exitit |
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83 | |
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84 | /* If a task switch is necessary, call scheduler */ |
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85 | ldr r0, =_Context_Switch_necessary |
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86 | ldrb r1, [r0] |
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87 | cmp r1, #0 |
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88 | |
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89 | /* since bframe is going to clear _ISR_Signals_to_thread_executing, */ |
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90 | /* we need to load it here */ |
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91 | ldr r0, =_ISR_Signals_to_thread_executing |
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92 | ldrb r1, [r0] |
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93 | bne bframe |
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94 | |
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95 | /* If a signals to be sent (_ISR_Signals_to_thread_executing != 0), */ |
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96 | /* call scheduler */ |
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97 | cmp r1, #0 |
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98 | beq exitit |
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99 | |
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100 | /* _ISR_Signals_to_thread_executing = FALSE */ |
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101 | mov r1, #0 |
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102 | strb r1, [r0] |
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103 | |
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104 | bframe: |
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105 | /* Now we need to set up the return from this ISR to be _ISR_Dispatch */ |
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106 | /* To do that, we need to save the current lr_int and spsr_int on the */ |
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107 | /* SVC stack */ |
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108 | mrs r0, spsr |
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109 | ldmia sp!, {r1} /* get lr off stack */ |
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110 | stmdb sp!, {r1} |
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111 | mrs r2, cpsr |
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112 | bic r3, r2, #Mode_Bits |
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113 | orr r3, r3, #ModePriv /* change to SVC mode */ |
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114 | msr cpsr_c, r3 |
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115 | |
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116 | /* now in SVC mode */ |
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117 | stmdb sp!, {r0, r1} /* put spsr_int and lr_int on SVC stack */ |
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118 | msr cpsr_c, r2 /* change back to INT mode */ |
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119 | |
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120 | /* now in INT mode */ |
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121 | |
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122 | /* replace lr with address of _ISR_Dispatch */ |
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123 | ldr lr, =_ISR_Dispatch_p_4 /* On entry to an ISR, the lr is */ |
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124 | /* the return address + 4, so */ |
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125 | /* we have to emulate that */ |
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126 | ldmia sp!, {r1} /* out with the old */ |
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127 | stmdb sp!, {lr} /* in with the new (lr) */ |
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128 | |
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129 | |
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130 | orr r0, r0, #Int_Bits |
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131 | msr spsr, r0 |
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132 | |
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133 | exitit: |
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134 | ldmia sp!, {lr} /* restore regs from INT stack */ |
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135 | ldmia sp!, {r0, r1, r2, r3, r12} /* restore regs from INT stack */ |
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136 | subs pc, lr , #4 /* return */ |
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137 | LABEL_END(_ISR_Handler) |
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138 | |
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139 | /* on entry to _ISR_Dispatch, we're in SVC mode */ |
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140 | PUBLIC_ARM_FUNCTION(_ISR_Dispatch) |
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141 | stmdb sp!, {r0-r3, r12,lr} /* save regs on SVC stack */ |
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142 | /* (now safe to call C funcs) */ |
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143 | /* we don't save lr, since */ |
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144 | /* it's just going to get */ |
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145 | /* overwritten */ |
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146 | _ISR_Dispatch_p_4: |
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147 | bl _Thread_Dispatch |
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148 | ldmia sp!, {r0-r3, r12, lr} |
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149 | |
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150 | stmdb sp!, {r0-r2} |
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151 | /* Now we have to screw with the stack */ |
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152 | mov r0, sp /* copy the SVC stack pointer */ |
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153 | |
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154 | mrs r1, cpsr |
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155 | bic r2, r1, #Mode_Bits /* clear mode bits */ |
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156 | orr r2, r2, #(Mode_IRQ | Int_Bits) /* change to INT mode */ |
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157 | msr cpsr_c, r2 /* disable interrupts */ |
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158 | |
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159 | /* now in INT mode */ |
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160 | stmdb sp!, {r4, r5, r6} /* save temp vars on INT stack */ |
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161 | ldmia r0!, {r4, r5, r6} /* Get r0-r3 from SVC stack */ |
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162 | stmdb sp!, {r4, r5, r6} /* and save them on INT stack */ |
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163 | |
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164 | ldmia r0!, {r4, r5} /* get saved values from SVC stack */ |
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165 | /* r4=spsr, r5=lr */ |
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166 | mov lr, r5 /* restore lr_int */ |
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167 | msr spsr, r4 /* restore spsr_int */ |
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168 | |
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169 | /* switch to SVC mode, update sp, then return to INT mode */ |
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170 | msr cpsr_c, r1 /* switch to SVC mode */ |
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171 | mov sp, r0 /* update sp_svc */ |
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172 | msr cpsr_c, r2 /* switch back to INT mode */ |
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173 | |
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174 | /* pop all the registers from the stack */ |
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175 | ldmia sp!, {r0, r1, r2} |
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176 | ldmia sp!, {r4, r5, r6} |
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177 | |
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178 | /* Finally, we can return to the interrupted task */ |
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179 | subs pc, lr, #4 |
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180 | |
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181 | LABEL_END(_ISR_Dispatch) |
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182 | /* @endcond */ |
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183 | |
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