source: rtems/c/src/lib/libbsp/arm/gba/include/gba_registers.h @ 3c7ed6b

4.104.114.84.9
Last change on this file since 3c7ed6b was 3c7ed6b, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 6, 2005 at 6:46:04 PM

2005-07-06 Markku Puro <markku.puro@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, clock/clockdrv.c, console/conio.c, console/console.c, console/defaultfont.c, include/arm_mode_bits.h, include/asm_macros.h, include/bsp.h, include/bspopts.h.in, include/conio.h, include/gba.h, include/gba_registers.h, include/tm27.h, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, start/logo.S, start/start.S, startup/bspstart.c, startup/cpu.c, startup/cpu_asm.S, startup/exit.c, startup/linkcmds, timer/timer.c: New files.
  • Property mode set to 100644
File size: 62.3 KB
Line 
1/**
2 *  @file gba_registers.h
3 *
4 *  Game Boy Advance registers.
5 *
6 *  This include file contains definitions related to the ARM BSP.
7 */
8/*
9 *  RTEMS GBA BSP
10 *
11 *  Copyright (c) 2004  Markku Puro <markku.puro@kopteri.net>
12 *
13 *  The license and distribution terms for this file may be
14 *  found in found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 *
17 *  $Id$
18 */
19
20/*---------------------------------------------------------------------------+
21| THIS CODE WAS NOT MADE IN ASSOCIATION WITH NINTENDO AND DOES NOT MAKE
22| USE OF ANY INTELLECTUAL PROPERTY CLAIMED BY NINTENDO.
23|
24| GAMEBOY ADVANCE IS A TRADEMARK OF NINTENDO.
25|
26| THIS CODE HAS BEEN PROVIDED "AS-IS" WITHOUT A WARRANTY OF ANY KIND,
27| EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO IMPLIED
28| WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE.
29| THE ENTIRE RISK AS TO THE QUALITY OR PERFORMANCE OF THE CODE IS WITH YOU.
30|
31| IN NO EVENT, UNLESS AGREED TO IN WRITING, WILL ANY COPYRIGHT HOLDER,
32| OR ANY OTHER PARTY, BE HELD LIABLE FOR ANY DAMAGES RESULTING FROM
33| THE USE OR INABILITY TO USE THIS CODE.
34+----------------------------------------------------------------------------*/
35
36#ifndef _GBA_REGISTERS_H
37#define _GBA_REGISTERS_H
38
39#ifndef __asm__
40extern volatile unsigned int  *Regs;        /**< Chip registers              */
41#endif
42
43
44/*---------------------------------------------------------------------------+
45|    General address definitions
46+----------------------------------------------------------------------------*/
47/* General Internal Memory */
48#define GBA_BIOS_ADDR        0x00000000  /**< GBA BIOS start address         */
49#define GBA_BIOS_END         0x00004000  /**< GBA BIOS end address           */
50#define GBA_EXT_RAM_ADDR     0x02000000  /**< On-board RAM start address     */
51#define GBA_EXT_RAM_END      0x02040000  /**< On-board RAM end address       */
52#define GBA_INT_RAM_ADDR     0x03000000  /**< In-chip RAM start address      */
53#define GBA_INT_RAM_END      0x03008000  /**< In-chip RAM end address        */
54#define GBA_IO_REGS_ADDR     0x04000000  /**< IO registers start address     */
55#define GBA_IO_REGS_END      0x04000400  /**< IO registers end address       */
56/* Internal Display Memory */
57#define GBA_PAL_RAM_ADDR     0x05000000  /**< PAL RAM start address          */
58#define GBA_PAL_RAM_END      0x05000400  /**< PAL RAM end address            */
59#define GBA_VRAM_ADDR        0x06000000  /**< VRAM start address             */
60#define GBA_VRAM_END         0x06180000  /**< VRAM end address               */
61#define GBA_OAM_ADDR         0x07000000  /**< OAM start address              */
62#define GBA_OAM_END          0x07000400  /**< OAM end address                */
63/* External Memory (Game Pak) */
64#define GBA_ROM0_ADDR        0x08000000  /**< Card ROM0 start address        */
65#define GBA_ROM1_ADDR        0x0A000000  /**< Card ROM1 start address        */
66#define GBA_ROM2_ADDR        0x0C000000  /**< Card ROM2 start address        */
67#define GBA_SRAM_ADDR        0x0E000000  /**< Card SRAM start address        */
68#define GBA_SRAM_END         0x0E010000  /**< Card SRAM end address          */
69/* Unused Memory Area */
70#define GBA_MAX_ADDR         0x10000000  /**< Upper 4bits of address bus unused */
71/* Memory pointers */
72#ifndef __asm__
73#define GBA_BASE_BIOS       (volatile unsigned char *)GBA_BIOS_ADDR    /**< BIOS - System ROM 16KBytes, protected */
74#define GBA_BASE_EXT_RAM    (volatile unsigned char *)GBA_EXT_RAM_ADDR /**< WRAM - On-board Work RAM 256KBytes    */
75#define GBA_BASE_INT_RAM    (volatile unsigned char *)GBA_INT_RAM_ADDR /**< WRAM - In-chip Work RAM 32KBytes      */
76#define GBA_BASE_IO_REGS    (volatile unsigned char *)GBA_IO_REGS_ADDR /**< I/O Registers                         */
77#define GBA_BASE_PAL_RAM    (volatile unsigned char *)GBA_PAL_RAM_ADDR /**< BG/OBJ Palette RAM 1KBytes            */
78#define GBA_BASE_VRAM       (volatile unsigned char *)GBA_VRAM_ADDR    /**< VRAM - Video RAM 96KBytes             */
79#define GBA_BASE_OAM        (volatile unsigned char *)GBA_OAM_ADDR     /**< OAM - OBJ Attribytes                  */
80#define GBA_BASE_ROM0       (volatile unsigned char *)GBA_ROM0_ADDR    /**< Card ROM 32MB                         */
81#define GBA_BASE_ROM1       (volatile unsigned char *)GBA_ROM1_ADDR    /**< Card ROM 32MB                         */
82#define GBA_BASE_ROM2       (volatile unsigned char *)GBA_ROM2_ADDR    /**< Card ROM 32MB                         */
83#define GBA_BASE_SRAM       (volatile unsigned char *)GBA_SRAM_ADDR    /**< Card SRAM 64KBytes                    */
84#endif
85/*---------------------------------------------------------------------------*
86 *   Display Control
87 *---------------------------------------------------------------------------*/
88#define GBA_DISP_BG_MODE_MASK    0x0007      /**< BG Mode       */
89#define GBA_DISP_ON_MASK         0x1f00      /**< OBJ BG ON     */
90#define GBA_DISP_WIN_MASK        0x6000      /**< Window ON     */
91
92#define GBA_DISP_BG_MODE_SHIFT   0
93#define GBA_DISP_ON_SHIFT        8
94#define GBA_DISP_WIN_SHIFT       13
95
96#define GBA_DISP_MODE_0          0x0000      /**< BG Mode 0     */
97#define GBA_DISP_MODE_1          0x0001      /**< BG Mode 1     */
98#define GBA_DISP_MODE_2          0x0002      /**< BG Mode 2     */
99#define GBA_DISP_MODE_3          0x0003      /**< BG Mode 3     */
100#define GBA_DISP_MODE_4          0x0004      /**< BG Mode 4     */
101#define GBA_DISP_MODE_5          0x0005      /**< BG Mode 5     */
102#define GBA_DISP_BMP_FRAME_NO    0x0010      /**< Bitmap Mode Display Frame     */
103#define GBA_DISP_OBJ_HOFF        0x0020      /**< OBJ Processing in H Blank OFF */
104#define GBA_DISP_OBJ_CHAR_2D_MAP 0x0000      /**< OBJ Character Data 2D Mapping */
105#define GBA_DISP_OBJ_CHAR_1D_MAP 0x0040      /**< OBJ Character Data 1D Mapping */
106#define GBA_DISP_LCDC_OFF        0x0080      /**< LCDC OFF       */
107#define GBA_DISP_BG0_ON          0x0100      /**< BG0 ON         */
108#define GBA_DISP_BG1_ON          0x0200      /**< BG1 ON         */
109#define GBA_DISP_BG2_ON          0x0400      /**< BG2 ON         */
110#define GBA_DISP_BG3_ON          0x0800      /**< BG3 ON         */
111#define GBA_DISP_BG_ALL_ON       0x0f00      /**< All BG ON      */
112#define GBA_DISP_OBJ_ON          0x1000      /**< OBJ ON         */
113#define GBA_DISP_OBJ_BG_ALL_ON   0x1f00      /**< All OBJ/BG ON  */
114#define GBA_DISP_WIN0_ON         0x2000      /**< Window 0 ON    */
115#define GBA_DISP_WIN1_ON         0x4000      /**< Window 1 ON    */
116#define GBA_DISP_WIN01_ON        0x6000      /**< Window 0,1 ON  */
117#define GBA_DISP_OBJWIN_ON       0x8000      /**< OBJ Window ON  */
118#define GBA_DISP_WIN_ALL_ON      0xe000      /**< All Window ON  */
119#define GBA_DISP_ALL_ON          0x7f00      /**< All ON         */
120
121#define GBA_BG_MODE_0            0
122#define GBA_BG_MODE_1            1
123#define GBA_BG_MODE_2            2
124#define GBA_BG_MODE_3            3
125#define GBA_BG_MODE_4            4
126#define GBA_BG_MODE_5            5
127
128#define GBA_BG0_ENABLE           1
129#define GBA_BG1_ENABLE           2
130#define GBA_BG2_ENABLE           4
131#define GBA_BG3_ENABLE           8
132#define GBA_OBJ_ENABLE          16
133
134#define GBA_OBJ_1D_MAP           1
135#define GBA_OBJ_2D_MAP           0
136
137
138/*---------------------------------------------------------------------------+
139|    LCD
140+----------------------------------------------------------------------------*/
141/* LCD I/O Register address offsets */
142#define GBA_DISPCNT             0x00000000   /**< LCD Control                */
143#define GBA_DISPSTAT            0x00000004   /**< General LCD Status (STAT,LYC) */
144#define GBA_VCOUNT              0x00000006   /**< Vertical Counter (LY)      */
145#define GBA_BG0CNT              0x00000008   /**< BG0 Control                */
146#define GBA_BG1CNT              0x0000000A   /**< BG1 Control                */
147#define GBA_BG2CNT              0x0000000C   /**< BG2 Control                */
148#define GBA_BG3CNT              0x0000000E   /**< BG3 Control                */
149#define GBA_BG0HOFS             0x00000010   /**< BG0 X-Offset               */
150#define GBA_BG0VOFS             0x00000012   /**< BG0 Y-Offset               */
151#define GBA_BG1HOFS             0x00000014   /**< BG1 X-Offset               */
152#define GBA_BG1VOFS             0x00000016   /**< BG1 Y-Offset               */
153#define GBA_BG2HOFS             0x00000018   /**< BG2 X-Offset               */
154#define GBA_BG2VOFS             0x0000001A   /**< BG2 Y-Offset               */
155#define GBA_BG3HOFS             0x0000001C   /**< BG3 X-Offset               */
156#define GBA_BG3VOFS             0x0000001E   /**< BG3 Y-Offset               */
157#define GBA_BG2PA               0x00000020   /**< BG2 Rotation/Scaling Parameter A (dx)  */
158#define GBA_BG2PB               0x00000022   /**< BG2 Rotation/Scaling Parameter B (dmx) */
159#define GBA_BG2PC               0x00000024   /**< BG2 Rotation/Scaling Parameter C (dy)  */
160#define GBA_BG2PD               0x00000026   /**< BG2 Rotation/Scaling Parameter D (dmy) */
161#define GBA_BG2X                0x00000028   /**< BG2 Reference Point X-Coordinate       */
162#define GBA_BG2X_L              0x00000028   /**< BG2 Reference Point X-Coordinate low   */
163#define GBA_BG2X_H              0x0000002A   /**< BG2 Reference Point X-Coordinate high  */
164#define GBA_BG2Y                0x0000002C   /**< BG2 Reference Point Y-Coordinate       */
165#define GBA_BG2Y_L              0x0000002C   /**< BG2 Reference Point Y-Coordinate low   */
166#define GBA_BG2Y_H              0x0000002E   /**< BG2 Reference Point Y-Coordinate high  */
167#define GBA_BG3PA               0x00000030   /**< BG3 Rotation/Scaling Parameter A (dx)  */
168#define GBA_BG3PB               0x00000032   /**< BG3 Rotation/Scaling Parameter B (dmx) */
169#define GBA_BG3PC               0x00000034   /**< BG3 Rotation/Scaling Parameter C (dy)  */
170#define GBA_BG3PD               0x00000036   /**< BG3 Rotation/Scaling Parameter D (dmy) */
171#define GBA_BG3X                0x00000038   /**< BG3 Reference Point X-Coordinate       */
172#define GBA_BG3X_L              0x00000038   /**< BG3 Reference Point X-Coordinate low   */
173#define GBA_BG3X_H              0x0000003A   /**< BG3 Reference Point X-Coordinate high  */
174#define GBA_BG3Y                0x0000003C   /**< BG3 Reference Point Y-Coordinate       */
175#define GBA_BG3Y_L              0x0000003C   /**< BG3 Reference Point Y-Coordinate low   */
176#define GBA_BG3Y_H              0x0000003E   /**< BG3 Reference Point Y-Coordinate hugh  */
177#define GBA_WIN0H               0x00000040   /**< Window 0 Horizontal Dimensions         */
178#define GBA_WIN1H               0x00000042   /**< Window 1 Horizontal Dimensions         */
179#define GBA_WIN0V               0x00000044   /**< Window 0 Vertical Dimensions           */
180#define GBA_WIN1V               0x00000046   /**< Window 1 Vertical Dimensions           */
181#define GBA_WININ               0x00000048   /**< Control Inside of Window(s)            */
182#define GBA_WINOUT              0x0000004A   /**< Control Outside of Windows & Inside of OBJ Window */
183#define GBA_MOSAIC              0x0000004C   /**< Mosaic Size                            */
184#define GBA_BLDCNT              0x00000050   /**< Color Special Effects Selection        */
185#define GBA_BLDMOD              0x00000050   /**< Color Special Effects Selection       X*/
186#define GBA_BLDALPHA            0x00000052   /**< Alpha Blending Coefficients            */
187#define GBA_COLEV               0x00000052   /**< Alpha Blending Coefficients           X*/
188#define GBA_BLDY                0x00000054   /**< Brightness (Fade-In/Out) Coefficient   */
189#define GBA_COLY                0x00000054   /**< Brightness (Fade-In/Out) Coefficient  X*/
190/* LCD I/O Register addresses */
191#define GBA_REG_DISPCNT_ADDR    GBA_IO_REGS_ADDR + GBA_DISPCNT
192#define GBA_REG_DISPSTAT_ADDR   GBA_IO_REGS_ADDR + GBA_DISPSTAT
193#define GBA_REG_VCOUNT_ADDR     GBA_IO_REGS_ADDR + GBA_VCOUNT
194#define GBA_REG_BG0CNT_ADDR     GBA_IO_REGS_ADDR + GBA_BG0CNT
195#define GBA_REG_BG1CNT_ADDR     GBA_IO_REGS_ADDR + GBA_BG1CNT
196#define GBA_REG_BG2CNT_ADDR     GBA_IO_REGS_ADDR + GBA_BG2CNT
197#define GBA_REG_BG3CNT_ADDR     GBA_IO_REGS_ADDR + GBA_BG3CNT
198#define GBA_REG_BG0HOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG0HOFS
199#define GBA_REG_BG0VOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG0VOFS
200#define GBA_REG_BG1HOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG1HOFS
201#define GBA_REG_BG1VOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG1VOFS
202#define GBA_REG_BG2HOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG2HOFS
203#define GBA_REG_BG2VOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG2VOFS
204#define GBA_REG_BG3HOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG3HOFS
205#define GBA_REG_BG3VOFS_ADDR    GBA_IO_REGS_ADDR + GBA_BG3VOFS
206#define GBA_REG_BG2PA_ADDR      GBA_IO_REGS_ADDR + GBA_BG2PA
207#define GBA_REG_BG2PB_ADDR      GBA_IO_REGS_ADDR + GBA_BG2PB
208#define GBA_REG_BG2PC_ADDR      GBA_IO_REGS_ADDR + GBA_BG2PC
209#define GBA_REG_BG2PD_ADDR      GBA_IO_REGS_ADDR + GBA_BG2PD
210#define GBA_REG_BG2X_ADDR       GBA_IO_REGS_ADDR + GBA_BG2X
211#define GBA_REG_BG2X_L_ADDR     GBA_IO_REGS_ADDR + GBA_BG2X_L
212#define GBA_REG_BG2X_H_ADDR     GBA_IO_REGS_ADDR + GBA_BG2X_H
213#define GBA_REG_BG2Y_ADDR       GBA_IO_REGS_ADDR + GBA_BG2Y
214#define GBA_REG_BG2Y_L_ADDR     GBA_IO_REGS_ADDR + GBA_BG2Y_L
215#define GBA_REG_BG2Y_H_ADDR     GBA_IO_REGS_ADDR + GBA_BG2Y_H
216#define GBA_REG_BG3PA_ADDR      GBA_IO_REGS_ADDR + GBA_BG3PA
217#define GBA_REG_BG3PB_ADDR      GBA_IO_REGS_ADDR + GBA_BG3PB
218#define GBA_REG_BG3PC_ADDR      GBA_IO_REGS_ADDR + GBA_BG3PC
219#define GBA_REG_BG3PD_ADDR      GBA_IO_REGS_ADDR + GBA_BG3PD
220#define GBA_REG_BG3X_ADDR       GBA_IO_REGS_ADDR + GBA_BG3X
221#define GBA_REG_BG3X_L_ADDR     GBA_IO_REGS_ADDR + GBA_BG3X_L
222#define GBA_REG_BG3X_H_ADDR     GBA_IO_REGS_ADDR + GBA_BG3X_H
223#define GBA_REG_BG3Y_ADDR       GBA_IO_REGS_ADDR + GBA_BG3Y
224#define GBA_REG_BG3Y_L_ADDR     GBA_IO_REGS_ADDR + GBA_BG3Y_L
225#define GBA_REG_BG3Y_H_ADDR     GBA_IO_REGS_ADDR + GBA_BG3Y_H
226#define GBA_REG_WIN0H_ADDR      GBA_IO_REGS_ADDR + GBA_WIN0H
227#define GBA_REG_WIN1H_ADDR      GBA_IO_REGS_ADDR + GBA_WIN1H
228#define GBA_REG_WIN0V_ADDR      GBA_IO_REGS_ADDR + GBA_WIN0V
229#define GBA_REG_WIN1V_ADDR      GBA_IO_REGS_ADDR + GBA_WIN1V
230#define GBA_REG_WININ_ADDR      GBA_IO_REGS_ADDR + GBA_WININ
231#define GBA_REG_WINOUT_ADDR     GBA_IO_REGS_ADDR + GBA_WINOUT
232#define GBA_REG_MOSAIC_ADDR     GBA_IO_REGS_ADDR + GBA_MOSAIC
233#define GBA_REG_BLDCNT_ADDR     GBA_IO_REGS_ADDR + GBA_BLDCNT
234#define GBA_REG_BLDMOD_ADDR     GBA_IO_REGS_ADDR + GBA_BLDMOD
235#define GBA_REG_BLDALPHA_ADDR   GBA_IO_REGS_ADDR + GBA_BLDALPHA
236#define GBA_REG_COLEV_ADDR      GBA_IO_REGS_ADDR + GBA_COLEV
237#define GBA_REG_BLDY_ADDR       GBA_IO_REGS_ADDR + GBA_BLDY
238#define GBA_REG_COLY_ADDR       GBA_IO_REGS_ADDR + GBA_COLY
239/* LCD I/O Registers */
240#ifndef __asm__
241#define GBA_REG_DISPCNT         (*(volatile unsigned short *)(GBA_REG_DISPCNT_ADDR))
242#define GBA_REG_DISPSTAT        (*(volatile unsigned short *)(GBA_REG_DISPSTAT_ADDR))
243#define GBA_REG_VCOUNT          (*(volatile unsigned short *)(GBA_REG_VCOUNT_ADDR))
244#define GBA_REG_BG0CNT          (*(volatile unsigned short *)(GBA_REG_BG0CNT_ADDR))
245#define GBA_REG_BG1CNT          (*(volatile unsigned short *)(GBA_REG_BG1CNT_ADDR))
246#define GBA_REG_BG2CNT          (*(volatile unsigned short *)(GBA_REG_BG2CNT_ADDR))
247#define GBA_REG_BG3CNT          (*(volatile unsigned short *)(GBA_REG_BG3CNT_ADDR))
248#define GBA_REG_BG0HOFS         (*(volatile unsigned short *)(GBA_REG_BG0HOFS_ADDR))
249#define GBA_REG_BG0VOFS         (*(volatile unsigned short *)(GBA_REG_BG0VOFS_ADDR))
250#define GBA_REG_BG1HOFS         (*(volatile unsigned short *)(GBA_REG_BG1HOFS_ADDR))
251#define GBA_REG_BG1VOFS         (*(volatile unsigned short *)(GBA_REG_BG1VOFS_ADDR))
252#define GBA_REG_BG2HOFS         (*(volatile unsigned short *)(GBA_REG_BG2HOFS_ADDR))
253#define GBA_REG_BG2VOFS         (*(volatile unsigned short *)(GBA_REG_BG2VOFS_ADDR))
254#define GBA_REG_BG3HOFS         (*(volatile unsigned short *)(GBA_REG_BG3HOFS_ADDR))
255#define GBA_REG_BG3VOFS         (*(volatile unsigned short *)(GBA_REG_BG3VOFS_ADDR))
256#define GBA_REG_BG2PA           (*(volatile unsigned short *)(GBA_REG_BG2PA_ADDR))
257#define GBA_REG_BG2PB           (*(volatile unsigned short *)(GBA_REG_BG2PB_ADDR))
258#define GBA_REG_BG2PC           (*(volatile unsigned short *)(GBA_REG_BG2PC_ADDR))
259#define GBA_REG_BG2PD           (*(volatile unsigned short *)(GBA_REG_BG2PD_ADDR))
260#define GBA_REG_BG2X            (*(volatile unsigned int   *)(GBA_REG_BG2X_ADDR))
261#define GBA_REG_BG2X_L          (*(volatile unsigned short *)(GBA_REG_BG2X_L_ADDR))
262#define GBA_REG_BG2X_H          (*(volatile unsigned short *)(GBA_REG_BG2X_H_ADDR))
263#define GBA_REG_BG2Y            (*(volatile unsigned int   *)(GBA_REG_BG2Y_ADDR))
264#define GBA_REG_BG2Y_L          (*(volatile unsigned short *)(GBA_REG_BG2Y_L_ADDR))
265#define GBA_REG_BG2Y_H          (*(volatile unsigned short *)(GBA_REG_BG2Y_H_ADDR))
266#define GBA_REG_BG3PA           (*(volatile unsigned short *)(GBA_REG_BG3PA_ADDR))
267#define GBA_REG_BG3PB           (*(volatile unsigned short *)(GBA_REG_BG3PB_ADDR))
268#define GBA_REG_BG3PC           (*(volatile unsigned short *)(GBA_REG_BG3PC_ADDR))
269#define GBA_REG_BG3PD           (*(volatile unsigned short *)(GBA_REG_BG3PD_ADDR))
270#define GBA_REG_BG3X            (*(volatile unsigned int   *)(GBA_REG_BG3X_ADDR))
271#define GBA_REG_BG3X_L          (*(volatile unsigned short *)(GBA_REG_BG3X_L_ADDR))
272#define GBA_REG_BG3X_H          (*(volatile unsigned short *)(GBA_REG_BG3X_H_ADDR))
273#define GBA_REG_BG3Y            (*(volatile unsigned int   *)(GBA_REG_BG3Y_ADDR))
274#define GBA_REG_BG3Y_L          (*(volatile unsigned short *)(GBA_REG_BG3Y_L_ADDR))
275#define GBA_REG_BG3Y_H          (*(volatile unsigned short *)(GBA_REG_BG3Y_H_ADDR))
276#define GBA_REG_WIN0H           (*(volatile unsigned short *)(GBA_REG_WIN0H_ADDR))
277#define GBA_REG_WIN1H           (*(volatile unsigned short *)(GBA_REG_WIN1H_ADDR))
278#define GBA_REG_WIN0V           (*(volatile unsigned short *)(GBA_REG_WIN0V_ADDR))
279#define GBA_REG_WIN1V           (*(volatile unsigned short *)(GBA_REG_WIN1V_ADDR))
280#define GBA_REG_WININ           (*(volatile unsigned short *)(GBA_REG_WININ_ADDR))
281#define GBA_REG_WINOUT          (*(volatile unsigned short *)(GBA_REG_WINOUT_ADDR))
282#define GBA_REG_MOSAIC          (*(volatile unsigned short *)(GBA_REG_MOSAIC_ADDR))
283#define GBA_REG_BLDCNT          (*(volatile unsigned short *)(GBA_REG_BLDCNT_ADDR))
284#define GBA_REG_BLDMOD          (*(volatile unsigned short *)(GBA_REG_BLDMOD_ADDR))
285#define GBA_REG_BLDALPHA        (*(volatile unsigned short *)(GBA_REG_BLDALPHA_ADDR))
286#define GBA_REG_COLEV           (*(volatile unsigned short *)(GBA_REG_COLEV_ADDR))
287#define GBA_REG_BLDY            (*(volatile unsigned short *)(GBA_REG_BLDY_ADDR))
288#define GBA_REG_COLY            (*(volatile unsigned short *)(GBA_REG_COLY_ADDR))
289#endif
290/*---------------------------------------------------------------------------+
291|    SOUND
292+----------------------------------------------------------------------------*/
293#define GBA_SOUND_INIT            0x8000  /**< makes the sound restart       */
294#define GBA_SOUND_DUTY87          0x0000  /**< 87.5% wave duty               */
295#define GBA_SOUND_DUTY75          0x0040  /**< 75% wave duty                 */
296#define GBA_SOUND_DUTY50          0x0080  /**< 50% wave duty                 */
297#define GBA_SOUND_DUTY25          0x00C0  /**< 25% wave duty                 */
298
299#define GBA_SOUND1_PLAYONCE       0x4000  /**< play sound once               */
300#define GBA_SOUND1_PLAYLOOP       0x0000  /**< play sound looped             */
301#define GBA_SOUND1_INIT           0x8000  /**< makes the sound restart       */
302#define GBA_SOUND1_SWEEPSHIFTS(n)(n)      /**< number of sweep shifts (0-7)  */
303#define GBA_SOUND1_SWEEPINC       0x0000  /**< sweep add (freq increase)     */
304#define GBA_SOUND1_SWEEPDEC       0x0008  /**< sweep dec (freq decrese)      */
305#define GBA_SOUND1_SWEEPTIME(n)  (n<<4)   /**< time of sweep (0-7)           */
306#define GBA_SOUND1_ENVSTEPS(n)   (n<<8)   /**< envelope steps (0-7)          */
307#define GBA_SOUND1_ENVINC         0x0800  /**< envelope increase             */
308#define GBA_SOUND1_ENVDEC         0x0000  /**< envelope decrease             */
309#define GBA_SOUND1_ENVINIT(n)    (n<<12)  /**< initial envelope volume (0-15)*/
310
311#define GBA_SOUND2_PLAYONCE       0x4000  /**< play sound once               */
312#define GBA_SOUND2_PLAYLOOP       0x0000  /**< play sound looped             */
313#define GBA_SOUND2_INIT           0x8000  /**< makes the sound restart       */
314#define GBA_SOUND2_ENVSTEPS(n)   (n<<8)   /**< envelope steps (0-7)          */
315#define GBA_SOUND2_ENVINC         0x0800  /**< envelope increase             */
316#define GBA_SOUND2_ENVDEC         0x0000  /**< envelope decrease             */
317#define GBA_SOUND2_ENVINIT(n)    (n<<12)  /**< initial envelope volume (0-15)*/
318
319#define GBA_SOUND3_BANK32         0x0000  /**< Use two banks of 32 steps each*/
320#define GBA_SOUND3_BANK64         0x0020  /**< Use one bank of 64 steps      */
321#define GBA_SOUND3_SETBANK0       0x0000  /**< Bank to play 0 or 1 (non set bank is written to) */
322#define GBA_SOUND3_SETBANK1       0x0040
323#define GBA_SOUND3_PLAY           0x0080  /**< Output sound                  */
324
325#define GBA_SOUND3_OUTPUT0        0x0000  /**< Mute output                   */
326#define GBA_SOUND3_OUTPUT1        0x2000  /**< Output unmodified             */
327#define GBA_SOUND3_OUTPUT12       0x4000  /**< Output 1/2                    */
328#define GBA_SOUND3_OUTPUT14       0x6000  /**< Output 1/4                    */
329#define GBA_SOUND3_OUTPUT34       0x8000  /**< Output 3/4                    */
330
331#define GBA_SOUND3_PLAYONCE       0x4000  /**< Play sound once               */
332#define GBA_SOUND3_PLAYLOOP       0x0000  /**< Play sound looped             */
333#define GBA_SOUND3_INIT           0x8000  /**< Makes the sound restart       */
334
335#define GBA_SOUND4_PLAYONCE       0x4000  /**< play sound once               */
336#define GBA_SOUND4_PLAYLOOP       0x0000  /**< play sound looped             */
337#define GBA_SOUND4_INIT           0x8000  /**< makes the sound restart       */
338#define GBA_SOUND4_ENVSTEPS(n)   (n<<8)   /**< envelope steps (0-7)          */
339#define GBA_SOUND4_ENVINC         0x0800  /**< envelope increase             */
340#define GBA_SOUND4_ENVDEC         0x0000  /**< envelope decrease             */
341#define GBA_SOUND4_ENVINIT(n)    (n<<12)  /**< initial envelope volume (0-15)*/
342
343#define GBA_SOUND4_STEPS7         0x0004
344#define GBA_SOUND4_STEPS15        0x0000
345#define GBA_SOUND4_PLAYONCE       0x4000
346#define GBA_SOUND4_PLAYLOOP       0x0000
347#define GBA_SOUND4_INIT           0x8000
348
349/* Sound Register address offsets */
350#define GBA_SOUND1CNT_L         0x00000060    /**< Channel 1 sweep           */
351#define GBA_SG10                0x00000060    /**< Channel 1 sweep low      X*/
352#define GBA_SG10_L              0x00000060    /**< Channel 1 sweep high     X*/
353#define GBA_SOUND1CNT_H         0x00000062    /**< Channel 1 Duty/Len/Env    */
354#define GBA_SG10_H              0x00000062    /**< Channel 1 Duty/Len/Env   X*/
355#define GBA_SOUND1CNT_X         0x00000064    /**< Channel 1 Freq/Control    */
356#define GBA_SG11                0x00000064    /**< Channel 1 Freq/Control   X*/
357#define GBA_SOUND2CNT_L         0x00000068    /**< Channel 2 Duty/Len/Env    */
358#define GBA_SG20                0x00000068    /**< Channel 2 Duty/Len/Env   X*/
359#define GBA_SOUND2CNT_H         0x0000006C    /**< Channel 2 Freq/Control    */
360#define GBA_SG21                0x0000006C    /**< Channel 2 Freq/Control   X*/
361#define GBA_SOUND3CNT_L         0x00000070    /**< Channel 3 Stop/Wave RAM   */
362#define GBA_SG30                0x00000070    /**< Channel 3 Stop/Wave RAM  X*/
363#define GBA_SG30_L              0x00000070    /**< Channel 3 Stop/Wave RAM  X*/
364#define GBA_SOUND3CNT_H         0x00000072    /**< Channel 3 Len/Vol         */
365#define GBA_SG30_H              0x00000072    /**< Channel 3 Len/Vol        X*/
366#define GBA_SOUND3CNT_X         0x00000074    /**< Channel 3 Freq/Control    */
367#define GBA_SG31                0x00000074    /**< Channel 3 Freq/Control   X*/
368#define GBA_SOUND4CNT_L         0x00000078    /**< Channel 4 Len/Env         */
369#define GBA_SG40                0x00000078    /**< Channel 4 Len/Env        X*/
370#define GBA_SOUND4CNT_H         0x0000007C    /**< Channel 4 Freq/Control    */
371#define GBA_SG41                0x0000007C    /**< Channel 4 Freq/Control   X*/
372#define GBA_SOUNDCNT_L          0x00000080    /**< Control LR/Vol/Enable     */
373#define GBA_SGCNT0_L            0x00000080    /**< Control LR/Vol/Enable    X*/
374#define GBA_SOUNDCNT_H          0x00000082    /**< Control Mixing/DMA        */
375#define GBA_SGCNT0_H            0x00000082    /**< Control Mixing/DMA       X*/
376#define GBA_SOUNDCNT_X          0x00000084    /**< Control Sound on/off      */
377#define GBA_SGCNT1              0x00000084    /**< Control Sound on/off     X*/
378#define GBA_SOUNDBIAS           0x00000088    /**< Sound PWM control         */
379#define GBA_SGBIAS              0x00000088    /**< Sound PWM control        X*/
380#define GBA_SGWR0               0x00000090    /**< Ch3 Wave Pattern RAM     X*/
381#define GBA_WAVE_RAM0_L         0x00000090    /**< Ch3 Wave Pattern RAM      */
382#define GBA_SGWR0_L             0x00000090    /**< Ch3 Wave Pattern RAM     X*/
383#define GBA_WAVE_RAM0_H         0x00000092    /**< Ch3 Wave Pattern RAM      */
384#define GBA_SGWR0_H             0x00000092    /**< Ch3 Wave Pattern RAM     X*/
385#define GBA_SGWR1               0x00000094    /**< Ch3 Wave Pattern RAM     X*/
386#define GBA_WAVE_RAM1_L         0x00000094    /**< Ch3 Wave Pattern RAM      */
387#define GBA_SGWR1_L             0x00000094    /**< Ch3 Wave Pattern RAM     X*/
388#define GBA_WAVE_RAM1_H         0x00000096    /**< Ch3 Wave Pattern RAM      */
389#define GBA_SGWR1_H             0x00000096    /**< Ch3 Wave Pattern RAM     X*/
390#define GBA_SGWR2               0x00000098    /**< Ch3 Wave Pattern RAM     X*/
391#define GBA_WAVE_RAM2_L         0x00000098    /**< Ch3 Wave Pattern RAM      */
392#define GBA_SGWR2_L             0x00000098    /**< Ch3 Wave Pattern RAM     X*/
393#define GBA_WAVE_RAM2_H         0x0000009A    /**< Ch3 Wave Pattern RAM      */
394#define GBA_SGWR2_H             0x0000009A    /**< Ch3 Wave Pattern RAM     X*/
395#define GBA_SGWR3               0x0000009C    /**< Ch3 Wave Pattern RAM     X*/
396#define GBA_WAVE_RAM3_L         0x0000009C    /**< Ch3 Wave Pattern RAM      */
397#define GBA_SGWR3_L             0x0000009C    /**< Ch3 Wave Pattern RAM     X*/
398#define GBA_WAVE_RAM3_H         0x0000009E    /**< Ch3 Wave Pattern RAM      */
399#define GBA_SGWR3_H             0x0000009E    /**< Ch3 Wave Pattern RAM     X*/
400#define GBA_SGFIF0A             0x000000A0    /**< Sound A FIFO              X*/
401#define GBA_FIFO_A_L            0x000000A0    /**< Sound A FIFO               */
402#define GBA_SGFIFOA_L           0x000000A0    /**< Sound A FIFO              X*/
403#define GBA_FIFO_A_H            0x000000A2    /**< Sound A FIFO               */
404#define GBA_SGFIFOA_H           0x000000A2    /**< Sound A FIFO              X*/
405#define GBA_SGFIFOB             0x000000A4    /**< Sound B FIFO              X*/
406#define GBA_FIFO_B_L            0x000000A4    /**< Sound B FIFO               */
407#define GBA_SGFIFOB_L           0x000000A4    /**< Sound B FIFO              X*/
408#define GBA_FIFO_B_H            0x000000A6    /**< Sound B FIFO               */
409#define GBA_SGFIFOB_H           0x000000A6    /**< Sound B FIFO              X*/
410/* Sound Registers addresses */
411#define GBA_REG_SOUND1CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND1CNT_L
412#define GBA_REG_SG10_ADDR         GBA_IO_REGS_ADDR + GBA_SG10
413#define GBA_REG_SG10_L_ADDR       GBA_IO_REGS_ADDR + GBA_SG10_L
414#define GBA_REG_SOUND1CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND1CNT_H
415#define GBA_REG_SG10_H_ADDR       GBA_IO_REGS_ADDR + GBA_SG10_H
416#define GBA_REG_SOUND1CNT_X_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND1CNT_X
417#define GBA_REG_SG11_ADDR         GBA_IO_REGS_ADDR + GBA_SG11
418#define GBA_REG_SOUND2CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND2CNT_L
419#define GBA_REG_SG20_ADDR         GBA_IO_REGS_ADDR + GBA_SG20
420#define GBA_REG_SOUND2CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND2CNT_H
421#define GBA_REG_SG21_ADDR         GBA_IO_REGS_ADDR + GBA_SG21
422#define GBA_REG_SOUND3CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND3CNT_L
423#define GBA_REG_SG30_ADDR         GBA_IO_REGS_ADDR + GBA_SG30
424#define GBA_REG_SG30_L_ADDR       GBA_IO_REGS_ADDR + GBA_SG30_L
425#define GBA_REG_SOUND3CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND3CNT_H
426#define GBA_REG_SG30_H_ADDR       GBA_IO_REGS_ADDR + GBA_SG30_H
427#define GBA_REG_SOUND3CNT_X_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND3CNT_X
428#define GBA_REG_SG31_ADDR         GBA_IO_REGS_ADDR + GBA_SG31
429#define GBA_REG_SOUND4CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND4CNT_L
430#define GBA_REG_SG40_ADDR         GBA_IO_REGS_ADDR + GBA_SG40
431#define GBA_REG_SOUND4CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_SOUND4CNT_H
432#define GBA_REG_SG41_ADDR         GBA_IO_REGS_ADDR + GBA_SG41
433#define GBA_REG_SOUNDCNT_L_ADDR   GBA_IO_REGS_ADDR + GBA_SOUNDCNT_L
434#define GBA_REG_SGCNT0_L_ADDR     GBA_IO_REGS_ADDR + GBA_SGCNT0_L
435#define GBA_REG_SOUNDCNT_H_ADDR   GBA_IO_REGS_ADDR + GBA_SOUNDCNT_H
436#define GBA_REG_SGCNT0_H_ADDR     GBA_IO_REGS_ADDR + GBA_SGCNT0_H
437#define GBA_REG_SOUNDCNT_X_ADDR   GBA_IO_REGS_ADDR + GBA_SOUNDCNT_X
438#define GBA_REG_SGCNT1_ADDR       GBA_IO_REGS_ADDR + GBA_SGCNT1
439#define GBA_REG_SGBIAS_ADDR       GBA_IO_REGS_ADDR + GBA_SGBIAS
440#define GBA_REG_SOUNDBIAS_ADDR    GBA_IO_REGS_ADDR + GBA_SOUNDBIAS
441#define GBA_REG_SGWR0_ADDR        GBA_IO_REGS_ADDR + GBA_SGWR0
442#define GBA_REG_WAVE_RAM0_L_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM0_L
443#define GBA_REG_SGWR0_L_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR0_L
444#define GBA_REG_WAVE_RAM0_H_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM0_H
445#define GBA_REG_SGWR0_H_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR0_H
446#define GBA_REG_SGWR1_ADDR        GBA_IO_REGS_ADDR + GBA_SGWR1
447#define GBA_REG_WAVE_RAM1_L_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM1_L
448#define GBA_REG_SGWR1_L_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR1_L
449#define GBA_REG_WAVE_RAM1_H_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM1_H
450#define GBA_REG_SGWR1_H_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR1_H
451#define GBA_REG_SGWR2_ADDR        GBA_IO_REGS_ADDR + GBA_SGWR2
452#define GBA_REG_WAVE_RAM2_L_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM2_L
453#define GBA_REG_SGWR2_L_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR2_L
454#define GBA_REG_WAVE_RAM2_H_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM2_H
455#define GBA_REG_SGWR2_H_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR2_H
456#define GBA_REG_SGWR3_ADDR        GBA_IO_REGS_ADDR + GBA_SGWR3
457#define GBA_REG_WAVE_RAM3_L_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM3_L
458#define GBA_REG_SGWR3_L_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR3_L
459#define GBA_REG_WAVE_RAM3_H_ADDR  GBA_IO_REGS_ADDR + GBA_WAVE_RAM3_H
460#define GBA_REG_SGWR3_H_ADDR      GBA_IO_REGS_ADDR + GBA_SGWR3_H
461#define GBA_REG_SGFIF0A_ADDR      GBA_IO_REGS_ADDR + GBA_SGFIF0A
462#define GBA_REG_FIFO_A_L_ADDR     GBA_IO_REGS_ADDR + GBA_FIFO_A_L
463#define GBA_REG_SGFIFOA_L_ADDR    GBA_IO_REGS_ADDR + GBA_SGFIFOA_L
464#define GBA_REG_FIFO_A_H_ADDR     GBA_IO_REGS_ADDR + GBA_FIFO_A_H
465#define GBA_REG_SGFIFOA_H_ADDR    GBA_IO_REGS_ADDR + GBA_SGFIFOA_H
466#define GBA_REG_SGFIFOB_ADDR      GBA_IO_REGS_ADDR + GBA_SGFIFOB
467#define GBA_REG_FIFO_B_L_ADDR     GBA_IO_REGS_ADDR + GBA_FIFO_B_L
468#define GBA_REG_SGFIFOB_L_ADDR    GBA_IO_REGS_ADDR + GBA_SGFIFOB_L
469#define GBA_REG_FIFO_B_H_ADDR     GBA_IO_REGS_ADDR + GBA_FIFO_B_H
470#define GBA_REG_SGFIFOB_H_ADDR    GBA_IO_REGS_ADDR + GBA_SGFIFOB_H
471/* Sound Registers */
472#ifndef __asm__
473#define GBA_REG_SOUND1CNT_L     (*(volatile unsigned int   *)(GBA_REG_SOUND1CNT_L_ADDR))
474#define GBA_REG_SG10            (*(volatile unsigned int   *)(GBA_REG_SG10_ADDR))
475#define GBA_REG_SG10_L          (*(volatile unsigned short *)(GBA_REG_SG10_L_ADDR))
476#define GBA_REG_SOUND1CNT_H     (*(volatile unsigned short *)(GBA_REG_SOUND1CNT_H_ADDR))
477#define GBA_REG_SG10_H          (*(volatile unsigned short *)(GBA_REG_SG10_H_ADDR))
478#define GBA_REG_SOUND1CNT_X     (*(volatile unsigned short *)(GGBA_REG_SOUND1CNT_X_ADDR))
479#define GBA_REG_SG11            (*(volatile unsigned short *)(GBA_REG_SG11_ADDR))
480#define GBA_REG_SOUND2CNT_L     (*(volatile unsigned short *)(GBA_REG_SOUND2CNT_L_ADDR))
481#define GBA_REG_SG20            (*(volatile unsigned short *)(GBA_REG_SG20_ADDR))
482#define GBA_REG_SOUND2CNT_H     (*(volatile unsigned short *)(GBA_REG_SOUND2CNT_H_ADDR))
483#define GBA_REG_SG21            (*(volatile unsigned short *)(GBA_REG_SG21_ADDR))
484#define GBA_REG_SOUND3CNT_L     (*(volatile unsigned int   *)(GBA_REG_SOUND3CNT_L_ADDR))
485#define GBA_REG_SG30            (*(volatile unsigned int   *)(GBA_REG_SG30_ADDR))
486#define GBA_REG_SG30_L          (*(volatile unsigned short *)(GBA_REG_SG30_L_ADDR))
487#define GBA_REG_SOUND3CNT_H     (*(volatile unsigned short *)(GBA_REG_SOUND3CNT_H_ADDR))
488#define GBA_REG_SG30_H          (*(volatile unsigned short *)(GBA_REG_SG30_H_ADDR))
489#define GBA_REG_SOUND3CNT_X     (*(volatile unsigned short *)(GBA_REG_SOUND3CNT_X_ADDR))
490#define GBA_REG_SG31            (*(volatile unsigned short *)(GBA_REG_SG31_ADDR))
491#define GBA_REG_SOUND4CNT_L     (*(volatile unsigned short *)(GBA_REG_SOUND4CNT_L_ADDR))
492#define GBA_REG_SG40            (*(volatile unsigned short *)(GBA_REG_SG40_ADDR))
493#define GBA_REG_SOUND4CNT_H     (*(volatile unsigned short *)(GBA_REG_SOUND4CNT_H_ADDR))
494#define GBA_REG_SG41            (*(volatile unsigned short *)(GBA_REG_SG41_ADDR))
495#define GBA_REG_SGCNT0          (*(volatile unsigned int   *)(GBA_REG_SGCNT0_ADDR))
496#define GBA_REG_SOUNDCNT_L      (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_L_ADDR))
497#define GBA_REG_SGCNT0_L        (*(volatile unsigned short *)(GBA_REG_SGCNT0_L_ADDR))
498#define GBA_REG_SOUNDCNT_H      (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_H_ADDR))
499#define GBA_REG_SGCNT0_H        (*(volatile unsigned short *)(GBA_REG_SGCNT0_H_ADDR))
500#define GBA_REG_SOUNDCNT_X      (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_X_ADDR))
501#define GBA_REG_SGCNT1          (*(volatile unsigned short *)(GBA_REG_SGCNT1_ADDR))
502#define GBA_REG_SOUNDBIAS       (*(volatile unsigned short *)(GBA_REG_SOUNDBIAS_ADDR))
503#define GBA_REG_SGBIAS          (*(volatile unsigned short *)(GBA_REG_SGBIAS_ADDR))
504#define GBA_REG_SGWR0           (*(volatile unsigned int   *)(GBA_REG_SGWR0_ADDR))
505#define GBA_REG_WAVE_RAM0_L     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM0_L_ADDR))
506#define GBA_REG_SGWR0_L         (*(volatile unsigned short *)(GBA_REG_SGWR0_L_ADDR))
507#define GBA_REG_WAVE_RAM0_H     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM0_H_ADDR))
508#define GBA_REG_SGWR0_H         (*(volatile unsigned short *)(GBA_REG_SGWR0_H_ADDR))
509#define GBA_REG_SGWR1           (*(volatile unsigned int   *)(GBA_REG_SGWR1_ADDR))
510#define GBA_REG_WAVE_RAM1_L     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM1_L_ADDR))
511#define GBA_REG_SGWR1_L         (*(volatile unsigned short *)(GBA_REG_SGWR1_L_ADDR))
512#define GBA_REG_WAVE_RAM1_H     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM1_H_ADDR))
513#define GBA_REG_SGWR1_H         (*(volatile unsigned short *)(GBA_REG_SGWR1_H_ADDR))
514#define GBA_REG_SGWR2           (*(volatile unsigned int   *)(GBA_REG_SGWR2_ADDR))
515#define GBA_REG_WAVE_RAM2_L     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM2_L_ADDR))
516#define GBA_REG_SGWR2_L         (*(volatile unsigned short *)(GBA_REG_SGWR2_L_ADDR))
517#define GBA_REG_WAVE_RAM2_H     (*(volatile unsigned short *)(GGBA_REG_WAVE_RAM2_H_ADDR))
518#define GBA_REG_SGWR2_H         (*(volatile unsigned short *)(GGBA_REG_SGWR2_H_ADDR))
519#define GBA_REG_SGWR3           (*(volatile unsigned int   *)(GBA_REG_SGWR3_ADDR))
520#define GBA_REG_WAVE_RAM3_L     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM3_L)
521#define GBA_REG_SGWR3_L         (*(volatile unsigned short *)(GBA_REG_SGWR3_L)
522#define GBA_REG_WAVE_RAM3_H     (*(volatile unsigned short *)(GBA_REG_WAVE_RAM3_H_ADDR))
523#define GBA_REG_SGWR3_H         (*(volatile unsigned short *)(GBA_REG_SGWR3_H_ADDR))
524#define GBA_REG_SGFIF0A         (*(volatile unsigned int   *)(GBA_REG_SGFIF0A_ADDR))
525#define GBA_REG_FIFO_A_L        (*(volatile unsigned short *)(GBA_REG_FIFO_A_L_ADDR))
526#define GBA_REG_SGFIFOA_L       (*(volatile unsigned short *)(GBA_REG_SGFIFOA_L_ADDR))
527#define GBA_REG_FIFO_A_H        (*(volatile unsigned short *)(GBA_REG_FIFO_A_H_ADDR))
528#define GBA_REG_SGFIFOA_H       (*(volatile unsigned short *)(GBA_REG_SGFIFOA_H_ADDR))
529#define GBA_REG_SGFIFOB         (*(volatile unsigned int   *)(GBA_REG_SGFIFOB_ADDR))
530#define GBA_REG_FIFO_B_L        (*(volatile unsigned short *)(GBA_REG_FIFO_B_L_ADDR))
531#define GBA_REG_SGFIFOB_L       (*(volatile unsigned short *)(GBA_REG_SGFIFOB_L_ADDR))
532#define GBA_REG_FIFO_B_H        (*(volatile unsigned short *)(GBA_REG_FIFO_B_H_ADDR))
533#define GBA_REG_SGFIFOB_H       (*(volatile unsigned short *)(GBA_REG_SGFIFOB_H_ADDR))
534#endif
535
536/*---------------------------------------------------------------------------+
537|    DMA
538+----------------------------------------------------------------------------*/
539#define GBA_DMA_ENABLE            0x80000000  /**<  DMA Enable               */
540#define GBA_DMA_IF_ENABLE         0x40000000  /**<  Interrupt Request Enable */
541#define GBA_DMA_TIMMING_IMM       0x00000000  /**<  Run Immediately          */
542#define GBA_DMA_TIMMING_V_BLANK   0x10000000  /**<  Run V Blank              */
543#define GBA_DMA_TIMMING_H_BLANK   0x20000000  /**<  Run H Blank              */
544#define GBA_DMA_TIMMING_DISP      0x30000000  /**<  Run Display              */
545#define GBA_DMA_TIMMING_SOUND     0x30000000  /**<  Run Sound FIFO Request   */
546#define GBA_DMA_DREQ_ON           0x08000000  /**<  Data Request Synchronize Mode ON */
547#define GBA_DMA_16BIT_BUS         0x00000000  /**<  Select Bus Size 16Bit    */
548#define GBA_DMA_32BIT_BUS         0x04000000  /**<  Select Bus Size 32Bit    */
549#define GBA_DMA_CONTINUOUS_ON     0x02000000  /**<  Continuous Mode ON       */
550#define GBA_DMA_SRC_INC           0x00000000  /**<  Select Source Increment  */
551#define GBA_DMA_SRC_DEC           0x00800000  /**<  Select Source Decrement  */
552#define GBA_DMA_SRC_FIX           0x01000000  /**<  Select Source Fixed      */
553#define GBA_DMA_DEST_INC          0x00000000  /**<  Select Destination Increment */
554#define GBA_DMA_DEST_DEC          0x00200000  /**<  Select Destination Decrement */
555#define GBA_DMA_DEST_FIX          0x00400000  /**<  Select Destination Fixed */
556#define GBA_DMA_DEST_RELOAD       0x00600000  /**<  Select Destination       */
557
558
559/* DMA Transfer Channel address offsets */
560#define GBA_DMA0SAD             0x000000B0   /**< DMA0 Source Address             */
561#define GBA_DMA0SAD_L           0x000000B0   /**< DMA0 Source Address Low Value   */
562#define GBA_DMA0SAD_H           0x000000B2   /**< DMA0 Source Address High Value  */
563#define GBA_DMA0DAD             0x000000B4   /**< DMA0 Destination Address        */
564#define GBA_DMA0DAD_L           0x000000B4   /**< DMA0 Destination Address Low Value  */
565#define GBA_DMA0DAD_H           0x000000B6   /**< DMA0 Destination Address High Value */
566#define GBA_DMA0CNT             0x000000B8   /**< DMA0 Control Word Count          */
567#define GBA_DMA0CNT_L           0x000000B8   /**< DMA0 Control Low Value           */
568#define GBA_DMA0CNT_H           0x000000BA   /**< DMA0 Control High Value          */
569#define GBA_DMA1SAD             0x000000BC   /**< DMA1 Source Address              */
570#define GBA_DMA1SAD_L           0x000000BC   /**< DMA1 Source Address Low Value    */
571#define GBA_DMA1SAD_H           0x000000BE   /**< DMA1 Source Address High Value   */
572#define GBA_DMA1DAD             0x000000C0   /**< DMA1 Destination Address         */
573#define GBA_DMA1DAD_L           0x000000C0   /**< DMA1 Destination Address Low Value  */
574#define GBA_DMA1DAD_H           0x000000C2   /**< DMA1 Destination Address High Value */
575#define GBA_DMA1CNT             0x000000C4   /**< DMA1 Control Word Count          */
576#define GBA_DMA1CNT_L           0x000000C4   /**< DMA1 Control Low Value           */
577#define GBA_DMA1CNT_H           0x000000C6   /**< DMA1 Control High Value          */
578#define GBA_DMA2SAD             0x000000C8   /**< DMA2 Source Address              */
579#define GBA_DMA2SAD_L           0x000000C8   /**< DMA2 Source Address Low Value    */
580#define GBA_DMA2SAD_H           0x000000CA   /**< DMA2 Source Address High Value   */
581#define GBA_DMA2DAD             0x000000CC   /**< DMA2 Destination Address         */
582#define GBA_DMA2DAD_L           0x000000CC   /**< DMA2 Destination Address Low Value  */
583#define GBA_DMA2DAD_H           0x000000CE   /**< DMA2 Destination Address High Value */
584#define GBA_DMA2CNT             0x000000D0   /**< DMA2 Control Word Count          */
585#define GBA_DMA2CNT_L           0x000000D0   /**< DMA2 Control Low Value           */
586#define GBA_DMA2CNT_H           0x000000D2   /**< DMA2 Control High Value          */
587#define GBA_DMA3SAD             0x000000D4   /**< DMA3 Source Address              */
588#define GBA_DMA3SAD_L           0x000000D4   /**< DMA3 Source Address Low Value    */
589#define GBA_DMA3SAD_H           0x000000D6   /**< DMA3 Source Address High Value   */
590#define GBA_DMA3DAD             0x000000D8   /**< DMA3 Destination Address         */
591#define GBA_DMA3DAD_L           0x000000D8   /**< DMA3 Destination Address Low Value  */
592#define GBA_DMA3DAD_H           0x000000DA   /**< DMA3 Destination Address High Value */
593#define GBA_DMA3CNT             0x000000DC   /**< DMA3 Control Word Count          */
594#define GBA_DMA3CNT_L           0x000000DC   /**< DMA3 Control Low Value           */
595#define GBA_DMA3CNT_H           0x000000DE   /**< DMA3 Control High Value          */
596/* DMA Transfer Channel address  */
597#define GBA_REG_DMA0SAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA0SAD
598#define GBA_REG_DMA0SAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0SAD_L
599#define GBA_REG_DMA0SAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0SAD_H
600#define GBA_REG_DMA0DAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA0DAD
601#define GBA_REG_DMA0DAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0DAD_L
602#define GBA_REG_DMA0DAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0DAD_H
603#define GBA_REG_DMA0CNT_ADDR    GBA_IO_REGS_ADDR + GBA_DMA0CNT
604#define GBA_REG_DMA0CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0CNT_L
605#define GBA_REG_DMA0CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA0CNT_H
606#define GBA_REG_DMA1SAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA1SAD
607#define GBA_REG_DMA1SAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1SAD_L
608#define GBA_REG_DMA1SAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1SAD_H
609#define GBA_REG_DMA1DAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA1DAD)
610#define GBA_REG_DMA1DAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1DAD_L
611#define GBA_REG_DMA1DAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1DAD_H
612#define GBA_REG_DMA1CNT_ADDR    GBA_IO_REGS_ADDR + GBA_DMA1CNT
613#define GBA_REG_DMA1CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1CNT_L
614#define GBA_REG_DMA1CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA1CNT_H
615#define GBA_REG_DMA2SAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA2SAD
616#define GBA_REG_DMA2SAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2SAD_L
617#define GBA_REG_DMA2SAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2SAD_H
618#define GBA_REG_DMA2DAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA2DAD
619#define GBA_REG_DMA2DAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2DAD_L
620#define GBA_REG_DMA2DAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2DAD_H
621#define GBA_REG_DMA2CNT_ADDR    GBA_IO_REGS_ADDR + GBA_DMA2CNT
622#define GBA_REG_DMA2CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2CNT_L
623#define GBA_REG_DMA2CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA2CNT_H
624#define GBA_REG_DMA3SAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA3SAD
625#define GBA_REG_DMA3SAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3SAD_L
626#define GBA_REG_DMA3SAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3SAD_H
627#define GBA_REG_DMA3DAD_ADDR    GBA_IO_REGS_ADDR + GBA_DMA3DAD
628#define GBA_REG_DMA3DAD_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3DAD_L
629#define GBA_REG_DMA3DAD_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3DAD_H
630#define GBA_REG_DMA3CNT_ADDR    GBA_IO_REGS_ADDR + GBA_DMA3CNT
631#define GBA_REG_DMA3CNT_L_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3CNT_L
632#define GBA_REG_DMA3CNT_H_ADDR  GBA_IO_REGS_ADDR + GBA_DMA3CNT_H
633/* DMA Transfer Channel registers*/
634#ifndef __asm__
635#define GBA_REG_DMA0SAD         (*(volatile unsigned int   *)(GBA_REG_DMA0SAD_ADDR))
636#define GBA_REG_DMA0SAD_L       (*(volatile unsigned short *)(GBA_REG_DMA0SAD_L_ADDR))
637#define GBA_REG_DMA0SAD_H       (*(volatile unsigned short *)(GBA_REG_DMA0SAD_H_ADDR))
638#define GBA_REG_DMA0DAD         (*(volatile unsigned int   *)(GBA_REG_DMA0DAD_ADDR))
639#define GBA_REG_DMA0DAD_L       (*(volatile unsigned short *)(GBA_REG_DMA0DAD_L_ADDR))
640#define GBA_REG_DMA0DAD_H       (*(volatile unsigned short *)(GBA_REG_DMA0DAD_H_ADDR))
641#define GBA_REG_DMA0CNT         (*(volatile unsigned int   *)(GBA_REG_DMA0CNT_ADDR))
642#define GBA_REG_DMA0CNT_L       (*(volatile unsigned short *)(GBA_REG_DMA0CNT_L_ADDR))
643#define GBA_REG_DMA0CNT_H       (*(volatile unsigned short *)(GBA_REG_DMA0CNT_H_ADDR))
644#define GBA_REG_DMA1SAD         (*(volatile unsigned int   *)(GBA_REG_DMA1SAD_ADDR))
645#define GBA_REG_DMA1SAD_L       (*(volatile unsigned short *)(GBA_REG_DMA1SAD_L_ADDR))
646#define GBA_REG_DMA1SAD_H       (*(volatile unsigned short *)(GBA_REG_DMA1SAD_H_ADDR))
647#define GBA_REG_DMA1DAD         (*(volatile unsigned int   *)(GBA_REG_DMA1DAD_ADDR))
648#define GBA_REG_DMA1DAD_L       (*(volatile unsigned short *)(GBA_REG_DMA1DAD_L_ADDR))
649#define GBA_REG_DMA1DAD_H       (*(volatile unsigned short *)(GBA_REG_DMA1DAD_H_ADDR))
650#define GBA_REG_DMA1CNT         (*(volatile unsigned int   *)(GBA_REG_DMA1CNT_ADDR))
651#define GBA_REG_DMA1CNT_L       (*(volatile unsigned short *)(GBA_REG_DMA1CNT_L_ADDR))
652#define GBA_REG_DMA1CNT_H       (*(volatile unsigned short *)(GBA_REG_DMA1CNT_H_ADDR))
653#define GBA_REG_DMA2SAD         (*(volatile unsigned int   *)(GBA_REG_DMA2SAD_ADDR))
654#define GBA_REG_DMA2SAD_L       (*(volatile unsigned short *)(GBA_REG_DMA2SAD_L_ADDR))
655#define GBA_REG_DMA2SAD_H       (*(volatile unsigned short *)(GBA_REG_DMA2SAD_H_ADDR))
656#define GBA_REG_DMA2DAD         (*(volatile unsigned int   *)(GBA_REG_DMA2DAD_ADDR))
657#define GBA_REG_DMA2DAD_L       (*(volatile unsigned short *)(GBA_REG_DMA2DAD_L_ADDR))
658#define GBA_REG_DMA2DAD_H       (*(volatile unsigned short *)(GBA_REG_DMA2DAD_H_ADDR))
659#define GBA_REG_DMA2CNT         (*(volatile unsigned int   *)(GBA_REG_DMA2CNT_ADDR))
660#define GBA_REG_DMA2CNT_L       (*(volatile unsigned short *)(GBA_REG_DMA2CNT_L_ADDR))
661#define GBA_REG_DMA2CNT_H       (*(volatile unsigned short *)(GBA_REG_DMA2CNT_H_ADDR))
662#define GBA_REG_DMA3SAD         (*(volatile unsigned int   *)(GBA_REG_DMA3SAD_ADDR))
663#define GBA_REG_DMA3SAD_L       (*(volatile unsigned short *)(GBA_REG_DMA3SAD_L_ADDR))
664#define GBA_REG_DMA3SAD_H       (*(volatile unsigned short *)(GBA_REG_DMA3SAD_H_ADDR))
665#define GBA_REG_DMA3DAD         (*(volatile unsigned int   *)(GBA_REG_DMA3DAD_ADDR))
666#define GBA_REG_DMA3DAD_L       (*(volatile unsigned short *)(GBA_REG_DMA3DAD_L_ADDR))
667#define GBA_REG_DMA3DAD_H       (*(volatile unsigned short *)(GBA_REG_DMA3DAD_H_ADDR))
668#define GBA_REG_DMA3CNT         (*(volatile unsigned int *)(GBA_REG_DMA3CNT_ADDR))
669#define GBA_REG_DMA3CNT_L       (*(volatile unsigned short *)(GBA_REG_DMA3CNT_L_ADDR))
670#define GBA_REG_DMA3CNT_H       (*(volatile unsigned short *)(GBA_REG_DMA3CNT_H_ADDR))
671#endif
672
673/*---------------------------------------------------------------------------+
674|    TIMER
675+----------------------------------------------------------------------------*/
676#define GBA_TMR_PRESCALER_1CK     0x0000    /**< Prescaler 1 clock           */
677#define GBA_TMR_PRESCALER_64CK    0x0001    /**<          64 clocks          */
678#define GBA_TMR_PRESCALER_256CK   0x0002    /**<         256 clocks          */
679#define GBA_TMR_PRESCALER_1024CK  0x0003    /**<        1024 clocks          */
680#define GBA_TMR_IF_ENABLE         0x0040    /**< Interrupt Request Enable    */
681#define GBA_TMR_ENABLE            0x0080    /**< Run Timer                   */
682
683/* Timer Register address offsets */
684#define GBA_TM0D                0x00000100  /**< Timer 0 counter value      X*/
685#define GBA_TM0CNT_L            0x00000100  /**< Timer 0 counter value       */
686#define GBA_TM0CNT              0x00000102  /**< Timer 0 Control            X*/
687#define GBA_TM0CNT_H            0x00000102  /**< Timer 0 Control             */
688#define GBA_TM1D                0x00000104  /**< Timer 1 counter value      X*/
689#define GBA_TM1CNT_L            0x00000104  /**< Timer 1 counter value       */
690#define GBA_TM1CNT              0x00000106  /**< Timer 1 control            X*/
691#define GBA_TM1CNT_H            0x00000106  /**< Timer 1 control             */
692#define GBA_TM2D                0x00000108  /**< Timer 2 counter value      X*/
693#define GBA_TM2CNT_L            0x00000108  /**< Timer 2 counter value       */
694#define GBA_TM2CNT              0x0000010A  /**< Timer 2 control            X*/
695#define GBA_TM2CNT_H            0x0000010A  /**< Timer 2 control             */
696#define GBA_TM3D                0x0000010C  /**< Timer 3 counter value      X*/
697#define GBA_TM3CNT_L            0x0000010C  /**< Timer 3 counter value       */
698#define GBA_TM3CNT              0x0000010E  /**< Timer 4 control            X*/
699#define GBA_TM3CNT_H            0x0000010E  /**< Timer 4 control             */
700/* Timer Register addresses */
701#define GBA_REG_TM0D_ADDR       GBA_IO_REGS_ADDR + GBA_TM0D
702#define GBA_REG_TM0CNT_L_ADDR   GBA_IO_REGS_ADDR + GBA_TM0CNT_L
703#define GBA_REG_TM0CNT_ADDR     GBA_IO_REGS_ADDR + GBA_TM0CNT
704#define GBA_REG_TM0CNT_H_ADDR   GBA_IO_REGS_ADDR + GBA_TM0CNT_H
705#define GBA_REG_TM1D_ADDR       GBA_IO_REGS_ADDR + GBA_TM1D
706#define GBA_REG_TM1CNT_L_ADDR   GBA_IO_REGS_ADDR + GBA_TM1CNT_L
707#define GBA_REG_TM1CNT_ADDR     GBA_IO_REGS_ADDR + GBA_TM1CNT
708#define GBA_REG_TM1CNT_H_ADDR   GBA_IO_REGS_ADDR + GBA_TM1CNT_H
709#define GBA_REG_TM2D_ADDR       GBA_IO_REGS_ADDR + GBA_TM2D
710#define GBA_REG_TM2CNT_L_ADDR   GBA_IO_REGS_ADDR + GBA_TM2CNT_L
711#define GBA_REG_TM2CNT_ADDR     GBA_IO_REGS_ADDR + GBA_TM2CNT
712#define GBA_REG_TM2CNT_H_ADDR   GBA_IO_REGS_ADDR + GBA_TM2CNT_H
713#define GBA_REG_TM3D_ADDR       GBA_IO_REGS_ADDR + GBA_TM3D
714#define GBA_REG_TM3CNT_L_ADDR   GBA_IO_REGS_ADDR + GBA_TM3CNT_L
715#define GBA_REG_TM3CNT_ADDR     GBA_IO_REGS_ADDR + GBA_TM3CNT
716#define GBA_REG_TM3CNT_H_ADDR   GBA_IO_REGS_ADDR + GBA_TM3CNT_H
717/* Timer Registers */
718#ifndef __asm__
719#define GBA_REG_TM0D            (*(volatile unsigned short *)(GBA_REG_TM0D_ADDR))
720#define GBA_REG_TM0CNT_L        (*(volatile unsigned short *)(GBA_REG_TM0CNT_L_ADDR))
721#define GBA_REG_TM0CNT          (*(volatile unsigned short *)(GBA_REG_TM0CNT_ADDR))
722#define GBA_REG_TM0CNT_H        (*(volatile unsigned short *)(GBA_REG_TM0CNT_H_ADDR))
723#define GBA_REG_TM1D            (*(volatile unsigned short *)(GBA_REG_TM1D_ADDR))
724#define GBA_REG_TM1CNT_L        (*(volatile unsigned short *)(GBA_REG_TM1CNT_L_ADDR))
725#define GBA_REG_TM1CNT          (*(volatile unsigned short *)(GBA_REG_TM1CNT_ADDR))
726#define GBA_REG_TM1CNT_H        (*(volatile unsigned short *)(GBA_REG_TM1CNT_H_ADDR))
727#define GBA_REG_TM2D            (*(volatile unsigned short *)(GBA_REG_TM2D_ADDR))
728#define GBA_REG_TM2CMT_L        (*(volatile unsigned short *)(GBA_REG_TM2CNT_L_ADDR))
729#define GBA_REG_TM2CNT          (*(volatile unsigned short *)(GBA_REG_TM2CNT_ADDR))
730#define GBA_REG_TM2CNT_H        (*(volatile unsigned short *)(GBA_REG_TM2CNT_H_ADDR))
731#define GBA_REG_TM3D            (*(volatile unsigned short *)(GBA_REG_TM3D_ADDR))
732#define GBA_REG_TM3CNT_L        (*(volatile unsigned short *)(GBA_REG_TM3CNT_L_ADDR))
733#define GBA_REG_TM3CNT          (*(volatile unsigned short *)(GBA_REG_TM3CNT_ADDR))
734#define GBA_REG_TM3CNT_H        (*(volatile unsigned short *)(GBA_REG_TM3CNT_H_ADDR))
735#endif
736
737/*---------------------------------------------------------------------------+
738|    SERIAL set1
739+----------------------------------------------------------------------------*/
740#define GBA_SER_BAUD_MASK       0x0003
741#define GBA_SER_BAUD_9600       0x0000
742#define GBA_SER_BAUD_38400      0x0001
743#define GBA_SER_BAUD_57600      0x0002
744#define GBA_SER_BAUD_115200     0x0003
745#define GBA_SER_CTS             0x0004
746
747/* Serial Communication address offsets */
748#define GBA_SIOMULTI0           0x00000120 /**< SIO Multi-Player Data 0      */
749#define GBA_SCD0                0x00000120 /**< SIO Multi-Player Data 0     X*/
750#define GBA_SIOMULTI1           0x00000122 /**< SIO Multi-Player Data 1      */
751#define GBA_SCD1                0x00000122 /**< SIO Multi-Player Data 1     X*/
752#define GBA_SIOMULTI2           0x00000124 /**< SIO Multi-Player Data 2      */
753#define GBA_SCD2                0x00000124 /**< SIO Multi-Player Data 2     X*/
754#define GBA_SIOMULTI3           0x00000126 /**< SIO Multi-Player Data 3      */
755#define GBA_SCD3                0x00000126 /**< SIO Multi-Player Data 3     X*/
756#define GBA_SIOCNT              0x00000128 /**< SIO Control                  */
757#define GBA_SCCNT               0x00000128 /**< SIO Control                 X*/
758#define GBA_SCCNT_L             0x00000128 /**< SIO Control                 X*/
759#define GBA_SIOMLT_SEND         0x0000012A /**< Data Send Register           */
760#define GBA_SCCNT_H             0x0000012A /**< Data Send Register          X*/
761/* Serial Communication addresses */
762#define GBA_REG_SIOMULTI0_ADDR   GBA_IO_REGS_ADDR + GBA_SIOMULTI0
763#define GBA_REG_SCD0_ADDR        GBA_IO_REGS_ADDR + GBA_SCD0
764#define GBA_REG_SIOMULTI1_ADDR   GBA_IO_REGS_ADDR + GBA_SIOMULTI1
765#define GBA_REG_SCD1_ADDR        GBA_IO_REGS_ADDR + GBA_SCD1
766#define GBA_REG_SIOMULTI2_ADDR   GBA_IO_REGS_ADDR + GBA_SIOMULTI2
767#define GBA_REG_SCD2_ADDR        GBA_IO_REGS_ADDR + GBA_SCD2
768#define GBA_REG_SIOMULTI3_ADDR   GBA_IO_REGS_ADDR + GBA_SIOMULTI3
769#define GBA_REG_SCD3_ADDR        GBA_IO_REGS_ADDR + GBA_SCD3
770#define GBA_REG_SCCNT_ADDR       GBA_IO_REGS_ADDR + GBA_SCCNT
771#define GBA_REG_SIOCNT_ADDR      GBA_IO_REGS_ADDR + GBA_SIOCNT
772#define GBA_REG_SCCNT_L_ADDR     GBA_IO_REGS_ADDR + GBA_SCCNT_L
773#define GBA_REG_SIOMLT_SEND_ADDR GBA_IO_REGS_ADDR + GBA_SIOMLT_SEND
774#define GBA_REG_SCCNT_H_ADDR     GBA_IO_REGS_ADDR + GBA_SCCNT_H
775/* Serial Communication registers */
776#ifndef __asm__
777#define GBA_REG_SIOMULTI0       (*(volatile unsigned short *)(GBA_REG_SIOMULTI0_ADDR))
778#define GBA_REG_SCD0            (*(volatile unsigned short *)(GBA_REG_SCD0_ADDR))
779#define GBA_REG_SIOMULTI1       (*(volatile unsigned short *)(GBA_REG_SIOMULTI1_ADDR))
780#define GBA_REG_SCD1            (*(volatile unsigned short *)(GBA_REG_SCD1_ADDR))
781#define GBA_REG_SIOMULTI2       (*(volatile unsigned short *)(GBA_REG_SIOMULTI2_ADDR))
782#define GBA_REG_SCD2            (*(volatile unsigned short *)(GBA_REG_SCD2_ADDR))
783#define GBA_REG_SIOMULTI3       (*(volatile unsigned short *)(GBA_REG_SIOMULTI3_ADDR))
784#define GBA_REG_SCD3            (*(volatile unsigned short *)(GBA_REG_SCD3_ADDR))
785#define GBA_REG_SCCNT           (*(volatile unsigned int   *)(GBA_REG_SCCNT_ADDR))
786#define GBA_REG_SIOCNT          (*(volatile unsigned short *)(GBA_REG_SIOCNT_ADDR))
787#define GBA_REG_SCCNT_L         (*(volatile unsigned short *)(GBA_REG_SCCNT_L_ADDR))
788#define GBA_REG_SIOMLT_SEND     (*(volatile unsigned short *)(GBA_REG_SIOMLT_SEND_ADDR))
789#define GBA_REG_SCCNT_H         (*(volatile unsigned short *)(GBA_REG_SCCNT_H_ADDR))
790#endif
791
792/*---------------------------------------------------------------------------+
793|    KEYPAD
794+----------------------------------------------------------------------------*/
795/* GBA Keys */
796#define GBA_KEY_A               0x0001
797#define GBA_KEY_B               0x0002
798#define GBA_KEY_SELECT          0x0004
799#define GBA_KEY_START           0x0008
800#define GBA_KEY_RIGHT           0x0010
801#define GBA_KEY_LEFT            0x0020
802#define GBA_KEY_UP              0x0040
803#define GBA_KEY_DOWN            0x0080
804#define GBA_KEY_R               0x0100
805#define GBA_KEY_L               0x0200
806#define GBA_KEY_ALL             0x03FF
807/* Keypad registers address offsets */
808#define GBA_P1                  0x00000130 /**< Key Status                  X*/
809#define GBA_KEYINPUT            0x00000130 /**< Key Status                   */
810#define GBA_P1CNT               0x00000132 /**< Key Interrupt Control       X*/
811#define GBA_KEYCNT              0x00000132 /**< Key Interrupt Control        */
812/* Keypad registers addresses */
813#define GBA_REG_P1_ADDR         GBA_IO_REGS_ADDR + GBA_P1
814#define GBA_REG_KEYINPUT_ADDR   GBA_IO_REGS_ADDR + GBA_KEYINPUT
815#define GBA_REG_P1CNT_ADDR      GBA_IO_REGS_ADDR + GBA_P1CNT
816#define GBA_REG_KEYCNT_ADDR     GBA_IO_REGS_ADDR + GBA_KEYCNT
817/* Keypad registers */
818#ifndef __asm__
819#define GBA_REG_P1              (*(volatile unsigned short *)(GBA_REG_P1_ADDR))
820#define GBA_REG_KEYINPUT        (*(volatile unsigned short *)(GBA_REG_KEYINPUT_ADDR))
821#define GBA_REG_P1CNT           (*(volatile unsigned short *)(GBA_REG_P1CNT_ADDR))
822#define GBA_REG_KEYCNT          (*(volatile unsigned short *)(GBA_REG_KEYCNT_ADDR))
823#endif
824
825/*---------------------------------------------------------------------------+
826|    SERIAL set2
827+----------------------------------------------------------------------------*/
828/* Serial Communication address offsets */
829#define GBA_R                    0x00000134 /**< Mode Selection             X*/
830#define GBA_RCNT                 0x00000134 /**< Mode Selection              */
831#define GBA_HS_CTRL              0x00000140 /**< JOY BUS Control Register   X*/
832#define GBA_JOYCNT               0x00000140 /**< JOY BUS Control Register    */
833#define GBA_JOYRE                0x00000150 /**< Receive Data Register      X*/
834#define GBA_JOYRE_L              0x00000150 /**< Receive Data Register low  X*/
835#define GBA_JOY_RECV_L           0x00000150 /**< Receive Data Register low   */
836#define GBA_JOYRE_H              0x00000152 /**< Receive Data Register high X*/
837#define GBA_JOY_RECV_H           0x00000152 /**< Receive Data Register high  */
838#define GBA_JOYTR                0x00000154 /**< Send Data Register         X*/
839#define GBA_JOYTR_L              0x00000154 /**< Send Data Register low     X*/
840#define GBA_JOY_TRANS_L          0x00000154 /**< Send Data Register low      */
841#define GBA_JOYTR_H              0x00000156 /**< Send Data Register high    X*/
842#define GBA_JOY_TRANS_H          0x00000156 /**< Send Data Register high     */
843#define GBA_JSTAT                0x00000158 /**< Receive Status Register    X*/
844#define GBA_JOYSTAT              0x00000158 /**< Receive Status Register     */
845/* Serial Communication register addresses */
846#define GBA_REG_R_ADDR           GBA_IO_REGS_ADDR + GBA_R
847#define GBA_REG_RCNT_ADDR        GBA_IO_REGS_ADDR + GBA_RCNT
848#define GBA_REG_HS_CTRL_ADDR     GBA_IO_REGS_ADDR + GBA_HS_CTRL
849#define GBA_REG_JOYCNT_ADDR      GBA_IO_REGS_ADDR + GBA_JOYCNT
850#define GBA_REG_JOYRE_ADDR       GBA_IO_REGS_ADDR + GBA_JOYRE
851#define GBA_REG_JOYRE_L_ADDR     GBA_IO_REGS_ADDR + GBA_JOYRE_L
852#define GBA_REG_JOY_RECV_L_ADDR  GBA_IO_REGS_ADDR + GBA_JOY_RECV_L
853#define GBA_REG_JOYRE_H_ADDR     GBA_IO_REGS_ADDR + GBA_JOYRE_H
854#define GBA_REG_JOY_RECV_H_ADDR  GBA_IO_REGS_ADDR + GBA_JOY_RECV_H
855#define GBA_REG_JOYTR_ADDR       GBA_IO_REGS_ADDR + GBA_JOYTR
856#define GBA_REG_JOYTR_L_ADDR     GBA_IO_REGS_ADDR + GBA_JOYTR_L
857#define GBA_REG_JOY_TRANS_L_ADDR GBA_IO_REGS_ADDR + GBA_JOY_TRANS_L
858#define GBA_REG_JOYTR_H_ADDR     GBA_IO_REGS_ADDR + GBA_JOYTR_H
859#define GBA_REG_JOY_TRANS_H_ADDR GBA_IO_REGS_ADDR + GBA_JOY_TRANS_H
860#define GBA_REG_JSTAT_ADDR       GBA_IO_REGS_ADDR + GBA_JSTAT
861#define GBA_REG_JOYSTAT_ADDR     GBA_IO_REGS_ADDR + GBA_JOYSTAT
862/* Serial Communication registers */
863#ifndef __asm__
864#define GBA_REG_R               (*(volatile unsigned short *)(GBA_REG_R_ADDR))
865#define GBA_REG_RCNT            (*(volatile unsigned short *)(GBA_REG_RCNT_ADDR))
866#define GBA_REG_HS_CTRL         (*(volatile unsigned short *)(GBA_REG_HS_CTRL_ADDR))
867#define GBA_REG_JOYCNT          (*(volatile unsigned short *)(GBA_REG_JOYCNT_ADDR))
868#define GBA_REG_JOYRE           (*(volatile unsigned int   *)(GBA_REG_JOYRE_ADDR))
869#define GBA_REG_JOYRE_L         (*(volatile unsigned short *)(GBA_REG_JOYRE_L_ADDR))
870#define GBA_REG_JOY_RECV_L      (*(volatile unsigned short *)(GBA_REG_JOY_RECV_L_ADDR))
871#define GBA_REG_JOYRE_H         (*(volatile unsigned short *)(GBA_REG_JOYRE_H_ADDR))
872#define GBA_REG_JOY_RECV_H      (*(volatile unsigned short *)(GBA_REG_JOY_RECV_H_ADDR))
873#define GBA_REG_JOYTR           (*(volatile unsigned int   *)(GBA_REG_JOYTR_ADDR))
874#define GBA_REG_JOYTR_L         (*(volatile unsigned short *)(GBA_REG_JOYTR_L_ADDR))
875#define GBA_REG_JOY_TRANS_L     (*(volatile unsigned short *)(GBA_REG_JOY_TRANS_L_ADDR))
876#define GBA_REG_JOYTR_H         (*(volatile unsigned short *)(GBA_REG_JOYTR_H_ADDR))
877#define GBA_REG_JOY_TRANS_H     (*(volatile unsigned short *)(GBA_REG_JOY_TRANS_H_ADDR))
878#define GBA_REG_JSTAT           (*(volatile unsigned int   *)(GBA_REG_JSTAT_ADDR))
879#define GBA_REG_JOYSTAT         (*(volatile unsigned short *)(GBA_REG_JOYSTAT_ADDR))
880#endif
881
882/*---------------------------------------------------------------------------+
883|    INTERRUPT
884+----------------------------------------------------------------------------*/
885/* Interrupt sources */
886#define GBA_INT_VBLANK          0x0001
887#define GBA_INT_HBLANK          0x0002
888#define GBA_INT_VCOUNT          0x0004
889#define GBA_INT_TIMER0          0x0008
890#define GBA_INT_TIMER1          0x0010
891#define GBA_INT_TIMER2          0x0020
892#define GBA_INT_TIMER3          0x0040
893#define GBA_INT_SERIAL          0x0080
894#define GBA_INT_DMA0            0x0100
895#define GBA_INT_DMA1            0x0200
896#define GBA_INT_DMA2            0x0400
897#define GBA_INT_DMA3            0x0800
898#define GBA_INT_KEY             0x1000
899#define GBA_INT_CART            0x2000
900/* Interrupt address offsets */
901#define GBA_IE                  0x00000200 /**< Interrupt Enable        */
902#define GBA_IF                  0x00000202 /**< Interrupt Flags         */
903#define GBA_IME                 0x00000208 /**< Interrupt Master Enable */
904/* Interrupt addresses */
905#define GBA_REG_IE_ADDR         GBA_IO_REGS_ADDR + GBA_IE
906#define GBA_REG_IF_ADDR         GBA_IO_REGS_ADDR + GBA_IF
907#define GBA_REG_IME_ADDR        GBA_IO_REGS_ADDR + GBA_IME
908/* Interrupt registers */
909#ifndef __asm__
910#define GBA_REG_IE              (*(volatile unsigned short *)(GBA_REG_IE_ADDR))
911#define GBA_REG_IF              (*(volatile unsigned short *)(GBA_REG_IF_ADDR))
912#define GBA_REG_IME             (*(volatile unsigned short *)(GBA_REG_IME_ADDR))
913#endif
914
915/*---------------------------------------------------------------------------+
916|    Waitstate and Power-Down Control registers
917+----------------------------------------------------------------------------*/
918#define GBA_PHI_MASK            0x1800
919#define GBA_PHI_NONE            0x0000
920#define GBA_PHI_4_19MHZ         0x0800
921#define GBA_PHI_8_38MHZ         0x1000
922#define GBA_PHI_16_76MHZ        0x1800
923/* Waitstate and Power-Down Control address offsets */
924#define GBA_WSCNT               0x00000204 /**< Waitstate Control           X*/
925#define GBA_WAITCNT             0x00000204 /**< Waitstate Control            */
926#define GBA_PAUSE               0x00000300 /**< Power Down Control          X*/
927#define GBA_HALTCNT             0x00000300 /**< Power Down Control           */
928/* Waitstate and Power-Down Control addresses */
929#define GBA_REG_WSCNT_ADDR      GBA_IO_REGS_ADDR + GBA_WSCNT
930#define GBA_REG_WAITCNT_ADDR    GBA_IO_REGS_ADDR + GBA_WAITCNT
931#define GBA_REG_PAUSE_ADDR      GBA_IO_REGS_ADDR + GBA_PAUSE
932#define GBA_REG_HALTCNT_ADDR    GBA_IO_REGS_ADDR + GBA_HALTCNT
933/* Waitstate and Power-Down Control registers */
934#ifndef __asm__
935#define GBA_REG_WSCNT           (*(volatile unsigned short *)(GBA_REG_WSCNT_ADDR))
936#define GBA_REG_WAITCNT         (*(volatile unsigned short *)(GBA_REG_WAITCNT_ADDR))
937#define GBA_REG_PAUSE           (*(volatile unsigned short *)(GBA_REG_PAUSE_ADDR))
938#define GBA_REG_HALTCNT         (*(volatile unsigned short *)(GBA_REG_HALTCNT_ADDR))
939#endif
940
941
942/*
943 * @TODO remove UART register defines
944 * define for RTEMS UART registers to be able to compile
945 */
946#define RSRBR   0
947#define RSTHR   1
948#define RSIER   2
949#define RSIIR   3
950#define RSFCR   4
951#define RSLCR   5
952#define RSLSR   6
953#define RSDLL   7
954#define RSDLH   8
955#define RSCNT   9
956
957
958#endif /* _GBA_REGISTERS_H */
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