| 1 | /** |
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| 2 | * @file gba_registers.h |
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| 3 | * |
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| 4 | * Game Boy Advance registers. |
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| 5 | * |
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| 6 | * This include file contains definitions related to the ARM BSP. |
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| 7 | */ |
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| 8 | /* |
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| 9 | * RTEMS GBA BSP |
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| 10 | * |
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| 11 | * Copyright (c) 2004 Markku Puro <markku.puro@kopteri.net> |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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| 15 | * http://www.rtems.com/license/LICENSE. |
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| 16 | * |
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| 17 | * $Id$ |
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| 18 | */ |
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| 19 | |
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| 20 | /*---------------------------------------------------------------------------+ |
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| 21 | | THIS CODE WAS NOT MADE IN ASSOCIATION WITH NINTENDO AND DOES NOT MAKE |
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| 22 | | USE OF ANY INTELLECTUAL PROPERTY CLAIMED BY NINTENDO. |
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| 23 | | |
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| 24 | | GAMEBOY ADVANCE IS A TRADEMARK OF NINTENDO. |
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| 25 | | |
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| 26 | | THIS CODE HAS BEEN PROVIDED "AS-IS" WITHOUT A WARRANTY OF ANY KIND, |
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| 27 | | EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO IMPLIED |
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| 28 | | WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR USE. |
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| 29 | | THE ENTIRE RISK AS TO THE QUALITY OR PERFORMANCE OF THE CODE IS WITH YOU. |
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| 30 | | |
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| 31 | | IN NO EVENT, UNLESS AGREED TO IN WRITING, WILL ANY COPYRIGHT HOLDER, |
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| 32 | | OR ANY OTHER PARTY, BE HELD LIABLE FOR ANY DAMAGES RESULTING FROM |
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| 33 | | THE USE OR INABILITY TO USE THIS CODE. |
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| 34 | +----------------------------------------------------------------------------*/ |
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| 35 | |
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| 36 | #ifndef _GBA_REGISTERS_H |
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| 37 | #define _GBA_REGISTERS_H |
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| 38 | |
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| 39 | #ifndef __asm__ |
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| 40 | extern volatile unsigned int *Regs; /**< Chip registers */ |
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| 41 | #endif |
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| 42 | |
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| 43 | |
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| 44 | /*---------------------------------------------------------------------------+ |
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| 45 | | General address definitions |
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| 46 | +----------------------------------------------------------------------------*/ |
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| 47 | /* General Internal Memory */ |
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| 48 | #define GBA_BIOS_ADDR 0x00000000 /**< GBA BIOS start address */ |
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| 49 | #define GBA_BIOS_END 0x00004000 /**< GBA BIOS end address */ |
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| 50 | #define GBA_EXT_RAM_ADDR 0x02000000 /**< On-board RAM start address */ |
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| 51 | #define GBA_EXT_RAM_END 0x02040000 /**< On-board RAM end address */ |
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| 52 | #define GBA_INT_RAM_ADDR 0x03000000 /**< In-chip RAM start address */ |
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| 53 | #define GBA_INT_RAM_END 0x03008000 /**< In-chip RAM end address */ |
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| 54 | #define GBA_IO_REGS_ADDR 0x04000000 /**< IO registers start address */ |
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| 55 | #define GBA_IO_REGS_END 0x04000400 /**< IO registers end address */ |
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| 56 | /* Internal Display Memory */ |
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| 57 | #define GBA_PAL_RAM_ADDR 0x05000000 /**< PAL RAM start address */ |
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| 58 | #define GBA_PAL_RAM_END 0x05000400 /**< PAL RAM end address */ |
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| 59 | #define GBA_VRAM_ADDR 0x06000000 /**< VRAM start address */ |
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| 60 | #define GBA_VRAM_END 0x06180000 /**< VRAM end address */ |
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| 61 | #define GBA_OAM_ADDR 0x07000000 /**< OAM start address */ |
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| 62 | #define GBA_OAM_END 0x07000400 /**< OAM end address */ |
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| 63 | /* External Memory (Game Pak) */ |
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| 64 | #define GBA_ROM0_ADDR 0x08000000 /**< Card ROM0 start address */ |
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| 65 | #define GBA_ROM1_ADDR 0x0A000000 /**< Card ROM1 start address */ |
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| 66 | #define GBA_ROM2_ADDR 0x0C000000 /**< Card ROM2 start address */ |
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| 67 | #define GBA_SRAM_ADDR 0x0E000000 /**< Card SRAM start address */ |
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| 68 | #define GBA_SRAM_END 0x0E010000 /**< Card SRAM end address */ |
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| 69 | /* Unused Memory Area */ |
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| 70 | #define GBA_MAX_ADDR 0x10000000 /**< Upper 4bits of address bus unused */ |
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| 71 | /* Memory pointers */ |
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| 72 | #ifndef __asm__ |
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| 73 | #define GBA_BASE_BIOS (volatile unsigned char *)GBA_BIOS_ADDR /**< BIOS - System ROM 16KBytes, protected */ |
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| 74 | #define GBA_BASE_EXT_RAM (volatile unsigned char *)GBA_EXT_RAM_ADDR /**< WRAM - On-board Work RAM 256KBytes */ |
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| 75 | #define GBA_BASE_INT_RAM (volatile unsigned char *)GBA_INT_RAM_ADDR /**< WRAM - In-chip Work RAM 32KBytes */ |
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| 76 | #define GBA_BASE_IO_REGS (volatile unsigned char *)GBA_IO_REGS_ADDR /**< I/O Registers */ |
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| 77 | #define GBA_BASE_PAL_RAM (volatile unsigned char *)GBA_PAL_RAM_ADDR /**< BG/OBJ Palette RAM 1KBytes */ |
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| 78 | #define GBA_BASE_VRAM (volatile unsigned char *)GBA_VRAM_ADDR /**< VRAM - Video RAM 96KBytes */ |
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| 79 | #define GBA_BASE_OAM (volatile unsigned char *)GBA_OAM_ADDR /**< OAM - OBJ Attribytes */ |
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| 80 | #define GBA_BASE_ROM0 (volatile unsigned char *)GBA_ROM0_ADDR /**< Card ROM 32MB */ |
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| 81 | #define GBA_BASE_ROM1 (volatile unsigned char *)GBA_ROM1_ADDR /**< Card ROM 32MB */ |
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| 82 | #define GBA_BASE_ROM2 (volatile unsigned char *)GBA_ROM2_ADDR /**< Card ROM 32MB */ |
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| 83 | #define GBA_BASE_SRAM (volatile unsigned char *)GBA_SRAM_ADDR /**< Card SRAM 64KBytes */ |
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| 84 | #endif |
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| 85 | /*---------------------------------------------------------------------------* |
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| 86 | * Display Control |
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| 87 | *---------------------------------------------------------------------------*/ |
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| 88 | #define GBA_DISP_BG_MODE_MASK 0x0007 /**< BG Mode */ |
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| 89 | #define GBA_DISP_ON_MASK 0x1f00 /**< OBJ BG ON */ |
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| 90 | #define GBA_DISP_WIN_MASK 0x6000 /**< Window ON */ |
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| 91 | |
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| 92 | #define GBA_DISP_BG_MODE_SHIFT 0 |
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| 93 | #define GBA_DISP_ON_SHIFT 8 |
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| 94 | #define GBA_DISP_WIN_SHIFT 13 |
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| 95 | |
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| 96 | #define GBA_DISP_MODE_0 0x0000 /**< BG Mode 0 */ |
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| 97 | #define GBA_DISP_MODE_1 0x0001 /**< BG Mode 1 */ |
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| 98 | #define GBA_DISP_MODE_2 0x0002 /**< BG Mode 2 */ |
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| 99 | #define GBA_DISP_MODE_3 0x0003 /**< BG Mode 3 */ |
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| 100 | #define GBA_DISP_MODE_4 0x0004 /**< BG Mode 4 */ |
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| 101 | #define GBA_DISP_MODE_5 0x0005 /**< BG Mode 5 */ |
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| 102 | #define GBA_DISP_BMP_FRAME_NO 0x0010 /**< Bitmap Mode Display Frame */ |
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| 103 | #define GBA_DISP_OBJ_HOFF 0x0020 /**< OBJ Processing in H Blank OFF */ |
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| 104 | #define GBA_DISP_OBJ_CHAR_2D_MAP 0x0000 /**< OBJ Character Data 2D Mapping */ |
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| 105 | #define GBA_DISP_OBJ_CHAR_1D_MAP 0x0040 /**< OBJ Character Data 1D Mapping */ |
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| 106 | #define GBA_DISP_LCDC_OFF 0x0080 /**< LCDC OFF */ |
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| 107 | #define GBA_DISP_BG0_ON 0x0100 /**< BG0 ON */ |
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| 108 | #define GBA_DISP_BG1_ON 0x0200 /**< BG1 ON */ |
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| 109 | #define GBA_DISP_BG2_ON 0x0400 /**< BG2 ON */ |
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| 110 | #define GBA_DISP_BG3_ON 0x0800 /**< BG3 ON */ |
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| 111 | #define GBA_DISP_BG_ALL_ON 0x0f00 /**< All BG ON */ |
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| 112 | #define GBA_DISP_OBJ_ON 0x1000 /**< OBJ ON */ |
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| 113 | #define GBA_DISP_OBJ_BG_ALL_ON 0x1f00 /**< All OBJ/BG ON */ |
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| 114 | #define GBA_DISP_WIN0_ON 0x2000 /**< Window 0 ON */ |
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| 115 | #define GBA_DISP_WIN1_ON 0x4000 /**< Window 1 ON */ |
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| 116 | #define GBA_DISP_WIN01_ON 0x6000 /**< Window 0,1 ON */ |
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| 117 | #define GBA_DISP_OBJWIN_ON 0x8000 /**< OBJ Window ON */ |
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| 118 | #define GBA_DISP_WIN_ALL_ON 0xe000 /**< All Window ON */ |
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| 119 | #define GBA_DISP_ALL_ON 0x7f00 /**< All ON */ |
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| 120 | |
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| 121 | #define GBA_BG_MODE_0 0 |
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| 122 | #define GBA_BG_MODE_1 1 |
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| 123 | #define GBA_BG_MODE_2 2 |
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| 124 | #define GBA_BG_MODE_3 3 |
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| 125 | #define GBA_BG_MODE_4 4 |
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| 126 | #define GBA_BG_MODE_5 5 |
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| 127 | |
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| 128 | #define GBA_BG0_ENABLE 1 |
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| 129 | #define GBA_BG1_ENABLE 2 |
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| 130 | #define GBA_BG2_ENABLE 4 |
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| 131 | #define GBA_BG3_ENABLE 8 |
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| 132 | #define GBA_OBJ_ENABLE 16 |
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| 133 | |
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| 134 | #define GBA_OBJ_1D_MAP 1 |
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| 135 | #define GBA_OBJ_2D_MAP 0 |
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| 136 | |
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| 137 | |
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| 138 | /*---------------------------------------------------------------------------+ |
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| 139 | | LCD |
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| 140 | +----------------------------------------------------------------------------*/ |
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| 141 | /* LCD I/O Register address offsets */ |
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| 142 | #define GBA_DISPCNT 0x00000000 /**< LCD Control */ |
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| 143 | #define GBA_DISPSTAT 0x00000004 /**< General LCD Status (STAT,LYC) */ |
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| 144 | #define GBA_VCOUNT 0x00000006 /**< Vertical Counter (LY) */ |
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| 145 | #define GBA_BG0CNT 0x00000008 /**< BG0 Control */ |
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| 146 | #define GBA_BG1CNT 0x0000000A /**< BG1 Control */ |
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| 147 | #define GBA_BG2CNT 0x0000000C /**< BG2 Control */ |
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| 148 | #define GBA_BG3CNT 0x0000000E /**< BG3 Control */ |
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| 149 | #define GBA_BG0HOFS 0x00000010 /**< BG0 X-Offset */ |
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| 150 | #define GBA_BG0VOFS 0x00000012 /**< BG0 Y-Offset */ |
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| 151 | #define GBA_BG1HOFS 0x00000014 /**< BG1 X-Offset */ |
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| 152 | #define GBA_BG1VOFS 0x00000016 /**< BG1 Y-Offset */ |
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| 153 | #define GBA_BG2HOFS 0x00000018 /**< BG2 X-Offset */ |
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| 154 | #define GBA_BG2VOFS 0x0000001A /**< BG2 Y-Offset */ |
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| 155 | #define GBA_BG3HOFS 0x0000001C /**< BG3 X-Offset */ |
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| 156 | #define GBA_BG3VOFS 0x0000001E /**< BG3 Y-Offset */ |
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| 157 | #define GBA_BG2PA 0x00000020 /**< BG2 Rotation/Scaling Parameter A (dx) */ |
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| 158 | #define GBA_BG2PB 0x00000022 /**< BG2 Rotation/Scaling Parameter B (dmx) */ |
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| 159 | #define GBA_BG2PC 0x00000024 /**< BG2 Rotation/Scaling Parameter C (dy) */ |
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| 160 | #define GBA_BG2PD 0x00000026 /**< BG2 Rotation/Scaling Parameter D (dmy) */ |
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| 161 | #define GBA_BG2X 0x00000028 /**< BG2 Reference Point X-Coordinate */ |
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| 162 | #define GBA_BG2X_L 0x00000028 /**< BG2 Reference Point X-Coordinate low */ |
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| 163 | #define GBA_BG2X_H 0x0000002A /**< BG2 Reference Point X-Coordinate high */ |
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| 164 | #define GBA_BG2Y 0x0000002C /**< BG2 Reference Point Y-Coordinate */ |
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| 165 | #define GBA_BG2Y_L 0x0000002C /**< BG2 Reference Point Y-Coordinate low */ |
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| 166 | #define GBA_BG2Y_H 0x0000002E /**< BG2 Reference Point Y-Coordinate high */ |
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| 167 | #define GBA_BG3PA 0x00000030 /**< BG3 Rotation/Scaling Parameter A (dx) */ |
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| 168 | #define GBA_BG3PB 0x00000032 /**< BG3 Rotation/Scaling Parameter B (dmx) */ |
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| 169 | #define GBA_BG3PC 0x00000034 /**< BG3 Rotation/Scaling Parameter C (dy) */ |
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| 170 | #define GBA_BG3PD 0x00000036 /**< BG3 Rotation/Scaling Parameter D (dmy) */ |
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| 171 | #define GBA_BG3X 0x00000038 /**< BG3 Reference Point X-Coordinate */ |
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| 172 | #define GBA_BG3X_L 0x00000038 /**< BG3 Reference Point X-Coordinate low */ |
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| 173 | #define GBA_BG3X_H 0x0000003A /**< BG3 Reference Point X-Coordinate high */ |
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| 174 | #define GBA_BG3Y 0x0000003C /**< BG3 Reference Point Y-Coordinate */ |
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| 175 | #define GBA_BG3Y_L 0x0000003C /**< BG3 Reference Point Y-Coordinate low */ |
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| 176 | #define GBA_BG3Y_H 0x0000003E /**< BG3 Reference Point Y-Coordinate hugh */ |
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| 177 | #define GBA_WIN0H 0x00000040 /**< Window 0 Horizontal Dimensions */ |
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| 178 | #define GBA_WIN1H 0x00000042 /**< Window 1 Horizontal Dimensions */ |
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| 179 | #define GBA_WIN0V 0x00000044 /**< Window 0 Vertical Dimensions */ |
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| 180 | #define GBA_WIN1V 0x00000046 /**< Window 1 Vertical Dimensions */ |
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| 181 | #define GBA_WININ 0x00000048 /**< Control Inside of Window(s) */ |
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| 182 | #define GBA_WINOUT 0x0000004A /**< Control Outside of Windows & Inside of OBJ Window */ |
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| 183 | #define GBA_MOSAIC 0x0000004C /**< Mosaic Size */ |
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| 184 | #define GBA_BLDCNT 0x00000050 /**< Color Special Effects Selection */ |
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| 185 | #define GBA_BLDMOD 0x00000050 /**< Color Special Effects Selection X*/ |
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| 186 | #define GBA_BLDALPHA 0x00000052 /**< Alpha Blending Coefficients */ |
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| 187 | #define GBA_COLEV 0x00000052 /**< Alpha Blending Coefficients X*/ |
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| 188 | #define GBA_BLDY 0x00000054 /**< Brightness (Fade-In/Out) Coefficient */ |
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| 189 | #define GBA_COLY 0x00000054 /**< Brightness (Fade-In/Out) Coefficient X*/ |
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| 190 | /* LCD I/O Register addresses */ |
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| 191 | #define GBA_REG_DISPCNT_ADDR GBA_IO_REGS_ADDR + GBA_DISPCNT |
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| 192 | #define GBA_REG_DISPSTAT_ADDR GBA_IO_REGS_ADDR + GBA_DISPSTAT |
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| 193 | #define GBA_REG_VCOUNT_ADDR GBA_IO_REGS_ADDR + GBA_VCOUNT |
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| 194 | #define GBA_REG_BG0CNT_ADDR GBA_IO_REGS_ADDR + GBA_BG0CNT |
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| 195 | #define GBA_REG_BG1CNT_ADDR GBA_IO_REGS_ADDR + GBA_BG1CNT |
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| 196 | #define GBA_REG_BG2CNT_ADDR GBA_IO_REGS_ADDR + GBA_BG2CNT |
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| 197 | #define GBA_REG_BG3CNT_ADDR GBA_IO_REGS_ADDR + GBA_BG3CNT |
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| 198 | #define GBA_REG_BG0HOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG0HOFS |
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| 199 | #define GBA_REG_BG0VOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG0VOFS |
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| 200 | #define GBA_REG_BG1HOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG1HOFS |
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| 201 | #define GBA_REG_BG1VOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG1VOFS |
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| 202 | #define GBA_REG_BG2HOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG2HOFS |
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| 203 | #define GBA_REG_BG2VOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG2VOFS |
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| 204 | #define GBA_REG_BG3HOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG3HOFS |
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| 205 | #define GBA_REG_BG3VOFS_ADDR GBA_IO_REGS_ADDR + GBA_BG3VOFS |
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| 206 | #define GBA_REG_BG2PA_ADDR GBA_IO_REGS_ADDR + GBA_BG2PA |
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| 207 | #define GBA_REG_BG2PB_ADDR GBA_IO_REGS_ADDR + GBA_BG2PB |
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| 208 | #define GBA_REG_BG2PC_ADDR GBA_IO_REGS_ADDR + GBA_BG2PC |
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| 209 | #define GBA_REG_BG2PD_ADDR GBA_IO_REGS_ADDR + GBA_BG2PD |
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| 210 | #define GBA_REG_BG2X_ADDR GBA_IO_REGS_ADDR + GBA_BG2X |
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| 211 | #define GBA_REG_BG2X_L_ADDR GBA_IO_REGS_ADDR + GBA_BG2X_L |
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| 212 | #define GBA_REG_BG2X_H_ADDR GBA_IO_REGS_ADDR + GBA_BG2X_H |
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| 213 | #define GBA_REG_BG2Y_ADDR GBA_IO_REGS_ADDR + GBA_BG2Y |
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| 214 | #define GBA_REG_BG2Y_L_ADDR GBA_IO_REGS_ADDR + GBA_BG2Y_L |
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| 215 | #define GBA_REG_BG2Y_H_ADDR GBA_IO_REGS_ADDR + GBA_BG2Y_H |
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| 216 | #define GBA_REG_BG3PA_ADDR GBA_IO_REGS_ADDR + GBA_BG3PA |
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| 217 | #define GBA_REG_BG3PB_ADDR GBA_IO_REGS_ADDR + GBA_BG3PB |
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| 218 | #define GBA_REG_BG3PC_ADDR GBA_IO_REGS_ADDR + GBA_BG3PC |
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| 219 | #define GBA_REG_BG3PD_ADDR GBA_IO_REGS_ADDR + GBA_BG3PD |
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| 220 | #define GBA_REG_BG3X_ADDR GBA_IO_REGS_ADDR + GBA_BG3X |
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| 221 | #define GBA_REG_BG3X_L_ADDR GBA_IO_REGS_ADDR + GBA_BG3X_L |
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| 222 | #define GBA_REG_BG3X_H_ADDR GBA_IO_REGS_ADDR + GBA_BG3X_H |
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| 223 | #define GBA_REG_BG3Y_ADDR GBA_IO_REGS_ADDR + GBA_BG3Y |
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| 224 | #define GBA_REG_BG3Y_L_ADDR GBA_IO_REGS_ADDR + GBA_BG3Y_L |
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| 225 | #define GBA_REG_BG3Y_H_ADDR GBA_IO_REGS_ADDR + GBA_BG3Y_H |
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| 226 | #define GBA_REG_WIN0H_ADDR GBA_IO_REGS_ADDR + GBA_WIN0H |
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| 227 | #define GBA_REG_WIN1H_ADDR GBA_IO_REGS_ADDR + GBA_WIN1H |
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| 228 | #define GBA_REG_WIN0V_ADDR GBA_IO_REGS_ADDR + GBA_WIN0V |
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| 229 | #define GBA_REG_WIN1V_ADDR GBA_IO_REGS_ADDR + GBA_WIN1V |
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| 230 | #define GBA_REG_WININ_ADDR GBA_IO_REGS_ADDR + GBA_WININ |
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| 231 | #define GBA_REG_WINOUT_ADDR GBA_IO_REGS_ADDR + GBA_WINOUT |
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| 232 | #define GBA_REG_MOSAIC_ADDR GBA_IO_REGS_ADDR + GBA_MOSAIC |
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| 233 | #define GBA_REG_BLDCNT_ADDR GBA_IO_REGS_ADDR + GBA_BLDCNT |
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| 234 | #define GBA_REG_BLDMOD_ADDR GBA_IO_REGS_ADDR + GBA_BLDMOD |
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| 235 | #define GBA_REG_BLDALPHA_ADDR GBA_IO_REGS_ADDR + GBA_BLDALPHA |
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| 236 | #define GBA_REG_COLEV_ADDR GBA_IO_REGS_ADDR + GBA_COLEV |
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| 237 | #define GBA_REG_BLDY_ADDR GBA_IO_REGS_ADDR + GBA_BLDY |
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| 238 | #define GBA_REG_COLY_ADDR GBA_IO_REGS_ADDR + GBA_COLY |
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| 239 | /* LCD I/O Registers */ |
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| 240 | #ifndef __asm__ |
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| 241 | #define GBA_REG_DISPCNT (*(volatile unsigned short *)(GBA_REG_DISPCNT_ADDR)) |
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| 242 | #define GBA_REG_DISPSTAT (*(volatile unsigned short *)(GBA_REG_DISPSTAT_ADDR)) |
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| 243 | #define GBA_REG_VCOUNT (*(volatile unsigned short *)(GBA_REG_VCOUNT_ADDR)) |
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| 244 | #define GBA_REG_BG0CNT (*(volatile unsigned short *)(GBA_REG_BG0CNT_ADDR)) |
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| 245 | #define GBA_REG_BG1CNT (*(volatile unsigned short *)(GBA_REG_BG1CNT_ADDR)) |
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| 246 | #define GBA_REG_BG2CNT (*(volatile unsigned short *)(GBA_REG_BG2CNT_ADDR)) |
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| 247 | #define GBA_REG_BG3CNT (*(volatile unsigned short *)(GBA_REG_BG3CNT_ADDR)) |
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| 248 | #define GBA_REG_BG0HOFS (*(volatile unsigned short *)(GBA_REG_BG0HOFS_ADDR)) |
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| 249 | #define GBA_REG_BG0VOFS (*(volatile unsigned short *)(GBA_REG_BG0VOFS_ADDR)) |
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| 250 | #define GBA_REG_BG1HOFS (*(volatile unsigned short *)(GBA_REG_BG1HOFS_ADDR)) |
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| 251 | #define GBA_REG_BG1VOFS (*(volatile unsigned short *)(GBA_REG_BG1VOFS_ADDR)) |
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| 252 | #define GBA_REG_BG2HOFS (*(volatile unsigned short *)(GBA_REG_BG2HOFS_ADDR)) |
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| 253 | #define GBA_REG_BG2VOFS (*(volatile unsigned short *)(GBA_REG_BG2VOFS_ADDR)) |
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| 254 | #define GBA_REG_BG3HOFS (*(volatile unsigned short *)(GBA_REG_BG3HOFS_ADDR)) |
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| 255 | #define GBA_REG_BG3VOFS (*(volatile unsigned short *)(GBA_REG_BG3VOFS_ADDR)) |
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| 256 | #define GBA_REG_BG2PA (*(volatile unsigned short *)(GBA_REG_BG2PA_ADDR)) |
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| 257 | #define GBA_REG_BG2PB (*(volatile unsigned short *)(GBA_REG_BG2PB_ADDR)) |
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| 258 | #define GBA_REG_BG2PC (*(volatile unsigned short *)(GBA_REG_BG2PC_ADDR)) |
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| 259 | #define GBA_REG_BG2PD (*(volatile unsigned short *)(GBA_REG_BG2PD_ADDR)) |
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| 260 | #define GBA_REG_BG2X (*(volatile unsigned int *)(GBA_REG_BG2X_ADDR)) |
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| 261 | #define GBA_REG_BG2X_L (*(volatile unsigned short *)(GBA_REG_BG2X_L_ADDR)) |
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| 262 | #define GBA_REG_BG2X_H (*(volatile unsigned short *)(GBA_REG_BG2X_H_ADDR)) |
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| 263 | #define GBA_REG_BG2Y (*(volatile unsigned int *)(GBA_REG_BG2Y_ADDR)) |
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| 264 | #define GBA_REG_BG2Y_L (*(volatile unsigned short *)(GBA_REG_BG2Y_L_ADDR)) |
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| 265 | #define GBA_REG_BG2Y_H (*(volatile unsigned short *)(GBA_REG_BG2Y_H_ADDR)) |
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| 266 | #define GBA_REG_BG3PA (*(volatile unsigned short *)(GBA_REG_BG3PA_ADDR)) |
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| 267 | #define GBA_REG_BG3PB (*(volatile unsigned short *)(GBA_REG_BG3PB_ADDR)) |
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| 268 | #define GBA_REG_BG3PC (*(volatile unsigned short *)(GBA_REG_BG3PC_ADDR)) |
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| 269 | #define GBA_REG_BG3PD (*(volatile unsigned short *)(GBA_REG_BG3PD_ADDR)) |
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| 270 | #define GBA_REG_BG3X (*(volatile unsigned int *)(GBA_REG_BG3X_ADDR)) |
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| 271 | #define GBA_REG_BG3X_L (*(volatile unsigned short *)(GBA_REG_BG3X_L_ADDR)) |
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| 272 | #define GBA_REG_BG3X_H (*(volatile unsigned short *)(GBA_REG_BG3X_H_ADDR)) |
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| 273 | #define GBA_REG_BG3Y (*(volatile unsigned int *)(GBA_REG_BG3Y_ADDR)) |
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| 274 | #define GBA_REG_BG3Y_L (*(volatile unsigned short *)(GBA_REG_BG3Y_L_ADDR)) |
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| 275 | #define GBA_REG_BG3Y_H (*(volatile unsigned short *)(GBA_REG_BG3Y_H_ADDR)) |
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| 276 | #define GBA_REG_WIN0H (*(volatile unsigned short *)(GBA_REG_WIN0H_ADDR)) |
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| 277 | #define GBA_REG_WIN1H (*(volatile unsigned short *)(GBA_REG_WIN1H_ADDR)) |
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| 278 | #define GBA_REG_WIN0V (*(volatile unsigned short *)(GBA_REG_WIN0V_ADDR)) |
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| 279 | #define GBA_REG_WIN1V (*(volatile unsigned short *)(GBA_REG_WIN1V_ADDR)) |
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| 280 | #define GBA_REG_WININ (*(volatile unsigned short *)(GBA_REG_WININ_ADDR)) |
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| 281 | #define GBA_REG_WINOUT (*(volatile unsigned short *)(GBA_REG_WINOUT_ADDR)) |
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| 282 | #define GBA_REG_MOSAIC (*(volatile unsigned short *)(GBA_REG_MOSAIC_ADDR)) |
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| 283 | #define GBA_REG_BLDCNT (*(volatile unsigned short *)(GBA_REG_BLDCNT_ADDR)) |
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| 284 | #define GBA_REG_BLDMOD (*(volatile unsigned short *)(GBA_REG_BLDMOD_ADDR)) |
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| 285 | #define GBA_REG_BLDALPHA (*(volatile unsigned short *)(GBA_REG_BLDALPHA_ADDR)) |
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| 286 | #define GBA_REG_COLEV (*(volatile unsigned short *)(GBA_REG_COLEV_ADDR)) |
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| 287 | #define GBA_REG_BLDY (*(volatile unsigned short *)(GBA_REG_BLDY_ADDR)) |
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| 288 | #define GBA_REG_COLY (*(volatile unsigned short *)(GBA_REG_COLY_ADDR)) |
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| 289 | #endif |
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| 290 | /*---------------------------------------------------------------------------+ |
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| 291 | | SOUND |
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| 292 | +----------------------------------------------------------------------------*/ |
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| 293 | #define GBA_SOUND_INIT 0x8000 /**< makes the sound restart */ |
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| 294 | #define GBA_SOUND_DUTY87 0x0000 /**< 87.5% wave duty */ |
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| 295 | #define GBA_SOUND_DUTY75 0x0040 /**< 75% wave duty */ |
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| 296 | #define GBA_SOUND_DUTY50 0x0080 /**< 50% wave duty */ |
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| 297 | #define GBA_SOUND_DUTY25 0x00C0 /**< 25% wave duty */ |
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| 298 | |
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| 299 | #define GBA_SOUND1_PLAYONCE 0x4000 /**< play sound once */ |
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| 300 | #define GBA_SOUND1_PLAYLOOP 0x0000 /**< play sound looped */ |
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| 301 | #define GBA_SOUND1_INIT 0x8000 /**< makes the sound restart */ |
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| 302 | #define GBA_SOUND1_SWEEPSHIFTS(n)(n) /**< number of sweep shifts (0-7) */ |
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| 303 | #define GBA_SOUND1_SWEEPINC 0x0000 /**< sweep add (freq increase) */ |
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| 304 | #define GBA_SOUND1_SWEEPDEC 0x0008 /**< sweep dec (freq decrese) */ |
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| 305 | #define GBA_SOUND1_SWEEPTIME(n) (n<<4) /**< time of sweep (0-7) */ |
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| 306 | #define GBA_SOUND1_ENVSTEPS(n) (n<<8) /**< envelope steps (0-7) */ |
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| 307 | #define GBA_SOUND1_ENVINC 0x0800 /**< envelope increase */ |
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| 308 | #define GBA_SOUND1_ENVDEC 0x0000 /**< envelope decrease */ |
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| 309 | #define GBA_SOUND1_ENVINIT(n) (n<<12) /**< initial envelope volume (0-15)*/ |
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| 310 | |
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| 311 | #define GBA_SOUND2_PLAYONCE 0x4000 /**< play sound once */ |
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| 312 | #define GBA_SOUND2_PLAYLOOP 0x0000 /**< play sound looped */ |
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| 313 | #define GBA_SOUND2_INIT 0x8000 /**< makes the sound restart */ |
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| 314 | #define GBA_SOUND2_ENVSTEPS(n) (n<<8) /**< envelope steps (0-7) */ |
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| 315 | #define GBA_SOUND2_ENVINC 0x0800 /**< envelope increase */ |
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| 316 | #define GBA_SOUND2_ENVDEC 0x0000 /**< envelope decrease */ |
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| 317 | #define GBA_SOUND2_ENVINIT(n) (n<<12) /**< initial envelope volume (0-15)*/ |
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| 318 | |
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| 319 | #define GBA_SOUND3_BANK32 0x0000 /**< Use two banks of 32 steps each*/ |
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| 320 | #define GBA_SOUND3_BANK64 0x0020 /**< Use one bank of 64 steps */ |
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| 321 | #define GBA_SOUND3_SETBANK0 0x0000 /**< Bank to play 0 or 1 (non set bank is written to) */ |
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| 322 | #define GBA_SOUND3_SETBANK1 0x0040 |
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| 323 | #define GBA_SOUND3_PLAY 0x0080 /**< Output sound */ |
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| 324 | |
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| 325 | #define GBA_SOUND3_OUTPUT0 0x0000 /**< Mute output */ |
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| 326 | #define GBA_SOUND3_OUTPUT1 0x2000 /**< Output unmodified */ |
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| 327 | #define GBA_SOUND3_OUTPUT12 0x4000 /**< Output 1/2 */ |
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| 328 | #define GBA_SOUND3_OUTPUT14 0x6000 /**< Output 1/4 */ |
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| 329 | #define GBA_SOUND3_OUTPUT34 0x8000 /**< Output 3/4 */ |
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| 330 | |
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| 331 | #define GBA_SOUND3_PLAYONCE 0x4000 /**< Play sound once */ |
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| 332 | #define GBA_SOUND3_PLAYLOOP 0x0000 /**< Play sound looped */ |
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| 333 | #define GBA_SOUND3_INIT 0x8000 /**< Makes the sound restart */ |
|---|
| 334 | |
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| 335 | #define GBA_SOUND4_PLAYONCE 0x4000 /**< play sound once */ |
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| 336 | #define GBA_SOUND4_PLAYLOOP 0x0000 /**< play sound looped */ |
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| 337 | #define GBA_SOUND4_INIT 0x8000 /**< makes the sound restart */ |
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| 338 | #define GBA_SOUND4_ENVSTEPS(n) (n<<8) /**< envelope steps (0-7) */ |
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| 339 | #define GBA_SOUND4_ENVINC 0x0800 /**< envelope increase */ |
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| 340 | #define GBA_SOUND4_ENVDEC 0x0000 /**< envelope decrease */ |
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| 341 | #define GBA_SOUND4_ENVINIT(n) (n<<12) /**< initial envelope volume (0-15)*/ |
|---|
| 342 | |
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| 343 | #define GBA_SOUND4_STEPS7 0x0004 |
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| 344 | #define GBA_SOUND4_STEPS15 0x0000 |
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| 345 | #define GBA_SOUND4_PLAYONCE 0x4000 |
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| 346 | #define GBA_SOUND4_PLAYLOOP 0x0000 |
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| 347 | #define GBA_SOUND4_INIT 0x8000 |
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| 348 | |
|---|
| 349 | /* Sound Register address offsets */ |
|---|
| 350 | #define GBA_SOUND1CNT_L 0x00000060 /**< Channel 1 sweep */ |
|---|
| 351 | #define GBA_SG10 0x00000060 /**< Channel 1 sweep low X*/ |
|---|
| 352 | #define GBA_SG10_L 0x00000060 /**< Channel 1 sweep high X*/ |
|---|
| 353 | #define GBA_SOUND1CNT_H 0x00000062 /**< Channel 1 Duty/Len/Env */ |
|---|
| 354 | #define GBA_SG10_H 0x00000062 /**< Channel 1 Duty/Len/Env X*/ |
|---|
| 355 | #define GBA_SOUND1CNT_X 0x00000064 /**< Channel 1 Freq/Control */ |
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| 356 | #define GBA_SG11 0x00000064 /**< Channel 1 Freq/Control X*/ |
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| 357 | #define GBA_SOUND2CNT_L 0x00000068 /**< Channel 2 Duty/Len/Env */ |
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| 358 | #define GBA_SG20 0x00000068 /**< Channel 2 Duty/Len/Env X*/ |
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| 359 | #define GBA_SOUND2CNT_H 0x0000006C /**< Channel 2 Freq/Control */ |
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| 360 | #define GBA_SG21 0x0000006C /**< Channel 2 Freq/Control X*/ |
|---|
| 361 | #define GBA_SOUND3CNT_L 0x00000070 /**< Channel 3 Stop/Wave RAM */ |
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| 362 | #define GBA_SG30 0x00000070 /**< Channel 3 Stop/Wave RAM X*/ |
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| 363 | #define GBA_SG30_L 0x00000070 /**< Channel 3 Stop/Wave RAM X*/ |
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| 364 | #define GBA_SOUND3CNT_H 0x00000072 /**< Channel 3 Len/Vol */ |
|---|
| 365 | #define GBA_SG30_H 0x00000072 /**< Channel 3 Len/Vol X*/ |
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| 366 | #define GBA_SOUND3CNT_X 0x00000074 /**< Channel 3 Freq/Control */ |
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| 367 | #define GBA_SG31 0x00000074 /**< Channel 3 Freq/Control X*/ |
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| 368 | #define GBA_SOUND4CNT_L 0x00000078 /**< Channel 4 Len/Env */ |
|---|
| 369 | #define GBA_SG40 0x00000078 /**< Channel 4 Len/Env X*/ |
|---|
| 370 | #define GBA_SOUND4CNT_H 0x0000007C /**< Channel 4 Freq/Control */ |
|---|
| 371 | #define GBA_SG41 0x0000007C /**< Channel 4 Freq/Control X*/ |
|---|
| 372 | #define GBA_SOUNDCNT_L 0x00000080 /**< Control LR/Vol/Enable */ |
|---|
| 373 | #define GBA_SGCNT0_L 0x00000080 /**< Control LR/Vol/Enable X*/ |
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| 374 | #define GBA_SOUNDCNT_H 0x00000082 /**< Control Mixing/DMA */ |
|---|
| 375 | #define GBA_SGCNT0_H 0x00000082 /**< Control Mixing/DMA X*/ |
|---|
| 376 | #define GBA_SOUNDCNT_X 0x00000084 /**< Control Sound on/off */ |
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| 377 | #define GBA_SGCNT1 0x00000084 /**< Control Sound on/off X*/ |
|---|
| 378 | #define GBA_SOUNDBIAS 0x00000088 /**< Sound PWM control */ |
|---|
| 379 | #define GBA_SGBIAS 0x00000088 /**< Sound PWM control X*/ |
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| 380 | #define GBA_SGWR0 0x00000090 /**< Ch3 Wave Pattern RAM X*/ |
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| 381 | #define GBA_WAVE_RAM0_L 0x00000090 /**< Ch3 Wave Pattern RAM */ |
|---|
| 382 | #define GBA_SGWR0_L 0x00000090 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 383 | #define GBA_WAVE_RAM0_H 0x00000092 /**< Ch3 Wave Pattern RAM */ |
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| 384 | #define GBA_SGWR0_H 0x00000092 /**< Ch3 Wave Pattern RAM X*/ |
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| 385 | #define GBA_SGWR1 0x00000094 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 386 | #define GBA_WAVE_RAM1_L 0x00000094 /**< Ch3 Wave Pattern RAM */ |
|---|
| 387 | #define GBA_SGWR1_L 0x00000094 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 388 | #define GBA_WAVE_RAM1_H 0x00000096 /**< Ch3 Wave Pattern RAM */ |
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| 389 | #define GBA_SGWR1_H 0x00000096 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 390 | #define GBA_SGWR2 0x00000098 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 391 | #define GBA_WAVE_RAM2_L 0x00000098 /**< Ch3 Wave Pattern RAM */ |
|---|
| 392 | #define GBA_SGWR2_L 0x00000098 /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 393 | #define GBA_WAVE_RAM2_H 0x0000009A /**< Ch3 Wave Pattern RAM */ |
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| 394 | #define GBA_SGWR2_H 0x0000009A /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 395 | #define GBA_SGWR3 0x0000009C /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 396 | #define GBA_WAVE_RAM3_L 0x0000009C /**< Ch3 Wave Pattern RAM */ |
|---|
| 397 | #define GBA_SGWR3_L 0x0000009C /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 398 | #define GBA_WAVE_RAM3_H 0x0000009E /**< Ch3 Wave Pattern RAM */ |
|---|
| 399 | #define GBA_SGWR3_H 0x0000009E /**< Ch3 Wave Pattern RAM X*/ |
|---|
| 400 | #define GBA_SGFIF0A 0x000000A0 /**< Sound A FIFO X*/ |
|---|
| 401 | #define GBA_FIFO_A_L 0x000000A0 /**< Sound A FIFO */ |
|---|
| 402 | #define GBA_SGFIFOA_L 0x000000A0 /**< Sound A FIFO X*/ |
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| 403 | #define GBA_FIFO_A_H 0x000000A2 /**< Sound A FIFO */ |
|---|
| 404 | #define GBA_SGFIFOA_H 0x000000A2 /**< Sound A FIFO X*/ |
|---|
| 405 | #define GBA_SGFIFOB 0x000000A4 /**< Sound B FIFO X*/ |
|---|
| 406 | #define GBA_FIFO_B_L 0x000000A4 /**< Sound B FIFO */ |
|---|
| 407 | #define GBA_SGFIFOB_L 0x000000A4 /**< Sound B FIFO X*/ |
|---|
| 408 | #define GBA_FIFO_B_H 0x000000A6 /**< Sound B FIFO */ |
|---|
| 409 | #define GBA_SGFIFOB_H 0x000000A6 /**< Sound B FIFO X*/ |
|---|
| 410 | /* Sound Registers addresses */ |
|---|
| 411 | #define GBA_REG_SOUND1CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SOUND1CNT_L |
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| 412 | #define GBA_REG_SG10_ADDR GBA_IO_REGS_ADDR + GBA_SG10 |
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| 413 | #define GBA_REG_SG10_L_ADDR GBA_IO_REGS_ADDR + GBA_SG10_L |
|---|
| 414 | #define GBA_REG_SOUND1CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SOUND1CNT_H |
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| 415 | #define GBA_REG_SG10_H_ADDR GBA_IO_REGS_ADDR + GBA_SG10_H |
|---|
| 416 | #define GBA_REG_SOUND1CNT_X_ADDR GBA_IO_REGS_ADDR + GBA_SOUND1CNT_X |
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| 417 | #define GBA_REG_SG11_ADDR GBA_IO_REGS_ADDR + GBA_SG11 |
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| 418 | #define GBA_REG_SOUND2CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SOUND2CNT_L |
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| 419 | #define GBA_REG_SG20_ADDR GBA_IO_REGS_ADDR + GBA_SG20 |
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| 420 | #define GBA_REG_SOUND2CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SOUND2CNT_H |
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| 421 | #define GBA_REG_SG21_ADDR GBA_IO_REGS_ADDR + GBA_SG21 |
|---|
| 422 | #define GBA_REG_SOUND3CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SOUND3CNT_L |
|---|
| 423 | #define GBA_REG_SG30_ADDR GBA_IO_REGS_ADDR + GBA_SG30 |
|---|
| 424 | #define GBA_REG_SG30_L_ADDR GBA_IO_REGS_ADDR + GBA_SG30_L |
|---|
| 425 | #define GBA_REG_SOUND3CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SOUND3CNT_H |
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| 426 | #define GBA_REG_SG30_H_ADDR GBA_IO_REGS_ADDR + GBA_SG30_H |
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| 427 | #define GBA_REG_SOUND3CNT_X_ADDR GBA_IO_REGS_ADDR + GBA_SOUND3CNT_X |
|---|
| 428 | #define GBA_REG_SG31_ADDR GBA_IO_REGS_ADDR + GBA_SG31 |
|---|
| 429 | #define GBA_REG_SOUND4CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SOUND4CNT_L |
|---|
| 430 | #define GBA_REG_SG40_ADDR GBA_IO_REGS_ADDR + GBA_SG40 |
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| 431 | #define GBA_REG_SOUND4CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SOUND4CNT_H |
|---|
| 432 | #define GBA_REG_SG41_ADDR GBA_IO_REGS_ADDR + GBA_SG41 |
|---|
| 433 | #define GBA_REG_SOUNDCNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SOUNDCNT_L |
|---|
| 434 | #define GBA_REG_SGCNT0_L_ADDR GBA_IO_REGS_ADDR + GBA_SGCNT0_L |
|---|
| 435 | #define GBA_REG_SOUNDCNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SOUNDCNT_H |
|---|
| 436 | #define GBA_REG_SGCNT0_H_ADDR GBA_IO_REGS_ADDR + GBA_SGCNT0_H |
|---|
| 437 | #define GBA_REG_SOUNDCNT_X_ADDR GBA_IO_REGS_ADDR + GBA_SOUNDCNT_X |
|---|
| 438 | #define GBA_REG_SGCNT1_ADDR GBA_IO_REGS_ADDR + GBA_SGCNT1 |
|---|
| 439 | #define GBA_REG_SGBIAS_ADDR GBA_IO_REGS_ADDR + GBA_SGBIAS |
|---|
| 440 | #define GBA_REG_SOUNDBIAS_ADDR GBA_IO_REGS_ADDR + GBA_SOUNDBIAS |
|---|
| 441 | #define GBA_REG_SGWR0_ADDR GBA_IO_REGS_ADDR + GBA_SGWR0 |
|---|
| 442 | #define GBA_REG_WAVE_RAM0_L_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM0_L |
|---|
| 443 | #define GBA_REG_SGWR0_L_ADDR GBA_IO_REGS_ADDR + GBA_SGWR0_L |
|---|
| 444 | #define GBA_REG_WAVE_RAM0_H_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM0_H |
|---|
| 445 | #define GBA_REG_SGWR0_H_ADDR GBA_IO_REGS_ADDR + GBA_SGWR0_H |
|---|
| 446 | #define GBA_REG_SGWR1_ADDR GBA_IO_REGS_ADDR + GBA_SGWR1 |
|---|
| 447 | #define GBA_REG_WAVE_RAM1_L_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM1_L |
|---|
| 448 | #define GBA_REG_SGWR1_L_ADDR GBA_IO_REGS_ADDR + GBA_SGWR1_L |
|---|
| 449 | #define GBA_REG_WAVE_RAM1_H_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM1_H |
|---|
| 450 | #define GBA_REG_SGWR1_H_ADDR GBA_IO_REGS_ADDR + GBA_SGWR1_H |
|---|
| 451 | #define GBA_REG_SGWR2_ADDR GBA_IO_REGS_ADDR + GBA_SGWR2 |
|---|
| 452 | #define GBA_REG_WAVE_RAM2_L_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM2_L |
|---|
| 453 | #define GBA_REG_SGWR2_L_ADDR GBA_IO_REGS_ADDR + GBA_SGWR2_L |
|---|
| 454 | #define GBA_REG_WAVE_RAM2_H_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM2_H |
|---|
| 455 | #define GBA_REG_SGWR2_H_ADDR GBA_IO_REGS_ADDR + GBA_SGWR2_H |
|---|
| 456 | #define GBA_REG_SGWR3_ADDR GBA_IO_REGS_ADDR + GBA_SGWR3 |
|---|
| 457 | #define GBA_REG_WAVE_RAM3_L_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM3_L |
|---|
| 458 | #define GBA_REG_SGWR3_L_ADDR GBA_IO_REGS_ADDR + GBA_SGWR3_L |
|---|
| 459 | #define GBA_REG_WAVE_RAM3_H_ADDR GBA_IO_REGS_ADDR + GBA_WAVE_RAM3_H |
|---|
| 460 | #define GBA_REG_SGWR3_H_ADDR GBA_IO_REGS_ADDR + GBA_SGWR3_H |
|---|
| 461 | #define GBA_REG_SGFIF0A_ADDR GBA_IO_REGS_ADDR + GBA_SGFIF0A |
|---|
| 462 | #define GBA_REG_FIFO_A_L_ADDR GBA_IO_REGS_ADDR + GBA_FIFO_A_L |
|---|
| 463 | #define GBA_REG_SGFIFOA_L_ADDR GBA_IO_REGS_ADDR + GBA_SGFIFOA_L |
|---|
| 464 | #define GBA_REG_FIFO_A_H_ADDR GBA_IO_REGS_ADDR + GBA_FIFO_A_H |
|---|
| 465 | #define GBA_REG_SGFIFOA_H_ADDR GBA_IO_REGS_ADDR + GBA_SGFIFOA_H |
|---|
| 466 | #define GBA_REG_SGFIFOB_ADDR GBA_IO_REGS_ADDR + GBA_SGFIFOB |
|---|
| 467 | #define GBA_REG_FIFO_B_L_ADDR GBA_IO_REGS_ADDR + GBA_FIFO_B_L |
|---|
| 468 | #define GBA_REG_SGFIFOB_L_ADDR GBA_IO_REGS_ADDR + GBA_SGFIFOB_L |
|---|
| 469 | #define GBA_REG_FIFO_B_H_ADDR GBA_IO_REGS_ADDR + GBA_FIFO_B_H |
|---|
| 470 | #define GBA_REG_SGFIFOB_H_ADDR GBA_IO_REGS_ADDR + GBA_SGFIFOB_H |
|---|
| 471 | /* Sound Registers */ |
|---|
| 472 | #ifndef __asm__ |
|---|
| 473 | #define GBA_REG_SOUND1CNT_L (*(volatile unsigned int *)(GBA_REG_SOUND1CNT_L_ADDR)) |
|---|
| 474 | #define GBA_REG_SG10 (*(volatile unsigned int *)(GBA_REG_SG10_ADDR)) |
|---|
| 475 | #define GBA_REG_SG10_L (*(volatile unsigned short *)(GBA_REG_SG10_L_ADDR)) |
|---|
| 476 | #define GBA_REG_SOUND1CNT_H (*(volatile unsigned short *)(GBA_REG_SOUND1CNT_H_ADDR)) |
|---|
| 477 | #define GBA_REG_SG10_H (*(volatile unsigned short *)(GBA_REG_SG10_H_ADDR)) |
|---|
| 478 | #define GBA_REG_SOUND1CNT_X (*(volatile unsigned short *)(GGBA_REG_SOUND1CNT_X_ADDR)) |
|---|
| 479 | #define GBA_REG_SG11 (*(volatile unsigned short *)(GBA_REG_SG11_ADDR)) |
|---|
| 480 | #define GBA_REG_SOUND2CNT_L (*(volatile unsigned short *)(GBA_REG_SOUND2CNT_L_ADDR)) |
|---|
| 481 | #define GBA_REG_SG20 (*(volatile unsigned short *)(GBA_REG_SG20_ADDR)) |
|---|
| 482 | #define GBA_REG_SOUND2CNT_H (*(volatile unsigned short *)(GBA_REG_SOUND2CNT_H_ADDR)) |
|---|
| 483 | #define GBA_REG_SG21 (*(volatile unsigned short *)(GBA_REG_SG21_ADDR)) |
|---|
| 484 | #define GBA_REG_SOUND3CNT_L (*(volatile unsigned int *)(GBA_REG_SOUND3CNT_L_ADDR)) |
|---|
| 485 | #define GBA_REG_SG30 (*(volatile unsigned int *)(GBA_REG_SG30_ADDR)) |
|---|
| 486 | #define GBA_REG_SG30_L (*(volatile unsigned short *)(GBA_REG_SG30_L_ADDR)) |
|---|
| 487 | #define GBA_REG_SOUND3CNT_H (*(volatile unsigned short *)(GBA_REG_SOUND3CNT_H_ADDR)) |
|---|
| 488 | #define GBA_REG_SG30_H (*(volatile unsigned short *)(GBA_REG_SG30_H_ADDR)) |
|---|
| 489 | #define GBA_REG_SOUND3CNT_X (*(volatile unsigned short *)(GBA_REG_SOUND3CNT_X_ADDR)) |
|---|
| 490 | #define GBA_REG_SG31 (*(volatile unsigned short *)(GBA_REG_SG31_ADDR)) |
|---|
| 491 | #define GBA_REG_SOUND4CNT_L (*(volatile unsigned short *)(GBA_REG_SOUND4CNT_L_ADDR)) |
|---|
| 492 | #define GBA_REG_SG40 (*(volatile unsigned short *)(GBA_REG_SG40_ADDR)) |
|---|
| 493 | #define GBA_REG_SOUND4CNT_H (*(volatile unsigned short *)(GBA_REG_SOUND4CNT_H_ADDR)) |
|---|
| 494 | #define GBA_REG_SG41 (*(volatile unsigned short *)(GBA_REG_SG41_ADDR)) |
|---|
| 495 | #define GBA_REG_SGCNT0 (*(volatile unsigned int *)(GBA_REG_SGCNT0_ADDR)) |
|---|
| 496 | #define GBA_REG_SOUNDCNT_L (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_L_ADDR)) |
|---|
| 497 | #define GBA_REG_SGCNT0_L (*(volatile unsigned short *)(GBA_REG_SGCNT0_L_ADDR)) |
|---|
| 498 | #define GBA_REG_SOUNDCNT_H (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_H_ADDR)) |
|---|
| 499 | #define GBA_REG_SGCNT0_H (*(volatile unsigned short *)(GBA_REG_SGCNT0_H_ADDR)) |
|---|
| 500 | #define GBA_REG_SOUNDCNT_X (*(volatile unsigned short *)(GBA_REG_SOUNDCNT_X_ADDR)) |
|---|
| 501 | #define GBA_REG_SGCNT1 (*(volatile unsigned short *)(GBA_REG_SGCNT1_ADDR)) |
|---|
| 502 | #define GBA_REG_SOUNDBIAS (*(volatile unsigned short *)(GBA_REG_SOUNDBIAS_ADDR)) |
|---|
| 503 | #define GBA_REG_SGBIAS (*(volatile unsigned short *)(GBA_REG_SGBIAS_ADDR)) |
|---|
| 504 | #define GBA_REG_SGWR0 (*(volatile unsigned int *)(GBA_REG_SGWR0_ADDR)) |
|---|
| 505 | #define GBA_REG_WAVE_RAM0_L (*(volatile unsigned short *)(GBA_REG_WAVE_RAM0_L_ADDR)) |
|---|
| 506 | #define GBA_REG_SGWR0_L (*(volatile unsigned short *)(GBA_REG_SGWR0_L_ADDR)) |
|---|
| 507 | #define GBA_REG_WAVE_RAM0_H (*(volatile unsigned short *)(GBA_REG_WAVE_RAM0_H_ADDR)) |
|---|
| 508 | #define GBA_REG_SGWR0_H (*(volatile unsigned short *)(GBA_REG_SGWR0_H_ADDR)) |
|---|
| 509 | #define GBA_REG_SGWR1 (*(volatile unsigned int *)(GBA_REG_SGWR1_ADDR)) |
|---|
| 510 | #define GBA_REG_WAVE_RAM1_L (*(volatile unsigned short *)(GBA_REG_WAVE_RAM1_L_ADDR)) |
|---|
| 511 | #define GBA_REG_SGWR1_L (*(volatile unsigned short *)(GBA_REG_SGWR1_L_ADDR)) |
|---|
| 512 | #define GBA_REG_WAVE_RAM1_H (*(volatile unsigned short *)(GBA_REG_WAVE_RAM1_H_ADDR)) |
|---|
| 513 | #define GBA_REG_SGWR1_H (*(volatile unsigned short *)(GBA_REG_SGWR1_H_ADDR)) |
|---|
| 514 | #define GBA_REG_SGWR2 (*(volatile unsigned int *)(GBA_REG_SGWR2_ADDR)) |
|---|
| 515 | #define GBA_REG_WAVE_RAM2_L (*(volatile unsigned short *)(GBA_REG_WAVE_RAM2_L_ADDR)) |
|---|
| 516 | #define GBA_REG_SGWR2_L (*(volatile unsigned short *)(GBA_REG_SGWR2_L_ADDR)) |
|---|
| 517 | #define GBA_REG_WAVE_RAM2_H (*(volatile unsigned short *)(GGBA_REG_WAVE_RAM2_H_ADDR)) |
|---|
| 518 | #define GBA_REG_SGWR2_H (*(volatile unsigned short *)(GGBA_REG_SGWR2_H_ADDR)) |
|---|
| 519 | #define GBA_REG_SGWR3 (*(volatile unsigned int *)(GBA_REG_SGWR3_ADDR)) |
|---|
| 520 | #define GBA_REG_WAVE_RAM3_L (*(volatile unsigned short *)(GBA_REG_WAVE_RAM3_L) |
|---|
| 521 | #define GBA_REG_SGWR3_L (*(volatile unsigned short *)(GBA_REG_SGWR3_L) |
|---|
| 522 | #define GBA_REG_WAVE_RAM3_H (*(volatile unsigned short *)(GBA_REG_WAVE_RAM3_H_ADDR)) |
|---|
| 523 | #define GBA_REG_SGWR3_H (*(volatile unsigned short *)(GBA_REG_SGWR3_H_ADDR)) |
|---|
| 524 | #define GBA_REG_SGFIF0A (*(volatile unsigned int *)(GBA_REG_SGFIF0A_ADDR)) |
|---|
| 525 | #define GBA_REG_FIFO_A_L (*(volatile unsigned short *)(GBA_REG_FIFO_A_L_ADDR)) |
|---|
| 526 | #define GBA_REG_SGFIFOA_L (*(volatile unsigned short *)(GBA_REG_SGFIFOA_L_ADDR)) |
|---|
| 527 | #define GBA_REG_FIFO_A_H (*(volatile unsigned short *)(GBA_REG_FIFO_A_H_ADDR)) |
|---|
| 528 | #define GBA_REG_SGFIFOA_H (*(volatile unsigned short *)(GBA_REG_SGFIFOA_H_ADDR)) |
|---|
| 529 | #define GBA_REG_SGFIFOB (*(volatile unsigned int *)(GBA_REG_SGFIFOB_ADDR)) |
|---|
| 530 | #define GBA_REG_FIFO_B_L (*(volatile unsigned short *)(GBA_REG_FIFO_B_L_ADDR)) |
|---|
| 531 | #define GBA_REG_SGFIFOB_L (*(volatile unsigned short *)(GBA_REG_SGFIFOB_L_ADDR)) |
|---|
| 532 | #define GBA_REG_FIFO_B_H (*(volatile unsigned short *)(GBA_REG_FIFO_B_H_ADDR)) |
|---|
| 533 | #define GBA_REG_SGFIFOB_H (*(volatile unsigned short *)(GBA_REG_SGFIFOB_H_ADDR)) |
|---|
| 534 | #endif |
|---|
| 535 | |
|---|
| 536 | /*---------------------------------------------------------------------------+ |
|---|
| 537 | | DMA |
|---|
| 538 | +----------------------------------------------------------------------------*/ |
|---|
| 539 | #define GBA_DMA_ENABLE 0x80000000 /**< DMA Enable */ |
|---|
| 540 | #define GBA_DMA_IF_ENABLE 0x40000000 /**< Interrupt Request Enable */ |
|---|
| 541 | #define GBA_DMA_TIMMING_IMM 0x00000000 /**< Run Immediately */ |
|---|
| 542 | #define GBA_DMA_TIMMING_V_BLANK 0x10000000 /**< Run V Blank */ |
|---|
| 543 | #define GBA_DMA_TIMMING_H_BLANK 0x20000000 /**< Run H Blank */ |
|---|
| 544 | #define GBA_DMA_TIMMING_DISP 0x30000000 /**< Run Display */ |
|---|
| 545 | #define GBA_DMA_TIMMING_SOUND 0x30000000 /**< Run Sound FIFO Request */ |
|---|
| 546 | #define GBA_DMA_DREQ_ON 0x08000000 /**< Data Request Synchronize Mode ON */ |
|---|
| 547 | #define GBA_DMA_16BIT_BUS 0x00000000 /**< Select Bus Size 16Bit */ |
|---|
| 548 | #define GBA_DMA_32BIT_BUS 0x04000000 /**< Select Bus Size 32Bit */ |
|---|
| 549 | #define GBA_DMA_CONTINUOUS_ON 0x02000000 /**< Continuous Mode ON */ |
|---|
| 550 | #define GBA_DMA_SRC_INC 0x00000000 /**< Select Source Increment */ |
|---|
| 551 | #define GBA_DMA_SRC_DEC 0x00800000 /**< Select Source Decrement */ |
|---|
| 552 | #define GBA_DMA_SRC_FIX 0x01000000 /**< Select Source Fixed */ |
|---|
| 553 | #define GBA_DMA_DEST_INC 0x00000000 /**< Select Destination Increment */ |
|---|
| 554 | #define GBA_DMA_DEST_DEC 0x00200000 /**< Select Destination Decrement */ |
|---|
| 555 | #define GBA_DMA_DEST_FIX 0x00400000 /**< Select Destination Fixed */ |
|---|
| 556 | #define GBA_DMA_DEST_RELOAD 0x00600000 /**< Select Destination */ |
|---|
| 557 | |
|---|
| 558 | |
|---|
| 559 | /* DMA Transfer Channel address offsets */ |
|---|
| 560 | #define GBA_DMA0SAD 0x000000B0 /**< DMA0 Source Address */ |
|---|
| 561 | #define GBA_DMA0SAD_L 0x000000B0 /**< DMA0 Source Address Low Value */ |
|---|
| 562 | #define GBA_DMA0SAD_H 0x000000B2 /**< DMA0 Source Address High Value */ |
|---|
| 563 | #define GBA_DMA0DAD 0x000000B4 /**< DMA0 Destination Address */ |
|---|
| 564 | #define GBA_DMA0DAD_L 0x000000B4 /**< DMA0 Destination Address Low Value */ |
|---|
| 565 | #define GBA_DMA0DAD_H 0x000000B6 /**< DMA0 Destination Address High Value */ |
|---|
| 566 | #define GBA_DMA0CNT 0x000000B8 /**< DMA0 Control Word Count */ |
|---|
| 567 | #define GBA_DMA0CNT_L 0x000000B8 /**< DMA0 Control Low Value */ |
|---|
| 568 | #define GBA_DMA0CNT_H 0x000000BA /**< DMA0 Control High Value */ |
|---|
| 569 | #define GBA_DMA1SAD 0x000000BC /**< DMA1 Source Address */ |
|---|
| 570 | #define GBA_DMA1SAD_L 0x000000BC /**< DMA1 Source Address Low Value */ |
|---|
| 571 | #define GBA_DMA1SAD_H 0x000000BE /**< DMA1 Source Address High Value */ |
|---|
| 572 | #define GBA_DMA1DAD 0x000000C0 /**< DMA1 Destination Address */ |
|---|
| 573 | #define GBA_DMA1DAD_L 0x000000C0 /**< DMA1 Destination Address Low Value */ |
|---|
| 574 | #define GBA_DMA1DAD_H 0x000000C2 /**< DMA1 Destination Address High Value */ |
|---|
| 575 | #define GBA_DMA1CNT 0x000000C4 /**< DMA1 Control Word Count */ |
|---|
| 576 | #define GBA_DMA1CNT_L 0x000000C4 /**< DMA1 Control Low Value */ |
|---|
| 577 | #define GBA_DMA1CNT_H 0x000000C6 /**< DMA1 Control High Value */ |
|---|
| 578 | #define GBA_DMA2SAD 0x000000C8 /**< DMA2 Source Address */ |
|---|
| 579 | #define GBA_DMA2SAD_L 0x000000C8 /**< DMA2 Source Address Low Value */ |
|---|
| 580 | #define GBA_DMA2SAD_H 0x000000CA /**< DMA2 Source Address High Value */ |
|---|
| 581 | #define GBA_DMA2DAD 0x000000CC /**< DMA2 Destination Address */ |
|---|
| 582 | #define GBA_DMA2DAD_L 0x000000CC /**< DMA2 Destination Address Low Value */ |
|---|
| 583 | #define GBA_DMA2DAD_H 0x000000CE /**< DMA2 Destination Address High Value */ |
|---|
| 584 | #define GBA_DMA2CNT 0x000000D0 /**< DMA2 Control Word Count */ |
|---|
| 585 | #define GBA_DMA2CNT_L 0x000000D0 /**< DMA2 Control Low Value */ |
|---|
| 586 | #define GBA_DMA2CNT_H 0x000000D2 /**< DMA2 Control High Value */ |
|---|
| 587 | #define GBA_DMA3SAD 0x000000D4 /**< DMA3 Source Address */ |
|---|
| 588 | #define GBA_DMA3SAD_L 0x000000D4 /**< DMA3 Source Address Low Value */ |
|---|
| 589 | #define GBA_DMA3SAD_H 0x000000D6 /**< DMA3 Source Address High Value */ |
|---|
| 590 | #define GBA_DMA3DAD 0x000000D8 /**< DMA3 Destination Address */ |
|---|
| 591 | #define GBA_DMA3DAD_L 0x000000D8 /**< DMA3 Destination Address Low Value */ |
|---|
| 592 | #define GBA_DMA3DAD_H 0x000000DA /**< DMA3 Destination Address High Value */ |
|---|
| 593 | #define GBA_DMA3CNT 0x000000DC /**< DMA3 Control Word Count */ |
|---|
| 594 | #define GBA_DMA3CNT_L 0x000000DC /**< DMA3 Control Low Value */ |
|---|
| 595 | #define GBA_DMA3CNT_H 0x000000DE /**< DMA3 Control High Value */ |
|---|
| 596 | /* DMA Transfer Channel address */ |
|---|
| 597 | #define GBA_REG_DMA0SAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA0SAD |
|---|
| 598 | #define GBA_REG_DMA0SAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA0SAD_L |
|---|
| 599 | #define GBA_REG_DMA0SAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA0SAD_H |
|---|
| 600 | #define GBA_REG_DMA0DAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA0DAD |
|---|
| 601 | #define GBA_REG_DMA0DAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA0DAD_L |
|---|
| 602 | #define GBA_REG_DMA0DAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA0DAD_H |
|---|
| 603 | #define GBA_REG_DMA0CNT_ADDR GBA_IO_REGS_ADDR + GBA_DMA0CNT |
|---|
| 604 | #define GBA_REG_DMA0CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA0CNT_L |
|---|
| 605 | #define GBA_REG_DMA0CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA0CNT_H |
|---|
| 606 | #define GBA_REG_DMA1SAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA1SAD |
|---|
| 607 | #define GBA_REG_DMA1SAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA1SAD_L |
|---|
| 608 | #define GBA_REG_DMA1SAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA1SAD_H |
|---|
| 609 | #define GBA_REG_DMA1DAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA1DAD) |
|---|
| 610 | #define GBA_REG_DMA1DAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA1DAD_L |
|---|
| 611 | #define GBA_REG_DMA1DAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA1DAD_H |
|---|
| 612 | #define GBA_REG_DMA1CNT_ADDR GBA_IO_REGS_ADDR + GBA_DMA1CNT |
|---|
| 613 | #define GBA_REG_DMA1CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA1CNT_L |
|---|
| 614 | #define GBA_REG_DMA1CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA1CNT_H |
|---|
| 615 | #define GBA_REG_DMA2SAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA2SAD |
|---|
| 616 | #define GBA_REG_DMA2SAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA2SAD_L |
|---|
| 617 | #define GBA_REG_DMA2SAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA2SAD_H |
|---|
| 618 | #define GBA_REG_DMA2DAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA2DAD |
|---|
| 619 | #define GBA_REG_DMA2DAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA2DAD_L |
|---|
| 620 | #define GBA_REG_DMA2DAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA2DAD_H |
|---|
| 621 | #define GBA_REG_DMA2CNT_ADDR GBA_IO_REGS_ADDR + GBA_DMA2CNT |
|---|
| 622 | #define GBA_REG_DMA2CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA2CNT_L |
|---|
| 623 | #define GBA_REG_DMA2CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA2CNT_H |
|---|
| 624 | #define GBA_REG_DMA3SAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA3SAD |
|---|
| 625 | #define GBA_REG_DMA3SAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA3SAD_L |
|---|
| 626 | #define GBA_REG_DMA3SAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA3SAD_H |
|---|
| 627 | #define GBA_REG_DMA3DAD_ADDR GBA_IO_REGS_ADDR + GBA_DMA3DAD |
|---|
| 628 | #define GBA_REG_DMA3DAD_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA3DAD_L |
|---|
| 629 | #define GBA_REG_DMA3DAD_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA3DAD_H |
|---|
| 630 | #define GBA_REG_DMA3CNT_ADDR GBA_IO_REGS_ADDR + GBA_DMA3CNT |
|---|
| 631 | #define GBA_REG_DMA3CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_DMA3CNT_L |
|---|
| 632 | #define GBA_REG_DMA3CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_DMA3CNT_H |
|---|
| 633 | /* DMA Transfer Channel registers*/ |
|---|
| 634 | #ifndef __asm__ |
|---|
| 635 | #define GBA_REG_DMA0SAD (*(volatile unsigned int *)(GBA_REG_DMA0SAD_ADDR)) |
|---|
| 636 | #define GBA_REG_DMA0SAD_L (*(volatile unsigned short *)(GBA_REG_DMA0SAD_L_ADDR)) |
|---|
| 637 | #define GBA_REG_DMA0SAD_H (*(volatile unsigned short *)(GBA_REG_DMA0SAD_H_ADDR)) |
|---|
| 638 | #define GBA_REG_DMA0DAD (*(volatile unsigned int *)(GBA_REG_DMA0DAD_ADDR)) |
|---|
| 639 | #define GBA_REG_DMA0DAD_L (*(volatile unsigned short *)(GBA_REG_DMA0DAD_L_ADDR)) |
|---|
| 640 | #define GBA_REG_DMA0DAD_H (*(volatile unsigned short *)(GBA_REG_DMA0DAD_H_ADDR)) |
|---|
| 641 | #define GBA_REG_DMA0CNT (*(volatile unsigned int *)(GBA_REG_DMA0CNT_ADDR)) |
|---|
| 642 | #define GBA_REG_DMA0CNT_L (*(volatile unsigned short *)(GBA_REG_DMA0CNT_L_ADDR)) |
|---|
| 643 | #define GBA_REG_DMA0CNT_H (*(volatile unsigned short *)(GBA_REG_DMA0CNT_H_ADDR)) |
|---|
| 644 | #define GBA_REG_DMA1SAD (*(volatile unsigned int *)(GBA_REG_DMA1SAD_ADDR)) |
|---|
| 645 | #define GBA_REG_DMA1SAD_L (*(volatile unsigned short *)(GBA_REG_DMA1SAD_L_ADDR)) |
|---|
| 646 | #define GBA_REG_DMA1SAD_H (*(volatile unsigned short *)(GBA_REG_DMA1SAD_H_ADDR)) |
|---|
| 647 | #define GBA_REG_DMA1DAD (*(volatile unsigned int *)(GBA_REG_DMA1DAD_ADDR)) |
|---|
| 648 | #define GBA_REG_DMA1DAD_L (*(volatile unsigned short *)(GBA_REG_DMA1DAD_L_ADDR)) |
|---|
| 649 | #define GBA_REG_DMA1DAD_H (*(volatile unsigned short *)(GBA_REG_DMA1DAD_H_ADDR)) |
|---|
| 650 | #define GBA_REG_DMA1CNT (*(volatile unsigned int *)(GBA_REG_DMA1CNT_ADDR)) |
|---|
| 651 | #define GBA_REG_DMA1CNT_L (*(volatile unsigned short *)(GBA_REG_DMA1CNT_L_ADDR)) |
|---|
| 652 | #define GBA_REG_DMA1CNT_H (*(volatile unsigned short *)(GBA_REG_DMA1CNT_H_ADDR)) |
|---|
| 653 | #define GBA_REG_DMA2SAD (*(volatile unsigned int *)(GBA_REG_DMA2SAD_ADDR)) |
|---|
| 654 | #define GBA_REG_DMA2SAD_L (*(volatile unsigned short *)(GBA_REG_DMA2SAD_L_ADDR)) |
|---|
| 655 | #define GBA_REG_DMA2SAD_H (*(volatile unsigned short *)(GBA_REG_DMA2SAD_H_ADDR)) |
|---|
| 656 | #define GBA_REG_DMA2DAD (*(volatile unsigned int *)(GBA_REG_DMA2DAD_ADDR)) |
|---|
| 657 | #define GBA_REG_DMA2DAD_L (*(volatile unsigned short *)(GBA_REG_DMA2DAD_L_ADDR)) |
|---|
| 658 | #define GBA_REG_DMA2DAD_H (*(volatile unsigned short *)(GBA_REG_DMA2DAD_H_ADDR)) |
|---|
| 659 | #define GBA_REG_DMA2CNT (*(volatile unsigned int *)(GBA_REG_DMA2CNT_ADDR)) |
|---|
| 660 | #define GBA_REG_DMA2CNT_L (*(volatile unsigned short *)(GBA_REG_DMA2CNT_L_ADDR)) |
|---|
| 661 | #define GBA_REG_DMA2CNT_H (*(volatile unsigned short *)(GBA_REG_DMA2CNT_H_ADDR)) |
|---|
| 662 | #define GBA_REG_DMA3SAD (*(volatile unsigned int *)(GBA_REG_DMA3SAD_ADDR)) |
|---|
| 663 | #define GBA_REG_DMA3SAD_L (*(volatile unsigned short *)(GBA_REG_DMA3SAD_L_ADDR)) |
|---|
| 664 | #define GBA_REG_DMA3SAD_H (*(volatile unsigned short *)(GBA_REG_DMA3SAD_H_ADDR)) |
|---|
| 665 | #define GBA_REG_DMA3DAD (*(volatile unsigned int *)(GBA_REG_DMA3DAD_ADDR)) |
|---|
| 666 | #define GBA_REG_DMA3DAD_L (*(volatile unsigned short *)(GBA_REG_DMA3DAD_L_ADDR)) |
|---|
| 667 | #define GBA_REG_DMA3DAD_H (*(volatile unsigned short *)(GBA_REG_DMA3DAD_H_ADDR)) |
|---|
| 668 | #define GBA_REG_DMA3CNT (*(volatile unsigned int *)(GBA_REG_DMA3CNT_ADDR)) |
|---|
| 669 | #define GBA_REG_DMA3CNT_L (*(volatile unsigned short *)(GBA_REG_DMA3CNT_L_ADDR)) |
|---|
| 670 | #define GBA_REG_DMA3CNT_H (*(volatile unsigned short *)(GBA_REG_DMA3CNT_H_ADDR)) |
|---|
| 671 | #endif |
|---|
| 672 | |
|---|
| 673 | /*---------------------------------------------------------------------------+ |
|---|
| 674 | | TIMER |
|---|
| 675 | +----------------------------------------------------------------------------*/ |
|---|
| 676 | #define GBA_TMR_PRESCALER_1CK 0x0000 /**< Prescaler 1 clock */ |
|---|
| 677 | #define GBA_TMR_PRESCALER_64CK 0x0001 /**< 64 clocks */ |
|---|
| 678 | #define GBA_TMR_PRESCALER_256CK 0x0002 /**< 256 clocks */ |
|---|
| 679 | #define GBA_TMR_PRESCALER_1024CK 0x0003 /**< 1024 clocks */ |
|---|
| 680 | #define GBA_TMR_IF_ENABLE 0x0040 /**< Interrupt Request Enable */ |
|---|
| 681 | #define GBA_TMR_ENABLE 0x0080 /**< Run Timer */ |
|---|
| 682 | |
|---|
| 683 | /* Timer Register address offsets */ |
|---|
| 684 | #define GBA_TM0D 0x00000100 /**< Timer 0 counter value X*/ |
|---|
| 685 | #define GBA_TM0CNT_L 0x00000100 /**< Timer 0 counter value */ |
|---|
| 686 | #define GBA_TM0CNT 0x00000102 /**< Timer 0 Control X*/ |
|---|
| 687 | #define GBA_TM0CNT_H 0x00000102 /**< Timer 0 Control */ |
|---|
| 688 | #define GBA_TM1D 0x00000104 /**< Timer 1 counter value X*/ |
|---|
| 689 | #define GBA_TM1CNT_L 0x00000104 /**< Timer 1 counter value */ |
|---|
| 690 | #define GBA_TM1CNT 0x00000106 /**< Timer 1 control X*/ |
|---|
| 691 | #define GBA_TM1CNT_H 0x00000106 /**< Timer 1 control */ |
|---|
| 692 | #define GBA_TM2D 0x00000108 /**< Timer 2 counter value X*/ |
|---|
| 693 | #define GBA_TM2CNT_L 0x00000108 /**< Timer 2 counter value */ |
|---|
| 694 | #define GBA_TM2CNT 0x0000010A /**< Timer 2 control X*/ |
|---|
| 695 | #define GBA_TM2CNT_H 0x0000010A /**< Timer 2 control */ |
|---|
| 696 | #define GBA_TM3D 0x0000010C /**< Timer 3 counter value X*/ |
|---|
| 697 | #define GBA_TM3CNT_L 0x0000010C /**< Timer 3 counter value */ |
|---|
| 698 | #define GBA_TM3CNT 0x0000010E /**< Timer 4 control X*/ |
|---|
| 699 | #define GBA_TM3CNT_H 0x0000010E /**< Timer 4 control */ |
|---|
| 700 | /* Timer Register addresses */ |
|---|
| 701 | #define GBA_REG_TM0D_ADDR GBA_IO_REGS_ADDR + GBA_TM0D |
|---|
| 702 | #define GBA_REG_TM0CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_TM0CNT_L |
|---|
| 703 | #define GBA_REG_TM0CNT_ADDR GBA_IO_REGS_ADDR + GBA_TM0CNT |
|---|
| 704 | #define GBA_REG_TM0CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_TM0CNT_H |
|---|
| 705 | #define GBA_REG_TM1D_ADDR GBA_IO_REGS_ADDR + GBA_TM1D |
|---|
| 706 | #define GBA_REG_TM1CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_TM1CNT_L |
|---|
| 707 | #define GBA_REG_TM1CNT_ADDR GBA_IO_REGS_ADDR + GBA_TM1CNT |
|---|
| 708 | #define GBA_REG_TM1CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_TM1CNT_H |
|---|
| 709 | #define GBA_REG_TM2D_ADDR GBA_IO_REGS_ADDR + GBA_TM2D |
|---|
| 710 | #define GBA_REG_TM2CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_TM2CNT_L |
|---|
| 711 | #define GBA_REG_TM2CNT_ADDR GBA_IO_REGS_ADDR + GBA_TM2CNT |
|---|
| 712 | #define GBA_REG_TM2CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_TM2CNT_H |
|---|
| 713 | #define GBA_REG_TM3D_ADDR GBA_IO_REGS_ADDR + GBA_TM3D |
|---|
| 714 | #define GBA_REG_TM3CNT_L_ADDR GBA_IO_REGS_ADDR + GBA_TM3CNT_L |
|---|
| 715 | #define GBA_REG_TM3CNT_ADDR GBA_IO_REGS_ADDR + GBA_TM3CNT |
|---|
| 716 | #define GBA_REG_TM3CNT_H_ADDR GBA_IO_REGS_ADDR + GBA_TM3CNT_H |
|---|
| 717 | /* Timer Registers */ |
|---|
| 718 | #ifndef __asm__ |
|---|
| 719 | #define GBA_REG_TM0D (*(volatile unsigned short *)(GBA_REG_TM0D_ADDR)) |
|---|
| 720 | #define GBA_REG_TM0CNT_L (*(volatile unsigned short *)(GBA_REG_TM0CNT_L_ADDR)) |
|---|
| 721 | #define GBA_REG_TM0CNT (*(volatile unsigned short *)(GBA_REG_TM0CNT_ADDR)) |
|---|
| 722 | #define GBA_REG_TM0CNT_H (*(volatile unsigned short *)(GBA_REG_TM0CNT_H_ADDR)) |
|---|
| 723 | #define GBA_REG_TM1D (*(volatile unsigned short *)(GBA_REG_TM1D_ADDR)) |
|---|
| 724 | #define GBA_REG_TM1CNT_L (*(volatile unsigned short *)(GBA_REG_TM1CNT_L_ADDR)) |
|---|
| 725 | #define GBA_REG_TM1CNT (*(volatile unsigned short *)(GBA_REG_TM1CNT_ADDR)) |
|---|
| 726 | #define GBA_REG_TM1CNT_H (*(volatile unsigned short *)(GBA_REG_TM1CNT_H_ADDR)) |
|---|
| 727 | #define GBA_REG_TM2D (*(volatile unsigned short *)(GBA_REG_TM2D_ADDR)) |
|---|
| 728 | #define GBA_REG_TM2CMT_L (*(volatile unsigned short *)(GBA_REG_TM2CNT_L_ADDR)) |
|---|
| 729 | #define GBA_REG_TM2CNT (*(volatile unsigned short *)(GBA_REG_TM2CNT_ADDR)) |
|---|
| 730 | #define GBA_REG_TM2CNT_H (*(volatile unsigned short *)(GBA_REG_TM2CNT_H_ADDR)) |
|---|
| 731 | #define GBA_REG_TM3D (*(volatile unsigned short *)(GBA_REG_TM3D_ADDR)) |
|---|
| 732 | #define GBA_REG_TM3CNT_L (*(volatile unsigned short *)(GBA_REG_TM3CNT_L_ADDR)) |
|---|
| 733 | #define GBA_REG_TM3CNT (*(volatile unsigned short *)(GBA_REG_TM3CNT_ADDR)) |
|---|
| 734 | #define GBA_REG_TM3CNT_H (*(volatile unsigned short *)(GBA_REG_TM3CNT_H_ADDR)) |
|---|
| 735 | #endif |
|---|
| 736 | |
|---|
| 737 | /*---------------------------------------------------------------------------+ |
|---|
| 738 | | SERIAL set1 |
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| 739 | +----------------------------------------------------------------------------*/ |
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| 740 | #define GBA_SER_BAUD_MASK 0x0003 |
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| 741 | #define GBA_SER_BAUD_9600 0x0000 |
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| 742 | #define GBA_SER_BAUD_38400 0x0001 |
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| 743 | #define GBA_SER_BAUD_57600 0x0002 |
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| 744 | #define GBA_SER_BAUD_115200 0x0003 |
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| 745 | #define GBA_SER_CTS 0x0004 |
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| 746 | |
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| 747 | /* Serial Communication address offsets */ |
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| 748 | #define GBA_SIOMULTI0 0x00000120 /**< SIO Multi-Player Data 0 */ |
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| 749 | #define GBA_SCD0 0x00000120 /**< SIO Multi-Player Data 0 X*/ |
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| 750 | #define GBA_SIOMULTI1 0x00000122 /**< SIO Multi-Player Data 1 */ |
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| 751 | #define GBA_SCD1 0x00000122 /**< SIO Multi-Player Data 1 X*/ |
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| 752 | #define GBA_SIOMULTI2 0x00000124 /**< SIO Multi-Player Data 2 */ |
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| 753 | #define GBA_SCD2 0x00000124 /**< SIO Multi-Player Data 2 X*/ |
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| 754 | #define GBA_SIOMULTI3 0x00000126 /**< SIO Multi-Player Data 3 */ |
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| 755 | #define GBA_SCD3 0x00000126 /**< SIO Multi-Player Data 3 X*/ |
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| 756 | #define GBA_SIOCNT 0x00000128 /**< SIO Control */ |
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| 757 | #define GBA_SCCNT 0x00000128 /**< SIO Control X*/ |
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| 758 | #define GBA_SCCNT_L 0x00000128 /**< SIO Control X*/ |
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| 759 | #define GBA_SIOMLT_SEND 0x0000012A /**< Data Send Register */ |
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| 760 | #define GBA_SCCNT_H 0x0000012A /**< Data Send Register X*/ |
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| 761 | /* Serial Communication addresses */ |
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| 762 | #define GBA_REG_SIOMULTI0_ADDR GBA_IO_REGS_ADDR + GBA_SIOMULTI0 |
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| 763 | #define GBA_REG_SCD0_ADDR GBA_IO_REGS_ADDR + GBA_SCD0 |
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| 764 | #define GBA_REG_SIOMULTI1_ADDR GBA_IO_REGS_ADDR + GBA_SIOMULTI1 |
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| 765 | #define GBA_REG_SCD1_ADDR GBA_IO_REGS_ADDR + GBA_SCD1 |
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| 766 | #define GBA_REG_SIOMULTI2_ADDR GBA_IO_REGS_ADDR + GBA_SIOMULTI2 |
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| 767 | #define GBA_REG_SCD2_ADDR GBA_IO_REGS_ADDR + GBA_SCD2 |
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| 768 | #define GBA_REG_SIOMULTI3_ADDR GBA_IO_REGS_ADDR + GBA_SIOMULTI3 |
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| 769 | #define GBA_REG_SCD3_ADDR GBA_IO_REGS_ADDR + GBA_SCD3 |
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| 770 | #define GBA_REG_SCCNT_ADDR GBA_IO_REGS_ADDR + GBA_SCCNT |
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| 771 | #define GBA_REG_SIOCNT_ADDR GBA_IO_REGS_ADDR + GBA_SIOCNT |
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| 772 | #define GBA_REG_SCCNT_L_ADDR GBA_IO_REGS_ADDR + GBA_SCCNT_L |
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| 773 | #define GBA_REG_SIOMLT_SEND_ADDR GBA_IO_REGS_ADDR + GBA_SIOMLT_SEND |
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| 774 | #define GBA_REG_SCCNT_H_ADDR GBA_IO_REGS_ADDR + GBA_SCCNT_H |
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| 775 | /* Serial Communication registers */ |
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| 776 | #ifndef __asm__ |
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| 777 | #define GBA_REG_SIOMULTI0 (*(volatile unsigned short *)(GBA_REG_SIOMULTI0_ADDR)) |
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| 778 | #define GBA_REG_SCD0 (*(volatile unsigned short *)(GBA_REG_SCD0_ADDR)) |
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| 779 | #define GBA_REG_SIOMULTI1 (*(volatile unsigned short *)(GBA_REG_SIOMULTI1_ADDR)) |
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| 780 | #define GBA_REG_SCD1 (*(volatile unsigned short *)(GBA_REG_SCD1_ADDR)) |
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| 781 | #define GBA_REG_SIOMULTI2 (*(volatile unsigned short *)(GBA_REG_SIOMULTI2_ADDR)) |
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| 782 | #define GBA_REG_SCD2 (*(volatile unsigned short *)(GBA_REG_SCD2_ADDR)) |
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| 783 | #define GBA_REG_SIOMULTI3 (*(volatile unsigned short *)(GBA_REG_SIOMULTI3_ADDR)) |
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| 784 | #define GBA_REG_SCD3 (*(volatile unsigned short *)(GBA_REG_SCD3_ADDR)) |
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| 785 | #define GBA_REG_SCCNT (*(volatile unsigned int *)(GBA_REG_SCCNT_ADDR)) |
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| 786 | #define GBA_REG_SIOCNT (*(volatile unsigned short *)(GBA_REG_SIOCNT_ADDR)) |
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| 787 | #define GBA_REG_SCCNT_L (*(volatile unsigned short *)(GBA_REG_SCCNT_L_ADDR)) |
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| 788 | #define GBA_REG_SIOMLT_SEND (*(volatile unsigned short *)(GBA_REG_SIOMLT_SEND_ADDR)) |
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| 789 | #define GBA_REG_SCCNT_H (*(volatile unsigned short *)(GBA_REG_SCCNT_H_ADDR)) |
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| 790 | #endif |
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| 791 | |
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| 792 | /*---------------------------------------------------------------------------+ |
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| 793 | | KEYPAD |
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| 794 | +----------------------------------------------------------------------------*/ |
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| 795 | /* GBA Keys */ |
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| 796 | #define GBA_KEY_A 0x0001 |
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| 797 | #define GBA_KEY_B 0x0002 |
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| 798 | #define GBA_KEY_SELECT 0x0004 |
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| 799 | #define GBA_KEY_START 0x0008 |
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| 800 | #define GBA_KEY_RIGHT 0x0010 |
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| 801 | #define GBA_KEY_LEFT 0x0020 |
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| 802 | #define GBA_KEY_UP 0x0040 |
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| 803 | #define GBA_KEY_DOWN 0x0080 |
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| 804 | #define GBA_KEY_R 0x0100 |
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| 805 | #define GBA_KEY_L 0x0200 |
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| 806 | #define GBA_KEY_ALL 0x03FF |
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| 807 | /* Keypad registers address offsets */ |
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| 808 | #define GBA_P1 0x00000130 /**< Key Status X*/ |
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| 809 | #define GBA_KEYINPUT 0x00000130 /**< Key Status */ |
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| 810 | #define GBA_P1CNT 0x00000132 /**< Key Interrupt Control X*/ |
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| 811 | #define GBA_KEYCNT 0x00000132 /**< Key Interrupt Control */ |
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| 812 | /* Keypad registers addresses */ |
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| 813 | #define GBA_REG_P1_ADDR GBA_IO_REGS_ADDR + GBA_P1 |
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| 814 | #define GBA_REG_KEYINPUT_ADDR GBA_IO_REGS_ADDR + GBA_KEYINPUT |
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| 815 | #define GBA_REG_P1CNT_ADDR GBA_IO_REGS_ADDR + GBA_P1CNT |
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| 816 | #define GBA_REG_KEYCNT_ADDR GBA_IO_REGS_ADDR + GBA_KEYCNT |
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| 817 | /* Keypad registers */ |
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| 818 | #ifndef __asm__ |
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| 819 | #define GBA_REG_P1 (*(volatile unsigned short *)(GBA_REG_P1_ADDR)) |
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| 820 | #define GBA_REG_KEYINPUT (*(volatile unsigned short *)(GBA_REG_KEYINPUT_ADDR)) |
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| 821 | #define GBA_REG_P1CNT (*(volatile unsigned short *)(GBA_REG_P1CNT_ADDR)) |
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| 822 | #define GBA_REG_KEYCNT (*(volatile unsigned short *)(GBA_REG_KEYCNT_ADDR)) |
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| 823 | #endif |
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| 824 | |
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| 825 | /*---------------------------------------------------------------------------+ |
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| 826 | | SERIAL set2 |
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| 827 | +----------------------------------------------------------------------------*/ |
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| 828 | /* Serial Communication address offsets */ |
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| 829 | #define GBA_R 0x00000134 /**< Mode Selection X*/ |
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| 830 | #define GBA_RCNT 0x00000134 /**< Mode Selection */ |
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| 831 | #define GBA_HS_CTRL 0x00000140 /**< JOY BUS Control Register X*/ |
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| 832 | #define GBA_JOYCNT 0x00000140 /**< JOY BUS Control Register */ |
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| 833 | #define GBA_JOYRE 0x00000150 /**< Receive Data Register X*/ |
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| 834 | #define GBA_JOYRE_L 0x00000150 /**< Receive Data Register low X*/ |
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| 835 | #define GBA_JOY_RECV_L 0x00000150 /**< Receive Data Register low */ |
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| 836 | #define GBA_JOYRE_H 0x00000152 /**< Receive Data Register high X*/ |
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| 837 | #define GBA_JOY_RECV_H 0x00000152 /**< Receive Data Register high */ |
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| 838 | #define GBA_JOYTR 0x00000154 /**< Send Data Register X*/ |
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| 839 | #define GBA_JOYTR_L 0x00000154 /**< Send Data Register low X*/ |
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| 840 | #define GBA_JOY_TRANS_L 0x00000154 /**< Send Data Register low */ |
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| 841 | #define GBA_JOYTR_H 0x00000156 /**< Send Data Register high X*/ |
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| 842 | #define GBA_JOY_TRANS_H 0x00000156 /**< Send Data Register high */ |
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| 843 | #define GBA_JSTAT 0x00000158 /**< Receive Status Register X*/ |
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| 844 | #define GBA_JOYSTAT 0x00000158 /**< Receive Status Register */ |
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| 845 | /* Serial Communication register addresses */ |
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| 846 | #define GBA_REG_R_ADDR GBA_IO_REGS_ADDR + GBA_R |
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| 847 | #define GBA_REG_RCNT_ADDR GBA_IO_REGS_ADDR + GBA_RCNT |
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| 848 | #define GBA_REG_HS_CTRL_ADDR GBA_IO_REGS_ADDR + GBA_HS_CTRL |
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| 849 | #define GBA_REG_JOYCNT_ADDR GBA_IO_REGS_ADDR + GBA_JOYCNT |
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| 850 | #define GBA_REG_JOYRE_ADDR GBA_IO_REGS_ADDR + GBA_JOYRE |
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| 851 | #define GBA_REG_JOYRE_L_ADDR GBA_IO_REGS_ADDR + GBA_JOYRE_L |
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| 852 | #define GBA_REG_JOY_RECV_L_ADDR GBA_IO_REGS_ADDR + GBA_JOY_RECV_L |
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| 853 | #define GBA_REG_JOYRE_H_ADDR GBA_IO_REGS_ADDR + GBA_JOYRE_H |
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| 854 | #define GBA_REG_JOY_RECV_H_ADDR GBA_IO_REGS_ADDR + GBA_JOY_RECV_H |
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| 855 | #define GBA_REG_JOYTR_ADDR GBA_IO_REGS_ADDR + GBA_JOYTR |
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| 856 | #define GBA_REG_JOYTR_L_ADDR GBA_IO_REGS_ADDR + GBA_JOYTR_L |
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| 857 | #define GBA_REG_JOY_TRANS_L_ADDR GBA_IO_REGS_ADDR + GBA_JOY_TRANS_L |
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| 858 | #define GBA_REG_JOYTR_H_ADDR GBA_IO_REGS_ADDR + GBA_JOYTR_H |
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| 859 | #define GBA_REG_JOY_TRANS_H_ADDR GBA_IO_REGS_ADDR + GBA_JOY_TRANS_H |
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| 860 | #define GBA_REG_JSTAT_ADDR GBA_IO_REGS_ADDR + GBA_JSTAT |
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| 861 | #define GBA_REG_JOYSTAT_ADDR GBA_IO_REGS_ADDR + GBA_JOYSTAT |
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| 862 | /* Serial Communication registers */ |
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| 863 | #ifndef __asm__ |
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| 864 | #define GBA_REG_R (*(volatile unsigned short *)(GBA_REG_R_ADDR)) |
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| 865 | #define GBA_REG_RCNT (*(volatile unsigned short *)(GBA_REG_RCNT_ADDR)) |
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| 866 | #define GBA_REG_HS_CTRL (*(volatile unsigned short *)(GBA_REG_HS_CTRL_ADDR)) |
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| 867 | #define GBA_REG_JOYCNT (*(volatile unsigned short *)(GBA_REG_JOYCNT_ADDR)) |
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| 868 | #define GBA_REG_JOYRE (*(volatile unsigned int *)(GBA_REG_JOYRE_ADDR)) |
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| 869 | #define GBA_REG_JOYRE_L (*(volatile unsigned short *)(GBA_REG_JOYRE_L_ADDR)) |
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| 870 | #define GBA_REG_JOY_RECV_L (*(volatile unsigned short *)(GBA_REG_JOY_RECV_L_ADDR)) |
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| 871 | #define GBA_REG_JOYRE_H (*(volatile unsigned short *)(GBA_REG_JOYRE_H_ADDR)) |
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| 872 | #define GBA_REG_JOY_RECV_H (*(volatile unsigned short *)(GBA_REG_JOY_RECV_H_ADDR)) |
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| 873 | #define GBA_REG_JOYTR (*(volatile unsigned int *)(GBA_REG_JOYTR_ADDR)) |
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| 874 | #define GBA_REG_JOYTR_L (*(volatile unsigned short *)(GBA_REG_JOYTR_L_ADDR)) |
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| 875 | #define GBA_REG_JOY_TRANS_L (*(volatile unsigned short *)(GBA_REG_JOY_TRANS_L_ADDR)) |
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| 876 | #define GBA_REG_JOYTR_H (*(volatile unsigned short *)(GBA_REG_JOYTR_H_ADDR)) |
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| 877 | #define GBA_REG_JOY_TRANS_H (*(volatile unsigned short *)(GBA_REG_JOY_TRANS_H_ADDR)) |
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| 878 | #define GBA_REG_JSTAT (*(volatile unsigned int *)(GBA_REG_JSTAT_ADDR)) |
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| 879 | #define GBA_REG_JOYSTAT (*(volatile unsigned short *)(GBA_REG_JOYSTAT_ADDR)) |
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| 880 | #endif |
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| 881 | |
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| 882 | /*---------------------------------------------------------------------------+ |
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| 883 | | INTERRUPT |
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| 884 | +----------------------------------------------------------------------------*/ |
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| 885 | /* Interrupt sources */ |
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| 886 | #define GBA_INT_VBLANK 0x0001 |
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| 887 | #define GBA_INT_HBLANK 0x0002 |
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| 888 | #define GBA_INT_VCOUNT 0x0004 |
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| 889 | #define GBA_INT_TIMER0 0x0008 |
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| 890 | #define GBA_INT_TIMER1 0x0010 |
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| 891 | #define GBA_INT_TIMER2 0x0020 |
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| 892 | #define GBA_INT_TIMER3 0x0040 |
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| 893 | #define GBA_INT_SERIAL 0x0080 |
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| 894 | #define GBA_INT_DMA0 0x0100 |
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| 895 | #define GBA_INT_DMA1 0x0200 |
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| 896 | #define GBA_INT_DMA2 0x0400 |
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| 897 | #define GBA_INT_DMA3 0x0800 |
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| 898 | #define GBA_INT_KEY 0x1000 |
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| 899 | #define GBA_INT_CART 0x2000 |
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| 900 | /* Interrupt address offsets */ |
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| 901 | #define GBA_IE 0x00000200 /**< Interrupt Enable */ |
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| 902 | #define GBA_IF 0x00000202 /**< Interrupt Flags */ |
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| 903 | #define GBA_IME 0x00000208 /**< Interrupt Master Enable */ |
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| 904 | /* Interrupt addresses */ |
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| 905 | #define GBA_REG_IE_ADDR GBA_IO_REGS_ADDR + GBA_IE |
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| 906 | #define GBA_REG_IF_ADDR GBA_IO_REGS_ADDR + GBA_IF |
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| 907 | #define GBA_REG_IME_ADDR GBA_IO_REGS_ADDR + GBA_IME |
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| 908 | /* Interrupt registers */ |
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| 909 | #ifndef __asm__ |
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| 910 | #define GBA_REG_IE (*(volatile unsigned short *)(GBA_REG_IE_ADDR)) |
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| 911 | #define GBA_REG_IF (*(volatile unsigned short *)(GBA_REG_IF_ADDR)) |
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| 912 | #define GBA_REG_IME (*(volatile unsigned short *)(GBA_REG_IME_ADDR)) |
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| 913 | #endif |
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| 914 | |
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| 915 | /*---------------------------------------------------------------------------+ |
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| 916 | | Waitstate and Power-Down Control registers |
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| 917 | +----------------------------------------------------------------------------*/ |
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| 918 | #define GBA_PHI_MASK 0x1800 |
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| 919 | #define GBA_PHI_NONE 0x0000 |
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| 920 | #define GBA_PHI_4_19MHZ 0x0800 |
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| 921 | #define GBA_PHI_8_38MHZ 0x1000 |
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| 922 | #define GBA_PHI_16_76MHZ 0x1800 |
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| 923 | /* Waitstate and Power-Down Control address offsets */ |
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| 924 | #define GBA_WSCNT 0x00000204 /**< Waitstate Control X*/ |
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| 925 | #define GBA_WAITCNT 0x00000204 /**< Waitstate Control */ |
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| 926 | #define GBA_PAUSE 0x00000300 /**< Power Down Control X*/ |
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| 927 | #define GBA_HALTCNT 0x00000300 /**< Power Down Control */ |
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| 928 | /* Waitstate and Power-Down Control addresses */ |
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| 929 | #define GBA_REG_WSCNT_ADDR GBA_IO_REGS_ADDR + GBA_WSCNT |
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| 930 | #define GBA_REG_WAITCNT_ADDR GBA_IO_REGS_ADDR + GBA_WAITCNT |
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| 931 | #define GBA_REG_PAUSE_ADDR GBA_IO_REGS_ADDR + GBA_PAUSE |
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| 932 | #define GBA_REG_HALTCNT_ADDR GBA_IO_REGS_ADDR + GBA_HALTCNT |
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| 933 | /* Waitstate and Power-Down Control registers */ |
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| 934 | #ifndef __asm__ |
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| 935 | #define GBA_REG_WSCNT (*(volatile unsigned short *)(GBA_REG_WSCNT_ADDR)) |
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| 936 | #define GBA_REG_WAITCNT (*(volatile unsigned short *)(GBA_REG_WAITCNT_ADDR)) |
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| 937 | #define GBA_REG_PAUSE (*(volatile unsigned short *)(GBA_REG_PAUSE_ADDR)) |
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| 938 | #define GBA_REG_HALTCNT (*(volatile unsigned short *)(GBA_REG_HALTCNT_ADDR)) |
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| 939 | #endif |
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| 940 | |
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| 941 | |
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| 942 | /* |
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| 943 | * @TODO remove UART register defines |
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| 944 | * define for RTEMS UART registers to be able to compile |
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| 945 | */ |
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| 946 | #define RSRBR 0 |
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| 947 | #define RSTHR 1 |
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| 948 | #define RSIER 2 |
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| 949 | #define RSIIR 3 |
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| 950 | #define RSFCR 4 |
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| 951 | #define RSLCR 5 |
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| 952 | #define RSLSR 6 |
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| 953 | #define RSDLL 7 |
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| 954 | #define RSDLH 8 |
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| 955 | #define RSCNT 9 |
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| 956 | |
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| 957 | |
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| 958 | #endif /* _GBA_REGISTERS_H */ |
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