1 | /* |
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2 | * Cirrus EP7312 Startup code |
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3 | * |
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4 | * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> |
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5 | * |
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6 | * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com> |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | * |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | |
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18 | /* Some standard definitions...*/ |
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19 | |
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20 | .equ Mode_USR, 0x10 |
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21 | .equ Mode_FIQ, 0x11 |
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22 | .equ Mode_IRQ, 0x12 |
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23 | .equ Mode_SVC, 0x13 |
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24 | .equ Mode_ABT, 0x17 |
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25 | .equ Mode_ABORT, 0x17 |
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26 | .equ Mode_UNDEF, 0x1B |
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27 | .equ Mode_SYS, 0x1F /*only available on ARM Arch. v4*/ |
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28 | |
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29 | .equ I_Bit, 0x80 |
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30 | .equ F_Bit, 0x40 |
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31 | |
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32 | |
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33 | .text |
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34 | .globl _start |
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35 | |
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36 | |
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37 | _start: |
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38 | /* store the sp */ |
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39 | mov r12, sp |
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40 | /* |
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41 | * Here is the code to initialize the low-level BSP environment |
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42 | * (Chip Select, PLL, ....?) |
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43 | |
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44 | |
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45 | /* zero the bss */ |
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46 | LDR r1, =_bss_end_ /* get end of ZI region */ |
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47 | LDR r0, =_bss_start_ /* load base address of ZI region */ |
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48 | |
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49 | zi_init: |
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50 | MOV r2, #0 |
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51 | CMP r0, r1 /* loop whilst r0 < r1 */ |
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52 | STRLOT r2, [r0], #4 |
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53 | BLO zi_init |
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54 | |
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55 | /* Load basic ARM7 interrupt table */ |
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56 | VectorInit: |
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57 | MOV R0, #0 |
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58 | ADR R1, Vector_Init_Block |
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59 | LDMIA R1!, {R2, r3} /* Copy the Vectors (8 words) */ |
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60 | STMIA R0!, {r2, r3} |
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61 | LDMIA R1!, {R2, r3} /* Copy the Vectors (8 words) */ |
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62 | STMIA R0!, {r2, r3} |
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63 | LDMIA R1!, {R2, r3} /* Copy the Vectors (8 words) */ |
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64 | STMIA R0!, {r2, r3} |
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65 | LDMIA R1!, {R2, r3} /* Copy the Vectors (8 words) */ |
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66 | STMIA R0!, {r2, r3} |
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67 | |
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68 | LDMIA R1!, {R2, r3} /* Copy the .long'ed addresses (8 words) */ |
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69 | STMIA R0!, {r2, r3} |
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70 | LDMIA R1!, {R2, r3} /* Copy the .long'ed addresses (8 words) */ |
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71 | STMIA R0!, {r2, r3} |
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72 | LDMIA R1!, {R2, r3} /* Copy the .long'ed addresses (8 words) */ |
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73 | STMIA R0!, {r2, r3} |
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74 | LDMIA R1!, {R2, r3} /* Copy the .long'ed addresses (8 words) */ |
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75 | STMIA R0!, {r2, r3} |
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76 | |
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77 | B init2 |
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78 | |
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79 | /******************************************************* |
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80 | standard exception vectors table |
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81 | *** Must be located at address 0 |
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82 | ********************************************************/ |
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83 | |
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84 | Vector_Init_Block: |
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85 | LDR PC, Reset_Addr |
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86 | LDR PC, Undefined_Addr |
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87 | LDR PC, SWI_Addr |
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88 | LDR PC, Prefetch_Addr |
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89 | LDR PC, Abort_Addr |
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90 | NOP |
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91 | LDR PC, IRQ_Addr |
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92 | LDR PC, FIQ_Addr |
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93 | |
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94 | .globl Reset_Addr |
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95 | Reset_Addr: .long _start |
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96 | Undefined_Addr: .long Undefined_Handler |
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97 | SWI_Addr: .long SWI_Handler |
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98 | Prefetch_Addr: .long Prefetch_Handler |
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99 | Abort_Addr: .long Abort_Handler |
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100 | .long 0 |
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101 | IRQ_Addr: .long IRQ_Handler |
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102 | FIQ_Addr: .long FIQ_Handler |
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103 | |
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104 | /* The following handlers do not do anything useful */ |
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105 | .globl Undefined_Handler |
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106 | Undefined_Handler: |
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107 | B Undefined_Handler |
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108 | .globl SWI_Handler |
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109 | SWI_Handler: |
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110 | B SWI_Handler |
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111 | .globl Prefetch_Handler |
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112 | Prefetch_Handler: |
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113 | B Prefetch_Handler |
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114 | .globl Abort_Handler |
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115 | Abort_Handler: |
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116 | B Abort_Handler |
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117 | .globl IRQ_Handler |
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118 | IRQ_Handler: |
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119 | B IRQ_Handler |
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120 | .globl FIQ_Handler |
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121 | FIQ_Handler: |
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122 | B FIQ_Handler |
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123 | |
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124 | init2 : |
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125 | /* --- Initialise stack pointer registers |
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126 | |
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127 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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128 | MOV r0, #Mode_IRQ | I_Bit | F_Bit /* No interrupts */ |
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129 | MSR cpsr, r0 |
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130 | ldr r1, =_irq_stack_size |
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131 | LDR sp, =_irq_stack |
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132 | add sp, sp, r1 |
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133 | sub sp, sp, #0x64 |
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134 | |
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135 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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136 | MOV r0, #Mode_FIQ | I_Bit | F_Bit /* No interrupts */ |
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137 | MSR cpsr, r0 |
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138 | ldr r1, =_fiq_stack_size |
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139 | LDR sp, =_fiq_stack |
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140 | add sp, sp, r1 |
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141 | sub sp, sp, #0x64 |
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142 | |
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143 | /* Enter ABT mode and set up the ABT stack pointer */ |
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144 | MOV r0, #Mode_ABT | I_Bit | F_Bit /* No interrupts */ |
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145 | MSR cpsr, r0 |
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146 | ldr r1, =_abt_stack_size |
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147 | LDR sp, =_abt_stack |
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148 | add sp, sp, r1 |
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149 | sub sp, sp, #0x64 |
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150 | |
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151 | /* Set up the SVC stack pointer last and stay in SVC mode */ |
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152 | MOV r0, #Mode_SVC | I_Bit | F_Bit /* No interrupts */ |
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153 | MSR cpsr, r0 |
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154 | ldr r1, =_svc_stack_size |
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155 | LDR sp, =_svc_stack |
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156 | add sp, sp, r1 |
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157 | sub sp, sp, #0x64 |
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158 | |
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159 | /* save the original registers */ |
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160 | stmdb sp!, {r4-r12, lr} |
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161 | |
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162 | /* --- Now we enter the C code */ |
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163 | |
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164 | bl boot_card |
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165 | |
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166 | ldmia sp!, {r4-r12, lr} |
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167 | mov sp, r12 |
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168 | mov pc, lr |
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169 | |
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170 | |
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