source: rtems/c/src/lib/libbsp/arm/edb7312/start/start.S @ ae8cfc69

Last change on this file since ae8cfc69 was ae8cfc69, checked in by Joel Sherrill <joel.sherrill@…>, on 09/04/03 at 18:43:48

2003-09-04 Joel Sherrill <joel@…>

  • clock/clockdrv.c, console/uart.c, include/bsp.h, include/ep7312.h, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, start/start.S, startup/bspstart.c, startup/exit.c, startup/linkcmds, timer/timer.c: URL for license changed.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 * Cirrus EP7312 Startup code
3 *
4 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
5 *     
6 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *
11 *  http://www.rtems.com/license/LICENSE.
12 *
13 *
14 *  $Id$
15*/
16
17               
18/* Some standard definitions...*/
19
20.equ Mode_USR,               0x10
21.equ Mode_FIQ,               0x11
22.equ Mode_IRQ,               0x12
23.equ Mode_SVC,               0x13
24.equ Mode_ABT,               0x17
25.equ Mode_ABORT,             0x17
26.equ Mode_UNDEF,             0x1B
27.equ Mode_SYS,               0x1F /*only available on ARM Arch. v4*/
28
29.equ I_Bit,                  0x80
30.equ F_Bit,                  0x40
31
32
33        .text
34        .globl  _start
35
36         
37_start:
38        /* store the sp */
39        mov     r12, sp
40/*
41 * Here is the code to initialize the low-level BSP environment
42 * (Chip Select, PLL, ....?)
43
44       
45/* zero the bss */
46        LDR     r1, =_bss_end_       /* get end of ZI region */
47        LDR     r0, =_bss_start_     /* load base address of ZI region */
48
49zi_init:       
50        MOV     r2, #0
51        CMP     r0, r1                 /* loop whilst r0 < r1 */
52        STRLOT   r2, [r0], #4
53        BLO     zi_init
54       
55/* Load basic ARM7 interrupt table */
56VectorInit:     
57        MOV     R0, #0
58        ADR     R1, Vector_Init_Block
59        LDMIA   R1!, {R2, r3}   /* Copy the Vectors (8 words) */
60        STMIA   R0!, {r2, r3}
61        LDMIA   R1!, {R2, r3}   /* Copy the Vectors (8 words) */
62        STMIA   R0!, {r2, r3}
63        LDMIA   R1!, {R2, r3}   /* Copy the Vectors (8 words) */
64        STMIA   R0!, {r2, r3}
65        LDMIA   R1!, {R2, r3}   /* Copy the Vectors (8 words) */
66        STMIA   R0!, {r2, r3}
67
68        LDMIA   R1!, {R2, r3}   /* Copy the .long'ed addresses (8 words) */
69        STMIA   R0!, {r2, r3}
70        LDMIA   R1!, {R2, r3}   /* Copy the .long'ed addresses (8 words) */
71        STMIA   R0!, {r2, r3}
72        LDMIA   R1!, {R2, r3}   /* Copy the .long'ed addresses (8 words) */
73        STMIA   R0!, {r2, r3}
74        LDMIA   R1!, {R2, r3}   /* Copy the .long'ed addresses (8 words) */
75        STMIA   R0!, {r2, r3}
76
77        B       init2
78
79/*******************************************************
80 standard exception vectors table
81 *** Must be located at address 0
82********************************************************/       
83
84Vector_Init_Block:     
85        LDR     PC, Reset_Addr
86        LDR     PC, Undefined_Addr
87        LDR     PC, SWI_Addr
88        LDR     PC, Prefetch_Addr
89        LDR     PC, Abort_Addr
90        NOP
91        LDR     PC, IRQ_Addr
92        LDR     PC, FIQ_Addr
93
94        .globl Reset_Addr
95Reset_Addr:     .long   _start
96Undefined_Addr: .long   Undefined_Handler
97SWI_Addr:       .long   SWI_Handler
98Prefetch_Addr:  .long   Prefetch_Handler
99Abort_Addr:     .long   Abort_Handler
100                .long   0       
101IRQ_Addr:       .long   IRQ_Handler
102FIQ_Addr:       .long   FIQ_Handler
103       
104/* The following handlers do not do anything useful */
105        .globl Undefined_Handler
106Undefined_Handler:     
107        B       Undefined_Handler
108        .globl SWI_Handler
109SWI_Handler:   
110        B       SWI_Handler
111        .globl Prefetch_Handler
112Prefetch_Handler:       
113        B       Prefetch_Handler
114        .globl Abort_Handler
115Abort_Handler: 
116        B       Abort_Handler
117        .globl IRQ_Handler
118IRQ_Handler:   
119        B       IRQ_Handler
120        .globl FIQ_Handler
121FIQ_Handler:   
122        B       FIQ_Handler
123
124init2 :
125/* --- Initialise stack pointer registers
126       
127/* Enter IRQ mode and set up the IRQ stack pointer */
128    MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
129    MSR     cpsr, r0
130    ldr     r1, =_irq_stack_size
131    LDR     sp, =_irq_stack
132    add     sp, sp, r1
133    sub     sp, sp, #0x64       
134
135/* Enter FIQ mode and set up the FIQ stack pointer */
136    MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
137    MSR     cpsr, r0
138    ldr     r1, =_fiq_stack_size
139    LDR     sp, =_fiq_stack
140    add     sp, sp, r1
141    sub     sp, sp, #0x64       
142
143/* Enter ABT mode and set up the ABT stack pointer */
144    MOV     r0, #Mode_ABT | I_Bit | F_Bit     /* No interrupts */
145    MSR     cpsr, r0
146    ldr     r1, =_abt_stack_size
147    LDR     sp, =_abt_stack
148    add     sp, sp, r1
149    sub     sp, sp, #0x64       
150       
151/* Set up the SVC stack pointer last and stay in SVC mode */
152    MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
153    MSR     cpsr, r0
154    ldr     r1, =_svc_stack_size
155    LDR     sp, =_svc_stack
156    add     sp, sp, r1
157    sub     sp, sp, #0x64       
158
159        /* save the original registers */
160        stmdb   sp!, {r4-r12, lr}
161
162/* --- Now we enter the C code */
163
164    bl  boot_card
165
166        ldmia   sp!, {r4-r12, lr}
167        mov     sp, r12
168        mov     pc, lr
169
170
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