source: rtems/c/src/lib/libbsp/arm/edb7312/start/start.S @ 8d992be9

4.115
Last change on this file since 8d992be9 was 8d992be9, checked in by Sebastian Huber <sebastian.huber@…>, on 12/03/10 at 10:52:07

2010-12-03 Sebastian Huber <sebastian.huber@…>

  • bsp_specs, start/start.S, startup/linkcmds: Use linker command base file.
  • Property mode set to 100644
File size: 3.6 KB
Line 
1/*
2 * Cirrus EP7312 Startup code
3 *
4 * Copyright (c) 2010 embedded brains GmbH.
5 *
6 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
7 *
8 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *
16 *  $Id$
17*/
18
19#include <bsp/linker-symbols.h>
20
21/* Some standard definitions...*/
22
23.equ Mode_USR,               0x10
24.equ Mode_FIQ,               0x11
25.equ Mode_IRQ,               0x12
26.equ Mode_SVC,               0x13
27.equ Mode_ABT,               0x17
28.equ Mode_ABORT,             0x17
29.equ Mode_UNDEF,             0x1B
30.equ Mode_SYS,               0x1F /*only available on ARM Arch. v4*/
31
32.equ I_Bit,                  0x80
33.equ F_Bit,                  0x40
34
35.section ".bsp_start_text", "ax"
36.arm
37
38/*******************************************************
39 standard exception vectors table
40 *** Must be located at address 0
41********************************************************/
42
43Vector_Init_Block:
44        LDR     PC, Reset_Addr
45        LDR     PC, Undefined_Addr
46        LDR     PC, SWI_Addr
47        LDR     PC, Prefetch_Addr
48        LDR     PC, Abort_Addr
49        NOP
50        LDR     PC, IRQ_Addr
51        LDR     PC, FIQ_Addr
52
53        .globl Reset_Addr
54Reset_Addr:     .long   _start
55Undefined_Addr: .long   Undefined_Handler
56SWI_Addr:       .long   SWI_Handler
57Prefetch_Addr:  .long   Prefetch_Handler
58Abort_Addr:     .long   Abort_Handler
59                .long   0
60IRQ_Addr:       .long   IRQ_Handler
61FIQ_Addr:       .long   FIQ_Handler
62
63/* The following handlers do not do anything useful */
64        .globl Undefined_Handler
65Undefined_Handler:
66        B       Undefined_Handler
67        .globl SWI_Handler
68SWI_Handler:
69        B       SWI_Handler
70        .globl Prefetch_Handler
71Prefetch_Handler:
72        B       Prefetch_Handler
73        .globl Abort_Handler
74Abort_Handler:
75        B       Abort_Handler
76        .globl IRQ_Handler
77IRQ_Handler:
78        B       IRQ_Handler
79        .globl FIQ_Handler
80FIQ_Handler:
81        B       FIQ_Handler
82
83        .globl  _start
84_start:
85        /* store the sp */
86        mov     r12, sp
87/*
88 * Here is the code to initialize the low-level BSP environment
89 * (Chip Select, PLL, ....?)
90 */
91
92/* zero the bss */
93        LDR     r1, =bsp_section_bss_end   /* get end of ZI region */
94        LDR     r0, =bsp_section_bss_begin /* load base address of ZI region */
95
96zi_init:
97        MOV     r2, #0
98        CMP     r0, r1                 /* loop whilst r0 < r1 */
99        STRLOT   r2, [r0], #4
100        BLO     zi_init
101
102/* --- Initialise stack pointer registers */
103
104/* Enter IRQ mode and set up the IRQ stack pointer */
105    MOV     r0, #Mode_IRQ | I_Bit | F_Bit     /* No interrupts */
106    MSR     cpsr, r0
107    ldr     r1, =bsp_stack_irq_size
108    LDR     sp, =bsp_stack_irq_begin
109    add     sp, sp, r1
110    sub     sp, sp, #0x64
111
112/* Enter FIQ mode and set up the FIQ stack pointer */
113    MOV     r0, #Mode_FIQ | I_Bit | F_Bit     /* No interrupts */
114    MSR     cpsr, r0
115    ldr     r1, =bsp_stack_fiq_size
116    LDR     sp, =bsp_stack_fiq_begin
117    add     sp, sp, r1
118    sub     sp, sp, #0x64
119
120/* Enter ABT mode and set up the ABT stack pointer */
121    MOV     r0, #Mode_ABT | I_Bit | F_Bit     /* No interrupts */
122    MSR     cpsr, r0
123    ldr     r1, =bsp_stack_abt_size
124    LDR     sp, =bsp_stack_abt_begin
125    add     sp, sp, r1
126    sub     sp, sp, #0x64
127
128/* Set up the SVC stack pointer last and stay in SVC mode */
129    MOV     r0, #Mode_SVC | I_Bit | F_Bit     /* No interrupts */
130    MSR     cpsr, r0
131    ldr     r1, =bsp_stack_svc_size
132    LDR     sp, =bsp_stack_svc_begin
133    add     sp, sp, r1
134    sub     sp, sp, #0x64
135
136        /* save the original registers */
137        stmdb   sp!, {r4-r12, lr}
138
139/* --- Now we enter the C code */
140
141        mov     r0, #0
142        bl      boot_card
143
144        ldmia   sp!, {r4-r12, lr}
145        mov     sp, r12
146        mov     pc, lr
Note: See TracBrowser for help on using the repository browser.