source: rtems/c/src/lib/libbsp/arm/edb7312/irq/irq.c @ 0f8ee10e

4.115
Last change on this file since 0f8ee10e was 0f8ee10e, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 20, 2014 at 2:11:41 PM

arm/edb7312: Fix warnings

  • Property mode set to 100644
File size: 3.9 KB
Line 
1/*
2 * Cirrus EP7312 Intererrupt handler
3 */
4
5/*
6 * Copyright (c) 2010 embedded brains GmbH.
7 *
8 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
9 *
10 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15*/
16
17#include <rtems/score/armv4.h>
18
19#include <bsp.h>
20#include <bsp/irq.h>
21#include <bsp/irq-generic.h>
22
23#include <ep7312.h>
24
25void edb7312_interrupt_dispatch(rtems_vector_number vector)
26{
27  bsp_interrupt_handler_dispatch(vector);
28}
29
30rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
31{
32    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
33    {
34        /* interrupt managed by INTMR1 and INTSR1 */
35        *EP7312_INTMR1 |= (1 << vector);
36    }
37    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
38    {
39        /* interrupt managed by INTMR2 and INTSR2 */
40        *EP7312_INTMR2 |= (1 << (vector - 16));
41    }
42    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
43    {
44        /* interrupt managed by INTMR2 and INTSR2 */
45        *EP7312_INTMR2 |= (1 << (vector - 7));
46    }
47    else if(vector == BSP_DAIINT)
48    {
49        /* interrupt managed by INTMR3 and INTSR3 */
50        *EP7312_INTMR3 |= (1 << (vector - 21));
51    }
52
53  return RTEMS_SUCCESSFUL;
54}
55
56rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
57{
58    if(vector >= BSP_EXTFIQ && vector <= BSP_SSEOTI)
59    {
60        /* interrupt managed by INTMR1 and INTSR1 */
61        *EP7312_INTMR1 &= ~(1 << vector);
62    }
63    else if(vector >= BSP_KBDINT && vector <= BSP_SS2TX)
64    {
65        /* interrupt managed by INTMR2 and INTSR2 */
66        *EP7312_INTMR2 &= ~(1 << (vector - 16));
67    }
68    else if(vector >= BSP_UTXINT2 && vector <= BSP_URXINT2)
69    {
70        /* interrupt managed by INTMR2 and INTSR2 */
71        *EP7312_INTMR2 &= ~(1 << (vector - 7));
72    }
73    else if(vector == BSP_DAIINT)
74    {
75        /* interrupt managed by INTMR3 and INTSR3 */
76        *EP7312_INTMR3 &= ~(1 << (vector - 21));
77    }
78
79  return RTEMS_SUCCESSFUL;
80}
81
82rtems_status_code bsp_interrupt_facility_initialize(void)
83{
84  uint32_t int_stat = 0;
85
86  /* mask all interrupts */
87  *EP7312_INTMR1 = 0x0;
88  *EP7312_INTMR2 = 0x0;
89  *EP7312_INTMR3 = 0x0;
90 
91  /* clear all pending interrupt status' */
92  int_stat = *EP7312_INTSR1;
93  if(int_stat & EP7312_INTR1_EXTFIQ)
94  {
95  }
96  if(int_stat & EP7312_INTR1_BLINT)
97  {
98      *EP7312_BLEOI = 0xFFFFFFFF;
99  }
100  if(int_stat & EP7312_INTR1_WEINT)
101  {
102      *EP7312_TEOI = 0xFFFFFFFF;
103  }
104  if(int_stat & EP7312_INTR1_MCINT)
105  {
106  }
107  if(int_stat & EP7312_INTR1_CSINT)
108  {
109      *EP7312_COEOI = 0xFFFFFFFF;
110  }
111  if(int_stat & EP7312_INTR1_EINT1)
112  {
113  }
114  if(int_stat & EP7312_INTR1_EINT2)
115  {
116  }
117  if(int_stat & EP7312_INTR1_EINT3)
118  {
119  }
120  if(int_stat & EP7312_INTR1_TC1OI)
121  {
122      *EP7312_TC1EOI = 0xFFFFFFFF;
123  }
124  if(int_stat & EP7312_INTR1_TC2OI)
125  {
126      *EP7312_TC2EOI = 0xFFFFFFFF;
127  }
128  if(int_stat & EP7312_INTR1_RTCMI)
129  {
130      *EP7312_RTCEOI = 0xFFFFFFFF;
131  }
132  if(int_stat & EP7312_INTR1_TINT)
133  {
134      *EP7312_TEOI = 0xFFFFFFFF;
135  }
136  if(int_stat & EP7312_INTR1_URXINT1)
137  {
138  }
139  if(int_stat & EP7312_INTR1_UTXINT1)
140  {
141  }
142  if(int_stat & EP7312_INTR1_UMSINT)
143  {
144      *EP7312_UMSEOI = 0xFFFFFFFF;
145  }
146  if(int_stat & EP7312_INTR1_SSEOTI)
147  {
148      *EP7312_SYNCIO;
149  }
150  int_stat = *EP7312_INTSR1;
151 
152  int_stat = *EP7312_INTSR2;
153  if(int_stat & EP7312_INTR2_KBDINT)
154  {
155      *EP7312_KBDEOI = 0xFFFFFFFF;
156  }
157  if(int_stat & EP7312_INTR2_SS2RX)
158  {
159  }
160  if(int_stat & EP7312_INTR2_SS2TX)
161  {
162  }
163  if(int_stat & EP7312_INTR2_URXINT2)
164  {
165  }
166  if(int_stat & EP7312_INTR2_UTXINT2)
167  {
168  }
169  int_stat = *EP7312_INTSR2;
170 
171  int_stat = *EP7312_INTSR3;
172  if(int_stat & EP7312_INTR2_DAIINT)
173  {
174  }
175  int_stat = *EP7312_INTSR3;
176
177  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
178
179  return RTEMS_SUCCESSFUL;
180}
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