source: rtems/c/src/lib/libbsp/arm/edb7312/include/ep7312.h @ 9b4422a2

4.11
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 7.5 KB
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1/*
2 * Cirrus EP7312 register declarations
3 *
4 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
5 *
6 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *
13 * Notes: The PLL registers (pll_ro and pll_wo) are either read only
14 *        or write only. The data sheet says not to write the read
15 *        only one or read the write only one. I'm not sure what will
16 *        happen if you do.
17*/
18#ifndef __EP7312_H__
19#define __EP7312_H__
20
21#define EP7312_REG_BASE 0x80000000
22
23#define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
24#define EP7312_PBDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001))
25#define EP7312_PDDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003))
26#define EP7312_PADDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040))
27#define EP7312_PBDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041))
28#define EP7312_PDDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043))
29#define EP7312_PEDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080))
30#define EP7312_PEDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0))
31#define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100))
32#define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140))
33#define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180))
34#define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0))
35#define EP7312_INTSR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240))
36#define EP7312_INTMR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280))
37#define EP7312_LCDCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0))
38#define EP7312_TC1D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300))
39#define EP7312_TC2D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340))
40#define EP7312_RTCDR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380))
41#define EP7312_RTCMR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0))
42#define EP7312_PMPCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400))
43#define EP7312_CODR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440))
44#define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480))
45#define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0))
46#define EP7312_SYNCIO  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500))
47#define EP7312_PALLSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540))
48#define EP7312_PALMSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580))
49#define EP7312_STFCLR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0))
50#define EP7312_BLEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600))
51#define EP7312_MCEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640))
52#define EP7312_TEOI    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680))
53#define EP7312_TC1EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0))
54#define EP7312_TC2EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700))
55#define EP7312_RTCEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740))
56#define EP7312_UMSEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780))
57#define EP7312_COEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0))
58#define EP7312_HALT    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800))
59#define EP7312_STDBY   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840))
60#define EP7312_FBADDR  ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000))
61#define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100))
62#define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140))
63#define EP7312_INTSR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240))
64#define EP7312_INTMR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280))
65#define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480))
66#define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0))
67#define EP7312_SS2DR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500))
68#define EP7312_SRXEOF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600))
69#define EP7312_SS2POP  ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0))
70#define EP7312_KBDEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700))
71#define EP7312_DAIR    ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000))
72#define EP7312_DAIDR0  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040))
73#define EP7312_DAIDR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080))
74#define EP7312_DAIDR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0))
75#define EP7312_DAISR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100))
76#define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200))
77#define EP7312_INTSR3  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240))
78#define EP7312_INTMR3  ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280))
79#define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0))
80#define EP7312_SDCONF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300))
81#define EP7312_SDRFPR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340))
82#define EP7312_UNIQID  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440))
83#define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600))
84#define EP7312_PLLW    ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610))
85#define EP7312_PLLR    ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8))
86#define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700))
87#define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704))
88#define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708))
89#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C))
90
91/* serial port bits */
92/* BITS in UBRLCR1 */
93#define EP7312_UART_WRDLEN5    0x00000000
94#define EP7312_UART_WRDLEN6    0x00020000
95#define EP7312_UART_WRDLEN7    0x00040000
96#define EP7312_UART_WRDLEN8    0x00060000
97#define EP7312_UART_FIFOEN     0x00010000
98#define EP7312_UART_XSTOP      0x00008000
99#define EP7312_UART_EVENPRT    0x00004000
100#define EP7312_UART_PRTEN      0x00002000
101#define EP7312_UART_BREAK      0x00001000
102
103/* BITS in INTSR1 */
104#define EP7312_UART_UTXINT1    0x00002000
105#define EP7312_UART_URXINT1    0x00001000
106
107/* BITS in UARTTDR1 */
108#define EP7312_UART_FRMERR     0x00000100
109#define EP7312_UART_PARERR     0x00000200
110#define EP7312_UART_OVERR      0x00000400
111
112/* BITS in system status flag register 1 */
113#define EP7312_UART_UBUSY1     0x00000800
114#define EP7312_UART_URXFE1     0x00400000
115#define EP7312_UART_UTXFF1     0x00800000
116
117/* system configuration bits */
118/* BITS in SYSCON1 */
119#define EP7312_SYSCON1_UART1EN       0x00000100
120#define EP7312_SYSCON1_TC1_PRESCALE  0x00000010
121#define EP7312_SYSCON1_TC1_512KHZ    0x00000020
122#define EP7312_SYSCON1_TC2_PRESCALE  0x00000040
123#define EP7312_SYSCON1_TC2_512KHZ    0x00000080
124
125/* INTR1 (Interrupt 1) mask/status register bits */
126#define EP7312_INTR1_EXTFIQ  0x00000001
127#define EP7312_INTR1_BLINT   0x00000002
128#define EP7312_INTR1_WEINT   0x00000004
129#define EP7312_INTR1_MCINT   0x00000008
130#define EP7312_INTR1_CSINT   0x00000010
131#define EP7312_INTR1_EINT1   0x00000020
132#define EP7312_INTR1_EINT2   0x00000040
133#define EP7312_INTR1_EINT3   0x00000080
134#define EP7312_INTR1_TC1OI   0x00000100
135#define EP7312_INTR1_TC2OI   0x00000200
136#define EP7312_INTR1_RTCMI   0x00000400
137#define EP7312_INTR1_TINT    0x00000800
138#define EP7312_INTR1_URXINT1 0x00001000
139#define EP7312_INTR1_UTXINT1 0x00002000
140#define EP7312_INTR1_UMSINT  0x00004000
141#define EP7312_INTR1_SSEOTI  0x00008000
142
143/* INTR2 (Interrupt 2) mask/status register bits */
144#define EP7312_INTR2_KBDINT  0x00000001
145#define EP7312_INTR2_SS2RX   0x00000002
146#define EP7312_INTR2_SS2TX   0x00000004
147#define EP7312_INTR2_URXINT2 0x00001000
148#define EP7312_INTR2_UTXINT2 0x00002000
149
150/* INTR3 (Interrupt 3) mask/status register bits */
151#define EP7312_INTR2_DAIINT  0x00000001
152
153#endif /* __EP7312_H__ */
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