1 | /** |
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2 | * @file |
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3 | * @ingroup edb7312_registers |
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4 | * @brief Register declarations. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Cirrus EP7312 register declarations |
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9 | * |
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10 | * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com> |
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11 | * |
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12 | * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com> |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | * |
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18 | * |
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19 | * Notes: The PLL registers (pll_ro and pll_wo) are either read only |
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20 | * or write only. The data sheet says not to write the read |
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21 | * only one or read the write only one. I'm not sure what will |
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22 | * happen if you do. |
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23 | */ |
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24 | #ifndef __EP7312_H__ |
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25 | #define __EP7312_H__ |
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26 | |
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27 | #define EP7312_REG_BASE 0x80000000 |
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28 | |
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29 | /** |
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30 | * @defgroup edb7312_registers Register Definitions |
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31 | * @ingroup arm_edb7312 |
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32 | * @brief Cirrus EP7312 Register Definitions |
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33 | * @{ |
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34 | */ |
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35 | |
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36 | #define EP7312_PADR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000)) |
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37 | #define EP7312_PBDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001)) |
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38 | #define EP7312_PDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003)) |
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39 | #define EP7312_PADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040)) |
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40 | #define EP7312_PBDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041)) |
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41 | #define EP7312_PDDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043)) |
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42 | #define EP7312_PEDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080)) |
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43 | #define EP7312_PEDDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0)) |
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44 | #define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100)) |
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45 | #define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140)) |
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46 | #define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180)) |
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47 | #define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0)) |
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48 | #define EP7312_INTSR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240)) |
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49 | #define EP7312_INTMR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280)) |
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50 | #define EP7312_LCDCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0)) |
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51 | #define EP7312_TC1D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300)) |
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52 | #define EP7312_TC2D ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340)) |
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53 | #define EP7312_RTCDR ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380)) |
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54 | #define EP7312_RTCMR ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0)) |
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55 | #define EP7312_PMPCON ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400)) |
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56 | #define EP7312_CODR ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440)) |
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57 | #define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480)) |
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58 | #define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0)) |
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59 | #define EP7312_SYNCIO ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500)) |
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60 | #define EP7312_PALLSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540)) |
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61 | #define EP7312_PALMSW ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580)) |
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62 | #define EP7312_STFCLR ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0)) |
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63 | #define EP7312_BLEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600)) |
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64 | #define EP7312_MCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640)) |
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65 | #define EP7312_TEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680)) |
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66 | #define EP7312_TC1EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0)) |
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67 | #define EP7312_TC2EOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700)) |
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68 | #define EP7312_RTCEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740)) |
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69 | #define EP7312_UMSEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780)) |
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70 | #define EP7312_COEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0)) |
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71 | #define EP7312_HALT ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800)) |
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72 | #define EP7312_STDBY ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840)) |
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73 | #define EP7312_FBADDR ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000)) |
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74 | #define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100)) |
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75 | #define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140)) |
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76 | #define EP7312_INTSR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240)) |
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77 | #define EP7312_INTMR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280)) |
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78 | #define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480)) |
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79 | #define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0)) |
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80 | #define EP7312_SS2DR ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500)) |
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81 | #define EP7312_SRXEOF ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600)) |
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82 | #define EP7312_SS2POP ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0)) |
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83 | #define EP7312_KBDEOI ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700)) |
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84 | #define EP7312_DAIR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000)) |
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85 | #define EP7312_DAIDR0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040)) |
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86 | #define EP7312_DAIDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080)) |
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87 | #define EP7312_DAIDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0)) |
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88 | #define EP7312_DAISR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100)) |
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89 | #define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200)) |
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90 | #define EP7312_INTSR3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240)) |
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91 | #define EP7312_INTMR3 ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280)) |
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92 | #define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0)) |
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93 | #define EP7312_SDCONF ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300)) |
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94 | #define EP7312_SDRFPR ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340)) |
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95 | #define EP7312_UNIQID ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440)) |
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96 | #define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600)) |
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97 | #define EP7312_PLLW ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610)) |
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98 | #define EP7312_PLLR ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8)) |
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99 | #define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700)) |
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100 | #define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704)) |
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101 | #define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708)) |
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102 | #define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C)) |
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103 | |
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104 | /* serial port bits */ |
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105 | |
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106 | /** |
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107 | * @name BITS in UBRLCR1 |
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108 | * @{ |
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109 | */ |
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110 | |
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111 | #define EP7312_UART_WRDLEN5 0x00000000 |
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112 | #define EP7312_UART_WRDLEN6 0x00020000 |
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113 | #define EP7312_UART_WRDLEN7 0x00040000 |
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114 | #define EP7312_UART_WRDLEN8 0x00060000 |
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115 | #define EP7312_UART_FIFOEN 0x00010000 |
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116 | #define EP7312_UART_XSTOP 0x00008000 |
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117 | #define EP7312_UART_EVENPRT 0x00004000 |
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118 | #define EP7312_UART_PRTEN 0x00002000 |
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119 | #define EP7312_UART_BREAK 0x00001000 |
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120 | |
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121 | /** @} */ |
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122 | |
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123 | /** |
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124 | * @name BITS in INTSR1 |
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125 | * @{ |
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126 | */ |
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127 | |
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128 | #define EP7312_UART_UTXINT1 0x00002000 |
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129 | #define EP7312_UART_URXINT1 0x00001000 |
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130 | |
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131 | /** @} */ |
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132 | |
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133 | /** |
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134 | * @name BITS in UARTTDR1 |
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135 | * @{ |
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136 | */ |
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137 | |
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138 | #define EP7312_UART_FRMERR 0x00000100 |
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139 | #define EP7312_UART_PARERR 0x00000200 |
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140 | #define EP7312_UART_OVERR 0x00000400 |
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141 | |
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142 | /** @} */ |
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143 | |
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144 | /** |
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145 | * @name BITS in system status flag register 1 |
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146 | * @{ |
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147 | */ |
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148 | |
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149 | #define EP7312_UART_UBUSY1 0x00000800 |
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150 | #define EP7312_UART_URXFE1 0x00400000 |
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151 | #define EP7312_UART_UTXFF1 0x00800000 |
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152 | |
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153 | /** @} */ |
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154 | |
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155 | /* system configuration bits */ |
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156 | |
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157 | /** |
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158 | * @name BITS in SYSCON1 |
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159 | * @{ |
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160 | */ |
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161 | |
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162 | #define EP7312_SYSCON1_UART1EN 0x00000100 |
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163 | #define EP7312_SYSCON1_TC1_PRESCALE 0x00000010 |
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164 | #define EP7312_SYSCON1_TC1_512KHZ 0x00000020 |
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165 | #define EP7312_SYSCON1_TC2_PRESCALE 0x00000040 |
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166 | #define EP7312_SYSCON1_TC2_512KHZ 0x00000080 |
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167 | |
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168 | /** @} */ |
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169 | |
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170 | /** |
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171 | * @name INTR1 (Interrupt 1) mask/status register bits |
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172 | * @{ |
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173 | */ |
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174 | |
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175 | #define EP7312_INTR1_EXTFIQ 0x00000001 |
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176 | #define EP7312_INTR1_BLINT 0x00000002 |
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177 | #define EP7312_INTR1_WEINT 0x00000004 |
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178 | #define EP7312_INTR1_MCINT 0x00000008 |
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179 | #define EP7312_INTR1_CSINT 0x00000010 |
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180 | #define EP7312_INTR1_EINT1 0x00000020 |
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181 | #define EP7312_INTR1_EINT2 0x00000040 |
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182 | #define EP7312_INTR1_EINT3 0x00000080 |
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183 | #define EP7312_INTR1_TC1OI 0x00000100 |
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184 | #define EP7312_INTR1_TC2OI 0x00000200 |
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185 | #define EP7312_INTR1_RTCMI 0x00000400 |
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186 | #define EP7312_INTR1_TINT 0x00000800 |
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187 | #define EP7312_INTR1_URXINT1 0x00001000 |
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188 | #define EP7312_INTR1_UTXINT1 0x00002000 |
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189 | #define EP7312_INTR1_UMSINT 0x00004000 |
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190 | #define EP7312_INTR1_SSEOTI 0x00008000 |
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191 | |
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192 | /** @} */ |
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193 | |
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194 | /** |
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195 | * @name INTR2 (Interrupt 2) mask/status register bits |
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196 | * @{ |
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197 | */ |
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198 | |
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199 | #define EP7312_INTR2_KBDINT 0x00000001 |
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200 | #define EP7312_INTR2_SS2RX 0x00000002 |
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201 | #define EP7312_INTR2_SS2TX 0x00000004 |
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202 | #define EP7312_INTR2_URXINT2 0x00001000 |
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203 | #define EP7312_INTR2_UTXINT2 0x00002000 |
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204 | |
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205 | /** @} */ |
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206 | |
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207 | /** |
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208 | * @name INTR3 (Interrupt 3) mask/status register bits |
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209 | * @{ |
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210 | */ |
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211 | |
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212 | #define EP7312_INTR2_DAIINT 0x00000001 |
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213 | |
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214 | /** @} */ |
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215 | |
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216 | /** @} */ |
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217 | |
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218 | #endif /* __EP7312_H__ */ |
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