source: rtems/c/src/lib/libbsp/arm/edb7312/include/ep7312.h @ 49232d0

4.11
Last change on this file since 49232d0 was 49232d0, checked in by Daniel Ramirez <javamonn@…>, on Dec 21, 2013 at 9:50:55 PM

arm_edb7312: added new doxygen

  • Property mode set to 100644
File size: 8.0 KB
Line 
1/**
2 * @file
3 * @ingroup edb7312_registers
4 * @brief Register declarations.
5 */
6
7/*
8 * Cirrus EP7312 register declarations
9 *
10 * Copyright (c) 2002 by Charlie Steader <charlies@poliac.com>
11 *
12 * Copyright (c) 2002 by Jay Monkman <jtm@smoothsmoothie.com>
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *
19 * Notes: The PLL registers (pll_ro and pll_wo) are either read only
20 *        or write only. The data sheet says not to write the read
21 *        only one or read the write only one. I'm not sure what will
22 *        happen if you do.
23*/
24#ifndef __EP7312_H__
25#define __EP7312_H__
26
27#define EP7312_REG_BASE 0x80000000
28
29/**
30 * @defgroup edb7312_registers Register Definitions
31 * @ingroup arm_edb7312
32 * @brief Cirrus EP7312 Register Definitions
33 * @{
34 */
35
36#define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
37#define EP7312_PBDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0001))
38#define EP7312_PDDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0003))
39#define EP7312_PADDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0040))
40#define EP7312_PBDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0041))
41#define EP7312_PDDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x0043))
42#define EP7312_PEDR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0080))
43#define EP7312_PEDDR   ((volatile uint8_t*)(EP7312_REG_BASE + 0x00C0))
44#define EP7312_SYSCON1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0100))
45#define EP7312_SYSFLG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0140))
46#define EP7312_MEMCFG1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0180))
47#define EP7312_MEMCFG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x01C0))
48#define EP7312_INTSR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0240))
49#define EP7312_INTMR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0280))
50#define EP7312_LCDCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x02C0))
51#define EP7312_TC1D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0300))
52#define EP7312_TC2D    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0340))
53#define EP7312_RTCDR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0380))
54#define EP7312_RTCMR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x03C0))
55#define EP7312_PMPCON  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0400))
56#define EP7312_CODR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0440))
57#define EP7312_UARTDR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x0480))
58#define EP7312_UARTCR1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x04C0))
59#define EP7312_SYNCIO  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0500))
60#define EP7312_PALLSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0540))
61#define EP7312_PALMSW  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0580))
62#define EP7312_STFCLR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x05C0))
63#define EP7312_BLEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0600))
64#define EP7312_MCEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0640))
65#define EP7312_TEOI    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0680))
66#define EP7312_TC1EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x06C0))
67#define EP7312_TC2EOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0700))
68#define EP7312_RTCEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0740))
69#define EP7312_UMSEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x0780))
70#define EP7312_COEOI   ((volatile uint32_t*)(EP7312_REG_BASE + 0x07C0))
71#define EP7312_HALT    ((volatile uint32_t*)(EP7312_REG_BASE + 0x0800))
72#define EP7312_STDBY   ((volatile uint32_t*)(EP7312_REG_BASE + 0x0840))
73#define EP7312_FBADDR  ((volatile uint8_t*)(EP7312_REG_BASE + 0x1000))
74#define EP7312_SYSCON2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1100))
75#define EP7312_SYSFLG2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1140))
76#define EP7312_INTSR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1240))
77#define EP7312_INTMR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1280))
78#define EP7312_UARTDR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x1480))
79#define EP7312_UARTCR2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x14C0))
80#define EP7312_SS2DR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x1500))
81#define EP7312_SRXEOF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1600))
82#define EP7312_SS2POP  ((volatile uint32_t*)(EP7312_REG_BASE + 0x16C0))
83#define EP7312_KBDEOI  ((volatile uint32_t*)(EP7312_REG_BASE + 0x1700))
84#define EP7312_DAIR    ((volatile uint32_t*)(EP7312_REG_BASE + 0x2000))
85#define EP7312_DAIDR0  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2040))
86#define EP7312_DAIDR1  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2080))
87#define EP7312_DAIDR2  ((volatile uint32_t*)(EP7312_REG_BASE + 0x20C0))
88#define EP7312_DAISR   ((volatile uint32_t*)(EP7312_REG_BASE + 0x2100))
89#define EP7312_SYSCON3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2200))
90#define EP7312_INTSR3  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2240))
91#define EP7312_INTMR3  ((volatile uint8_t*)(EP7312_REG_BASE + 0x2280))
92#define EP7312_LEDFLSH ((volatile uint8_t*)(EP7312_REG_BASE + 0x22C0))
93#define EP7312_SDCONF  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2300))
94#define EP7312_SDRFPR  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2340))
95#define EP7312_UNIQID  ((volatile uint32_t*)(EP7312_REG_BASE + 0x2440))
96#define EP7312_DAI64Fs ((volatile uint32_t*)(EP7312_REG_BASE + 0x2600))
97#define EP7312_PLLW    ((volatile uint8_t*)(EP7312_REG_BASE + 0x2610))
98#define EP7312_PLLR    ((volatile uint8_t*)(EP7312_REG_BASE + 0xA5A8))
99#define EP7312_RANDID0 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2700))
100#define EP7312_RANDID1 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2704))
101#define EP7312_RANDID2 ((volatile uint32_t*)(EP7312_REG_BASE + 0x2708))
102#define EP7312_RANDID3 ((volatile uint32_t*)(EP7312_REG_BASE + 0x270C))
103
104/* serial port bits */
105
106/**
107 * @name BITS in UBRLCR1
108 * @{
109 */
110
111#define EP7312_UART_WRDLEN5    0x00000000
112#define EP7312_UART_WRDLEN6    0x00020000
113#define EP7312_UART_WRDLEN7    0x00040000
114#define EP7312_UART_WRDLEN8    0x00060000
115#define EP7312_UART_FIFOEN     0x00010000
116#define EP7312_UART_XSTOP      0x00008000
117#define EP7312_UART_EVENPRT    0x00004000
118#define EP7312_UART_PRTEN      0x00002000
119#define EP7312_UART_BREAK      0x00001000
120
121/** @} */
122
123/**
124 * @name BITS in INTSR1
125 * @{
126 */
127
128#define EP7312_UART_UTXINT1    0x00002000
129#define EP7312_UART_URXINT1    0x00001000
130
131/** @} */
132
133/**
134 * @name BITS in UARTTDR1
135 * @{
136 */
137
138#define EP7312_UART_FRMERR     0x00000100
139#define EP7312_UART_PARERR     0x00000200
140#define EP7312_UART_OVERR      0x00000400
141
142/** @} */
143
144/**
145 * @name BITS in system status flag register 1
146 * @{
147 */
148
149#define EP7312_UART_UBUSY1     0x00000800
150#define EP7312_UART_URXFE1     0x00400000
151#define EP7312_UART_UTXFF1     0x00800000
152
153/** @} */
154
155/* system configuration bits */
156
157/**
158 * @name  BITS in SYSCON1
159 * @{
160 */
161
162#define EP7312_SYSCON1_UART1EN       0x00000100
163#define EP7312_SYSCON1_TC1_PRESCALE  0x00000010
164#define EP7312_SYSCON1_TC1_512KHZ    0x00000020
165#define EP7312_SYSCON1_TC2_PRESCALE  0x00000040
166#define EP7312_SYSCON1_TC2_512KHZ    0x00000080
167
168/** @} */
169
170/**
171 * @name INTR1 (Interrupt 1) mask/status register bits
172 * @{
173 */
174
175#define EP7312_INTR1_EXTFIQ  0x00000001
176#define EP7312_INTR1_BLINT   0x00000002
177#define EP7312_INTR1_WEINT   0x00000004
178#define EP7312_INTR1_MCINT   0x00000008
179#define EP7312_INTR1_CSINT   0x00000010
180#define EP7312_INTR1_EINT1   0x00000020
181#define EP7312_INTR1_EINT2   0x00000040
182#define EP7312_INTR1_EINT3   0x00000080
183#define EP7312_INTR1_TC1OI   0x00000100
184#define EP7312_INTR1_TC2OI   0x00000200
185#define EP7312_INTR1_RTCMI   0x00000400
186#define EP7312_INTR1_TINT    0x00000800
187#define EP7312_INTR1_URXINT1 0x00001000
188#define EP7312_INTR1_UTXINT1 0x00002000
189#define EP7312_INTR1_UMSINT  0x00004000
190#define EP7312_INTR1_SSEOTI  0x00008000
191
192/** @} */
193
194/**
195 * @name INTR2 (Interrupt 2) mask/status register bits
196 * @{
197 */
198
199#define EP7312_INTR2_KBDINT  0x00000001
200#define EP7312_INTR2_SS2RX   0x00000002
201#define EP7312_INTR2_SS2TX   0x00000004
202#define EP7312_INTR2_URXINT2 0x00001000
203#define EP7312_INTR2_UTXINT2 0x00002000
204
205/** @} */
206
207/**
208 * @name INTR3 (Interrupt 3) mask/status register bits
209 * @{
210 */
211
212#define EP7312_INTR2_DAIINT  0x00000001
213
214/** @} */
215
216/** @} */
217
218#endif /* __EP7312_H__ */
Note: See TracBrowser for help on using the repository browser.