source: rtems/c/src/lib/libbsp/arm/csb337/start/start.S @ 2433a8ab

5
Last change on this file since 2433a8ab was 2433a8ab, checked in by Sebastian Huber <sebastian.huber@…>, on Mar 7, 2017 at 1:32:42 PM

arm: Remove legacy execption support

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 * Cogent CSB337 startup code
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9*/
10
11#include <bsp/linker-symbols.h>
12
13/* Some standard definitions...*/
14.equ PSR_MODE_USR,       0x10
15.equ PSR_MODE_FIQ,       0x11
16.equ PSR_MODE_IRQ,       0x12
17.equ PSR_MODE_SVC,       0x13
18.equ PSR_MODE_ABT,       0x17
19.equ PSR_MODE_UNDEF,     0x1B
20.equ PSR_MODE_SYS,       0x1F
21
22.equ PSR_I,              0x80
23.equ PSR_F,              0x40
24.equ PSR_T,              0x20
25
26.text
27.globl  _start
28_start:
29        /*
30         * Since I don't plan to return to the bootloader,
31         * I don't have to save the registers.
32         *
33         * I'll just set the CPSR for SVC mode, interrupts
34         * off, and ARM instructions.
35         */
36        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
37        msr     cpsr, r0
38
39        /* zero the bss */
40        ldr     r1, =bsp_section_bss_end
41        ldr     r0, =bsp_section_bss_begin
42
43_bss_init:
44        mov     r2, #0
45        cmp     r0, r1
46        strlot  r2, [r0], #4
47        blo     _bss_init        /* loop while r0 < r1 */
48
49
50        /* --- Initialize stack pointer registers */
51        /* Enter IRQ mode and set up the IRQ stack pointer */
52        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
53        msr     cpsr, r0
54        ldr     r1, =bsp_stack_irq_size
55        ldr     sp, =bsp_stack_irq_begin
56        add     sp, sp, r1
57
58        /* Enter FIQ mode and set up the FIQ stack pointer */
59        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
60        msr     cpsr, r0
61        ldr     r1, =bsp_stack_fiq_size
62        ldr     sp, =bsp_stack_fiq_begin
63        add     sp, sp, r1
64
65        /* Enter ABT mode and set up the ABT stack pointer */
66        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
67        msr     cpsr, r0
68        ldr     r1, =bsp_stack_abt_size
69        ldr     sp, =bsp_stack_abt_begin
70        add     sp, sp, r1
71
72        /* Set up the SVC stack pointer last and stay in SVC mode */
73        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
74        msr     cpsr, r0
75        ldr     r1, =bsp_stack_svc_size
76        ldr     sp, =bsp_stack_svc_begin
77        add     sp, sp, r1
78        sub     sp, sp, #0x64
79
80        /*
81         * Initialize the MMU. After we return, the MMU is enabled,
82         * and memory may be remapped. I hope we don't remap this
83         * memory away.
84         */
85        ldr     r0, =mem_map
86        bl      mmu_init
87
88        /*
89         * Initialize the exception vectors. This includes the
90         * exceptions vectors (0x00000000-0x0000001c), and the
91         * pointers to the exception handlers (0x00000020-0x0000003c).
92         */
93        mov     r0, #0
94        adr     r1, vector_block
95        ldmia   r1!, {r2-r9}
96        stmia   r0!, {r2-r9}
97        ldmia   r1!, {r2-r9}
98        stmia   r0!, {r2-r9}
99
100        /* Now we are prepared to start the BSP's C code */
101        mov     r0, #0
102        bl      boot_card
103
104        /*
105         * Theoretically, we could return to what started us up,
106         * but we'd have to have saved the registers and stacks.
107         * Instead, we'll just reset.
108         */
109        bl      bsp_reset
110
111        /* We shouldn't get here. If we do, hang */
112_hang:  b       _hang
113
114
115/*
116 * This is the exception vector table and the pointers to
117 * the functions that handle the exceptions. It's a total
118 * of 16 words (64 bytes)
119 */
120vector_block:
121        ldr    pc, handler_addr_reset
122        ldr    pc, handler_addr_undef
123        ldr    pc, handler_addr_swi
124        ldr    pc, handler_addr_prefetch
125        ldr    pc, handler_addr_abort
126        nop
127        ldr    pc, handler_addr_irq
128        ldr    pc, handler_addr_fiq
129
130handler_addr_reset:
131        .word  bsp_reset
132
133handler_addr_undef:
134        .word  _ARMV4_Exception_undef_default
135
136handler_addr_swi:
137        .word  _ARMV4_Exception_swi_default
138
139handler_addr_prefetch:
140        .word  _ARMV4_Exception_pref_abort_default
141
142handler_addr_abort:
143        .word  _ARMV4_Exception_data_abort_default
144
145handler_addr_reserved:
146        .word  _ARMV4_Exception_reserved_default
147
148handler_addr_irq:
149        .word  _ARMV4_Exception_interrupt
150
151handler_addr_fiq:
152        .word  _ARMV4_Exception_fiq_default
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