1 | /* |
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2 | * AT91RM9200 ethernet driver |
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3 | * |
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4 | * Copyright (c) 2003 by Cogent Computer Systems |
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5 | * Written by Mike Kelly <mike@cogcomp.com> |
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6 | * and Jay Monkman <jtm@lopingdog.com> |
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7 | * |
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8 | * |
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9 | * July 2009: Joel Sherrill merged csb637 PHY differences from |
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10 | * MicroMonitor 1.17. |
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11 | */ |
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12 | |
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13 | #include <rtems.h> |
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14 | #include <rtems/rtems_bsdnet.h> |
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15 | #include <at91rm9200.h> |
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16 | #include <at91rm9200_emac.h> |
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17 | #include <at91rm9200_gpio.h> |
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18 | #include <at91rm9200_pmc.h> |
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19 | |
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20 | #include <stdio.h> |
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21 | #include <string.h> |
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22 | |
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23 | #include <errno.h> |
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24 | #include <rtems/error.h> |
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25 | #include <assert.h> |
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26 | |
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27 | #include <sys/param.h> |
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28 | #include <sys/mbuf.h> |
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29 | #include <sys/socket.h> |
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30 | #include <sys/sockio.h> |
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31 | |
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32 | #include <net/if.h> |
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33 | |
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34 | #include <netinet/in.h> |
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35 | #include <netinet/if_ether.h> |
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36 | |
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37 | #include <bsp/irq.h> |
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38 | #include <bspopts.h> |
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39 | |
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40 | /* enable debugging of the PHY code */ |
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41 | #define PHY_DBG |
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42 | |
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43 | /* enable debugging of the EMAC code */ |
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44 | /* #define EMAC_DBG */ |
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45 | |
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46 | #if csb637 |
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47 | /* Bit defines for the PHY Status Register #1 (phy address 0x01) */ |
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48 | /* 1 = PHY able to perform 100BASE-T4 */ |
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49 | #define PHY_STAT_100BASE_T4 BIT15 |
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50 | /* 1 = PHY able to perform full-duplex 100BASE-X */ |
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51 | #define PHY_STAT_100BASE_X_FDX BIT14 |
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52 | /* 1 = PHY able to perform half-duplex 100BASE-X */ |
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53 | #define PHY_STAT_100BASE_X_HDX BIT13 |
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54 | /* 1 = PHY able to operate at 10 Mbps in full-duplex mode */ |
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55 | #define PHY_STAT_10BASE_FDX BIT12 |
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56 | /* 1 = PHY able to operate at 10 Mbps in half-duplex mode */ |
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57 | #define PHY_STAT_10BASE_HDX BIT11 |
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58 | /* 1 = PHY will accept management frames with preamble suppressed */ |
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59 | #define PHY_STAT_MF_PREAMBLE BIT6 |
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60 | /* 1 = Auto-negotiation complete */ |
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61 | #define PHY_STAT_AUTO_NEG_DONE BIT5 |
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62 | /* 1 = Remote fault condition detected */ |
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63 | #define PHY_STAT_REM_FLT BIT4 |
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64 | /* 1 = PHY is able to perform Auto-Negotiation */ |
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65 | #define PHY_STAT_AUTO_NEG_ABLE BIT3 |
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66 | /* 1 = Link is up */ |
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67 | #define PHY_STAT_LINK_UP BIT2 |
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68 | /* 1 = Jabber condition detected */ |
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69 | #define PHY_STAT_JABBER BIT1 |
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70 | /* 1 = Extended register capabilities */ |
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71 | #define PHY_STAT_EXT_REG BIT0 |
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72 | |
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73 | /* Bit defines for the Auxillary Mode 3 register */ |
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74 | #define PHY_AUX_MODE2_TRAFFIC_LED BIT6 |
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75 | #endif |
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76 | |
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77 | /* interrupt stuff */ |
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78 | #define EMAC_INT_PRIORITY 0 /* lowest priority */ |
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79 | |
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80 | /* RTEMS event used by interrupt handler to start receive daemon. */ |
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81 | #define START_RECEIVE_EVENT RTEMS_EVENT_1 |
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82 | |
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83 | /* RTEMS event used to start transmit daemon. */ |
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84 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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85 | |
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86 | static void at91rm9200_emac_isr (void *); |
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87 | static void at91rm9200_emac_isr_on(void); |
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88 | |
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89 | /* use the values defined in linkcmds for our use of SRAM */ |
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90 | extern void * at91rm9200_emac_rxbuf_hdrs; |
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91 | extern void * at91rm9200_emac_txbuf; |
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92 | extern void * at91rm9200_emac_rxbufs; |
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93 | |
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94 | /* Set up EMAC hardware */ |
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95 | /* Number of Receive and Transmit Buffers and Buffer Descriptors */ |
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96 | #define NUM_RXBDS 8 |
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97 | #define NUM_TXBDS 1 |
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98 | #define RX_BUFFER_SIZE 0x600 |
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99 | |
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100 | /* use internal SRAM for buffers and descriptors |
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101 | * also insure that the receive descriptors |
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102 | * start on a 64byte boundary |
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103 | * Receive Buffer Descriptor Header |
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104 | */ |
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105 | |
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106 | typedef struct |
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107 | { |
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108 | unsigned long address; |
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109 | unsigned long status; |
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110 | } RXBUF_HDR; |
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111 | |
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112 | RXBUF_HDR *rxbuf_hdrs; |
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113 | unsigned char *txbuf; |
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114 | unsigned char *rxbuf; |
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115 | |
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116 | int delay_cnt; |
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117 | |
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118 | /* |
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119 | * Hardware-specific storage |
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120 | */ |
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121 | typedef struct |
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122 | { |
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123 | /* |
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124 | * Connection to networking code |
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125 | * This entry *must* be the first in the sonic_softc structure. |
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126 | */ |
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127 | struct arpcom arpcom; |
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128 | |
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129 | /* |
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130 | * Interrupt vector |
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131 | */ |
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132 | rtems_vector_number vector; |
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133 | |
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134 | /* |
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135 | * Indicates configuration |
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136 | */ |
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137 | int acceptBroadcast; |
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138 | |
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139 | /* |
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140 | * Task waiting for interrupts |
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141 | */ |
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142 | rtems_id rxDaemonTid; |
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143 | rtems_id txDaemonTid; |
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144 | |
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145 | /* |
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146 | * current receive header |
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147 | */ |
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148 | int rx_buf_idx; |
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149 | |
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150 | |
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151 | |
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152 | /* |
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153 | * Statistics |
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154 | */ |
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155 | unsigned long Interrupts; |
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156 | unsigned long rxInterrupts; |
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157 | unsigned long rxMissed; |
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158 | unsigned long rxGiant; |
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159 | unsigned long rxNonOctet; |
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160 | unsigned long rxBadCRC; |
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161 | unsigned long rxCollision; |
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162 | |
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163 | unsigned long txInterrupts; |
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164 | unsigned long txSingleCollision; |
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165 | unsigned long txMultipleCollision; |
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166 | unsigned long txCollision; |
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167 | unsigned long txDeferred; |
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168 | unsigned long txUnderrun; |
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169 | unsigned long txLateCollision; |
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170 | unsigned long txExcessiveCollision; |
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171 | unsigned long txExcessiveDeferral; |
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172 | unsigned long txLostCarrier; |
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173 | unsigned long txRawWait; |
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174 | } at91rm9200_emac_softc_t; |
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175 | |
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176 | static at91rm9200_emac_softc_t softc; |
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177 | |
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178 | |
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179 | /* The AT91RM9200 ethernet fifos are very undersized. Therefore |
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180 | * we use the internal SRAM to hold 4 receive packets and one |
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181 | * transmit packet. Note that the AT91RM9200 can only queue |
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182 | * one transmit packet at a time. |
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183 | */ |
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184 | |
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185 | /* function prototypes */ |
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186 | int rtems_at91rm9200_emac_attach (struct rtems_bsdnet_ifconfig *config, |
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187 | void *chip); |
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188 | void at91rm9200_emac_init(void *arg); |
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189 | void at91rm9200_emac_init_hw(at91rm9200_emac_softc_t *sc); |
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190 | void at91rm9200_emac_start(struct ifnet *ifp); |
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191 | void at91rm9200_emac_stop (at91rm9200_emac_softc_t *sc); |
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192 | void at91rm9200_emac_txDaemon (void *arg); |
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193 | void at91rm9200_emac_sendpacket (struct ifnet *ifp, struct mbuf *m); |
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194 | void at91rm9200_emac_rxDaemon(void *arg); |
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195 | void at91rm9200_emac_stats (at91rm9200_emac_softc_t *sc); |
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196 | static int at91rm9200_emac_ioctl (struct ifnet *ifp, |
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197 | ioctl_command_t command, |
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198 | caddr_t data); |
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199 | |
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200 | #if csb637 |
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201 | /* |
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202 | * phyread(): Read the PHY |
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203 | */ |
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204 | static uint32_t phyread(uint8_t reg) |
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205 | { |
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206 | EMAC_REG(EMAC_MAN) = (0x01 << 30 /* Start of Frame Delimiter */ |
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207 | | 0x02 << 28 /* Operation, 0x01 = Write, 0x02 = Read */ |
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208 | | 0x00 << 23 /* Phy Number, 0 as we only have one */ |
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209 | | reg << 18 /* Phy Register */ |
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210 | | 0x02 << 16); /* must be 0x02 for turn around field */ |
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211 | |
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212 | /* wait for phy read to complete (was udelay(5000)) */ |
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213 | rtems_task_wake_after(1); |
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214 | |
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215 | #if defined(EMAC_DBG) |
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216 | printk( |
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217 | "EMAC: Phy 0, Reg %d, Read 0x%04lx.\n", |
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218 | reg, |
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219 | (EMAC_REG(EMAC_MAN) & 0xffff) |
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220 | ); |
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221 | #endif |
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222 | |
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223 | return EMAC_REG(EMAC_MAN) & 0xffff; |
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224 | } |
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225 | #endif |
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226 | |
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227 | /* |
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228 | * phywrite(): Write the PHY |
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229 | */ |
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230 | static void phywrite(uint8_t reg, uint16_t data) |
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231 | { |
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232 | EMAC_REG(EMAC_MAN) = (0x01 << 30 /* Start of Frame Delimiter */ |
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233 | | 0x01 << 28 /* Operation, 0x01 = Write, 0x02 = Read */ |
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234 | | 0x00 << 23 /* Phy Number, BCM5221 is address 0 */ |
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235 | | reg << 18 /* Phy Register */ |
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236 | | 0x02 << 16 /* must be 0x02 for turn around field */ |
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237 | | data); |
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238 | #if defined(EMAC_DBG) |
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239 | printk("EMAC: Phy 0, Reg %d, Write 0x%04x.\n", reg, data); |
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240 | #endif |
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241 | |
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242 | /* wait for phy write to complete (was udelay(5000)) */ |
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243 | rtems_task_wake_after(1); |
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244 | } |
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245 | |
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246 | |
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247 | int rtems_at91rm9200_emac_attach ( |
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248 | struct rtems_bsdnet_ifconfig *config, |
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249 | void *chip /* only one ethernet, so no chip number */ |
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250 | ) |
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251 | { |
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252 | struct ifnet *ifp; |
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253 | int mtu; |
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254 | int unitnumber; |
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255 | char *unitname; |
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256 | void *p; |
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257 | |
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258 | /* an array of receive buffer descriptors -- avoid type punned warning */ |
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259 | p = (void *)&at91rm9200_emac_rxbuf_hdrs; |
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260 | rxbuf_hdrs = (RXBUF_HDR *)p; |
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261 | |
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262 | /* one transmit buffer, 1536 bytes maximum */ |
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263 | txbuf = (unsigned char *)&at91rm9200_emac_txbuf; |
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264 | |
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265 | /* receive buffers starting address */ |
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266 | rxbuf = (unsigned char *)&at91rm9200_emac_rxbufs; |
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267 | /* |
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268 | * Parse driver name |
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269 | */ |
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270 | if ((unitnumber = rtems_bsdnet_parse_driver_name (config, &unitname)) < 0) |
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271 | return 0; |
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272 | |
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273 | /* |
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274 | * Is driver free? |
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275 | */ |
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276 | if (unitnumber != 0) { |
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277 | printk ("Bad AT91RM9200 EMAC unit number.\n"); |
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278 | return 0; |
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279 | } |
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280 | ifp = &softc.arpcom.ac_if; |
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281 | if (ifp->if_softc != NULL) { |
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282 | printk ("Driver already in use.\n"); |
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283 | return 0; |
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284 | } |
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285 | |
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286 | /* |
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287 | * zero out the control structure |
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288 | */ |
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289 | |
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290 | memset( &softc, 0, sizeof(softc) ); |
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291 | |
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292 | |
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293 | /* get the MAC address from the chip */ |
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294 | softc.arpcom.ac_enaddr[0] = (EMAC_REG(EMAC_SA1L) >> 0) & 0xff; |
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295 | softc.arpcom.ac_enaddr[1] = (EMAC_REG(EMAC_SA1L) >> 8) & 0xff; |
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296 | softc.arpcom.ac_enaddr[2] = (EMAC_REG(EMAC_SA1L) >> 16) & 0xff; |
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297 | softc.arpcom.ac_enaddr[3] = (EMAC_REG(EMAC_SA1L) >> 24) & 0xff; |
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298 | softc.arpcom.ac_enaddr[4] = (EMAC_REG(EMAC_SA1H) >> 0) & 0xff; |
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299 | softc.arpcom.ac_enaddr[5] = (EMAC_REG(EMAC_SA1H) >> 8) & 0xff; |
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300 | |
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301 | #if 0 |
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302 | printk( "MAC=%02x:%02x:%02x:%02x:%02x:%02x\n", |
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303 | softc.arpcom.ac_enaddr[0], |
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304 | softc.arpcom.ac_enaddr[1], |
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305 | softc.arpcom.ac_enaddr[2], |
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306 | softc.arpcom.ac_enaddr[3], |
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307 | softc.arpcom.ac_enaddr[4], |
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308 | softc.arpcom.ac_enaddr[5] |
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309 | ); |
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310 | #endif |
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311 | |
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312 | if (config->mtu) { |
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313 | mtu = config->mtu; |
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314 | } else { |
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315 | mtu = ETHERMTU; |
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316 | } |
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317 | |
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318 | softc.acceptBroadcast = !config->ignore_broadcast; |
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319 | |
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320 | /* |
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321 | * Set up network interface values |
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322 | */ |
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323 | ifp->if_softc = &softc; |
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324 | ifp->if_unit = unitnumber; |
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325 | ifp->if_name = unitname; |
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326 | ifp->if_mtu = mtu; |
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327 | ifp->if_init = at91rm9200_emac_init; |
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328 | ifp->if_ioctl = at91rm9200_emac_ioctl; |
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329 | ifp->if_start = at91rm9200_emac_start; |
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330 | ifp->if_output = ether_output; |
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331 | ifp->if_flags = IFF_BROADCAST; |
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332 | if (ifp->if_snd.ifq_maxlen == 0) { |
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333 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
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334 | } |
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335 | |
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336 | softc.rx_buf_idx = 0; |
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337 | |
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338 | /* |
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339 | * Attach the interface |
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340 | */ |
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341 | if_attach (ifp); |
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342 | ether_ifattach (ifp); |
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343 | return 1; |
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344 | } |
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345 | |
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346 | void at91rm9200_emac_init(void *arg) |
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347 | { |
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348 | at91rm9200_emac_softc_t *sc = arg; |
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349 | struct ifnet *ifp = &sc->arpcom.ac_if; |
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350 | rtems_status_code status = RTEMS_SUCCESSFUL; |
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351 | |
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352 | /* |
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353 | *This is for stuff that only gets done once (at91rm9200_emac_init() |
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354 | * gets called multiple times |
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355 | */ |
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356 | if (sc->txDaemonTid == 0) { |
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357 | /* Set up EMAC hardware */ |
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358 | at91rm9200_emac_init_hw(sc); |
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359 | |
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360 | /* Start driver tasks */ |
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361 | sc->rxDaemonTid = rtems_bsdnet_newproc("ENrx", |
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362 | 4096, |
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363 | at91rm9200_emac_rxDaemon, |
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364 | sc); |
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365 | sc->txDaemonTid = rtems_bsdnet_newproc("ENtx", |
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366 | 4096, |
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367 | at91rm9200_emac_txDaemon, |
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368 | sc); |
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369 | } /* if txDaemonTid */ |
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370 | |
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371 | /* set our priority in the AIC */ |
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372 | AIC_SMR_REG(AIC_SMR_EMAC) = AIC_SMR_PRIOR(EMAC_INT_PRIORITY); |
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373 | |
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374 | /* install the interrupt handler */ |
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375 | status = rtems_interrupt_handler_install( |
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376 | AT91RM9200_INT_EMAC, |
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377 | "Network", |
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378 | RTEMS_INTERRUPT_UNIQUE, |
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379 | at91rm9200_emac_isr, |
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380 | NULL |
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381 | ); |
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382 | assert(status == RTEMS_SUCCESSFUL); |
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383 | at91rm9200_emac_isr_on(); |
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384 | |
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385 | /* EMAC doesn't support promiscuous, so ignore requests */ |
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386 | if (ifp->if_flags & IFF_PROMISC) { |
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387 | printk ("Warning - AT91RM9200 Ethernet driver" |
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388 | " doesn't support Promiscuous Mode!\n"); |
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389 | } |
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390 | |
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391 | /* |
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392 | * Tell the world that we're running. |
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393 | */ |
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394 | ifp->if_flags |= IFF_RUNNING; |
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395 | |
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396 | /* Enable TX/RX and clear the statistics counters */ |
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397 | EMAC_REG(EMAC_CTL) = (EMAC_CTL_TE | EMAC_CTL_RE | EMAC_CTL_CSR); |
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398 | |
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399 | /* clear any pending interrupts */ |
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400 | EMAC_REG(EMAC_TSR) = 0xffffffff; |
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401 | EMAC_REG(EMAC_RSR) = 0xffffffff; |
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402 | |
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403 | } /* at91rm9200_emac_init() */ |
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404 | |
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405 | void at91rm9200_emac_init_hw(at91rm9200_emac_softc_t *sc) |
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406 | { |
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407 | int i; |
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408 | |
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409 | /* Configure shared pins for Ethernet, not GPIO */ |
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410 | PIOA_REG(PIO_PDR) = ( BIT7 | /* tx clock */ |
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411 | BIT8 | /* tx enable */ |
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412 | BIT9 | /* tx data 0 */ |
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413 | BIT10 | /* tx data 1 */ |
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414 | BIT11 | /* carrier sense */ |
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415 | BIT12 | /* rx data 0 */ |
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416 | BIT13 | /* rx data 1 */ |
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417 | BIT14 | /* rx error */ |
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418 | BIT15 | /* MII clock */ |
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419 | BIT16 ); /* MII data */ |
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420 | |
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421 | PIOB_REG(PIO_PDR) = ( BIT12 | /* tx data 2 */ |
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422 | BIT13 | /* tx data 3 */ |
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423 | BIT14 | /* tx error */ |
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424 | BIT15 | /* rx data 2 */ |
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425 | BIT16 | /* rx data 3 */ |
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426 | BIT17 | /* rx data valid */ |
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427 | BIT18 | /* rx collistion */ |
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428 | BIT19 ); /* rx clock */ |
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429 | |
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430 | PIOB_REG(PIO_BSR) = ( BIT12 | /* tx data 2 */ |
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431 | BIT13 | /* tx data 3 */ |
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432 | BIT14 | /* tx error */ |
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433 | BIT15 | /* rx data 2 */ |
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434 | BIT16 | /* rx data 3 */ |
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435 | BIT17 | /* rx data valid */ |
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436 | BIT18 | /* rx collistion */ |
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437 | BIT19 ); /* rx clock */ |
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438 | |
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439 | |
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440 | /* Enable the clock to the EMAC */ |
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441 | PMC_REG(PMC_PCER) |= PMC_PCR_PID_EMAC; |
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442 | |
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443 | /* initialize our receive buffer descriptors */ |
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444 | for (i = 0; i < NUM_RXBDS-1; i++) { |
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445 | rxbuf_hdrs[i].address = (unsigned long)(&rxbuf[i * RX_BUFFER_SIZE]); |
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446 | rxbuf_hdrs[i].status = 0x00000000; |
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447 | } |
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448 | |
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449 | /* last one needs the wrapbit set as well */ |
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450 | rxbuf_hdrs[i].address = ((unsigned long)(&rxbuf[i * RX_BUFFER_SIZE]) | |
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451 | RXBUF_ADD_WRAP); |
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452 | rxbuf_hdrs[i].status = 0x00000000; |
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453 | |
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454 | /* point to our receive buffer queue */ |
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455 | EMAC_REG(EMAC_RBQP) = (unsigned long)rxbuf_hdrs; |
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456 | |
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457 | /* clear any left over status bits */ |
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458 | EMAC_REG(EMAC_RSR) &= ~(EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA); |
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459 | |
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460 | /* set the MII clock divder to MCK/64 */ |
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461 | EMAC_REG(EMAC_CFG) &= EMAC_CFG_CLK_MASK; |
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462 | EMAC_REG(EMAC_CFG) = (EMAC_CFG_CLK_64 | EMAC_CFG_BIG | EMAC_CFG_FD); |
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463 | |
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464 | /* enable the MII interface */ |
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465 | EMAC_REG(EMAC_CTL) = EMAC_CTL_MPE; |
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466 | |
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467 | #if csb637 |
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468 | { |
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469 | int timeout; |
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470 | uint32_t emac_link_status; |
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471 | |
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472 | #if defined(PHY_DBG) |
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473 | printk("EMAC: Getting Link Status.\n"); |
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474 | #endif |
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475 | /* read the PHY ID registers */ |
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476 | emac_link_status = phyread(0x02); |
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477 | emac_link_status = phyread(0x03); |
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478 | |
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479 | /* Get the link status - wait for done with a timeout */ |
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480 | for (timeout = 10000 ; timeout ; ) { |
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481 | for (i = 0; i < 100; i++) |
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482 | ; |
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483 | emac_link_status = phyread(0x01); |
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484 | if (!(emac_link_status & PHY_STAT_AUTO_NEG_ABLE)) { |
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485 | #if defined(PHY_DBG) |
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486 | printk("EMAC: PHY is unable to Auto-Negotatiate!\n"); |
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487 | #endif |
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488 | timeout = 0; |
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489 | break; |
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490 | } |
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491 | if (emac_link_status & PHY_STAT_AUTO_NEG_DONE) { |
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492 | #if defined(PHY_DBG) |
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493 | printk("EMAC: Auto-Negotiate Complete, Link = "); |
---|
494 | #endif |
---|
495 | break; |
---|
496 | } |
---|
497 | timeout-- ; |
---|
498 | } |
---|
499 | if (!timeout) { |
---|
500 | #if defined(PHY_DBG) |
---|
501 | printk( |
---|
502 | "EMAC: Auto-Negotatiate Failed, Status = 0x%04lx!\n" |
---|
503 | "EMAC: Initialization Halted.\n", |
---|
504 | emac_link_status |
---|
505 | ); |
---|
506 | #endif |
---|
507 | /* if autonegotiation fails, just force to 10HD... */ |
---|
508 | emac_link_status = PHY_STAT_10BASE_HDX; |
---|
509 | } |
---|
510 | |
---|
511 | /* Set SPD and FD based on the return link status */ |
---|
512 | if (emac_link_status & (PHY_STAT_100BASE_X_FDX | PHY_STAT_100BASE_X_HDX)){ |
---|
513 | EMAC_REG(EMAC_CFG) |= EMAC_CFG_SPD; |
---|
514 | #if defined(PHY_DBG) |
---|
515 | printk("100MBIT, "); |
---|
516 | #endif |
---|
517 | } else { |
---|
518 | EMAC_REG(EMAC_CFG) &= ~EMAC_CFG_SPD; |
---|
519 | #if defined(PHY_DBG) |
---|
520 | printk("10MBIT, "); |
---|
521 | #endif |
---|
522 | } |
---|
523 | |
---|
524 | if (emac_link_status & (PHY_STAT_100BASE_X_FDX | PHY_STAT_10BASE_FDX)) { |
---|
525 | EMAC_REG(EMAC_CFG) |= EMAC_CFG_FD; |
---|
526 | #if defined(PHY_DBG) |
---|
527 | printk("Full Duplex.\n"); |
---|
528 | #endif |
---|
529 | } else { |
---|
530 | EMAC_REG(EMAC_CFG) &= ~EMAC_CFG_FD; |
---|
531 | #if defined(PHY_DBG) |
---|
532 | printk("Half Duplex.\n"); |
---|
533 | #endif |
---|
534 | } |
---|
535 | |
---|
536 | /* Set PHY LED modes. Traffic Meter Mode for ACTLED |
---|
537 | * Set Bit 6 - Traffic Mode on |
---|
538 | */ |
---|
539 | phywrite(0x1b, PHY_AUX_MODE2_TRAFFIC_LED); |
---|
540 | } |
---|
541 | #else |
---|
542 | /* must be csb337 */ |
---|
543 | /* Set PHY LED2 to combined Link/Activity and enable pulse stretching */ |
---|
544 | phywrite( 18, 0x0d0a ); |
---|
545 | #endif |
---|
546 | |
---|
547 | #if 0 |
---|
548 | EMAC_REG(EMAC_MAN) = (0x01 << 30 | /* Start of Frame Delimiter */ |
---|
549 | 0x01 << 28 | /* Operation, 0x01 = Write */ |
---|
550 | 0x00 << 23 | /* Phy Number */ |
---|
551 | 0x14 << 18 | /* Phy Register */ |
---|
552 | 0x02 << 16 | /* must be 0x02 */ |
---|
553 | 0x0D0A); /* Write data (0x0000 if read) */ |
---|
554 | #endif |
---|
555 | |
---|
556 | } /* at91rm9200_emac_init_hw() */ |
---|
557 | |
---|
558 | void at91rm9200_emac_start(struct ifnet *ifp) |
---|
559 | { |
---|
560 | at91rm9200_emac_softc_t *sc = ifp->if_softc; |
---|
561 | |
---|
562 | rtems_bsdnet_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT); |
---|
563 | ifp->if_flags |= IFF_OACTIVE; |
---|
564 | } |
---|
565 | |
---|
566 | void at91rm9200_emac_stop (at91rm9200_emac_softc_t *sc) |
---|
567 | { |
---|
568 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
569 | |
---|
570 | ifp->if_flags &= ~IFF_RUNNING; |
---|
571 | |
---|
572 | /* |
---|
573 | * Stop the transmitter and receiver. |
---|
574 | */ |
---|
575 | EMAC_REG(EMAC_CTL) &= ~(EMAC_CTL_TE | EMAC_CTL_RE); |
---|
576 | } |
---|
577 | |
---|
578 | /* |
---|
579 | * Driver transmit daemon |
---|
580 | */ |
---|
581 | void at91rm9200_emac_txDaemon (void *arg) |
---|
582 | { |
---|
583 | at91rm9200_emac_softc_t *sc = (at91rm9200_emac_softc_t *)arg; |
---|
584 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
585 | struct mbuf *m; |
---|
586 | rtems_event_set events; |
---|
587 | |
---|
588 | for (;;) |
---|
589 | { |
---|
590 | /* turn on TX interrupt, then wait for one */ |
---|
591 | EMAC_REG(EMAC_IER) = EMAC_INT_TCOM; /* Transmit complete */ |
---|
592 | |
---|
593 | rtems_bsdnet_event_receive( |
---|
594 | START_TRANSMIT_EVENT, |
---|
595 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
596 | RTEMS_NO_TIMEOUT, |
---|
597 | &events); |
---|
598 | |
---|
599 | /* Send packets till queue is empty */ |
---|
600 | for (;;) |
---|
601 | { |
---|
602 | /* Get the next mbuf chain to transmit. */ |
---|
603 | IF_DEQUEUE(&ifp->if_snd, m); |
---|
604 | if (!m) |
---|
605 | break; |
---|
606 | at91rm9200_emac_sendpacket (ifp, m); |
---|
607 | } |
---|
608 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
609 | } |
---|
610 | } |
---|
611 | |
---|
612 | /* Send packet */ |
---|
613 | void at91rm9200_emac_sendpacket (struct ifnet *ifp, struct mbuf *m) |
---|
614 | { |
---|
615 | struct mbuf *l = NULL; |
---|
616 | unsigned int pkt_offset = 0; |
---|
617 | delay_cnt = 0; |
---|
618 | /* printk("at91rm9200_emac_sendpacket %p\n", m); */ |
---|
619 | |
---|
620 | /* Wait for EMAC Transmit Queue to become available. */ |
---|
621 | while (((EMAC_REG(EMAC_TSR) & EMAC_TSR_COMP) == 0) && |
---|
622 | ((EMAC_REG(EMAC_TSR) & EMAC_TSR_TXIDLE) == 0)) |
---|
623 | |
---|
624 | { |
---|
625 | delay_cnt++; |
---|
626 | /* sleep(0); make sure we don't hog the cpu */ |
---|
627 | continue; |
---|
628 | } |
---|
629 | |
---|
630 | /* copy the mbuf chain into the transmit buffer */ |
---|
631 | l = m; |
---|
632 | while (l != NULL) { |
---|
633 | memcpy(((char *)txbuf + pkt_offset), /* offset into pkt for mbuf */ |
---|
634 | (char *)mtod(l, void *), /* cast to void */ |
---|
635 | l->m_len); /* length of this mbuf */ |
---|
636 | |
---|
637 | pkt_offset += l->m_len; /* update offset */ |
---|
638 | l = l->m_next; /* get next mbuf, if any */ |
---|
639 | } |
---|
640 | |
---|
641 | /* free the mbuf chain we just copied */ |
---|
642 | m_freem(m); |
---|
643 | |
---|
644 | /* clear any pending status */ |
---|
645 | EMAC_REG(EMAC_TSR) = (EMAC_TSR_OVR | EMAC_TSR_COL | EMAC_TSR_RLE |
---|
646 | | EMAC_TSR_COMP | EMAC_TSR_UND); |
---|
647 | |
---|
648 | /* tell the EMAC about our buffer */ |
---|
649 | EMAC_REG(EMAC_TAR) = (unsigned long)txbuf; |
---|
650 | EMAC_REG(EMAC_TCR) = (unsigned long)pkt_offset; |
---|
651 | } /* at91rm9200_emac_sendpacket () */ |
---|
652 | |
---|
653 | |
---|
654 | /* SONIC reader task */ |
---|
655 | void at91rm9200_emac_rxDaemon(void *arg) |
---|
656 | { |
---|
657 | at91rm9200_emac_softc_t *sc = (at91rm9200_emac_softc_t *)arg; |
---|
658 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
659 | struct mbuf *m; |
---|
660 | struct ether_header *eh; |
---|
661 | rtems_event_set events; |
---|
662 | int pktlen; |
---|
663 | |
---|
664 | /* Input packet handling loop */ |
---|
665 | for (;;) { |
---|
666 | /* turn on RX interrupts, then wait for one */ |
---|
667 | EMAC_REG(EMAC_IER) = (EMAC_INT_RCOM | /* Receive complete */ |
---|
668 | EMAC_INT_RBNA | /* Receive buf not available */ |
---|
669 | EMAC_INT_ROVR); /* Receive overrun */ |
---|
670 | |
---|
671 | rtems_bsdnet_event_receive( |
---|
672 | START_RECEIVE_EVENT, |
---|
673 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
674 | RTEMS_NO_TIMEOUT, |
---|
675 | &events); |
---|
676 | |
---|
677 | if (EMAC_REG(EMAC_RSR) & EMAC_RSR_BNA) { |
---|
678 | printk("1: EMAC_BNA\n"); |
---|
679 | } |
---|
680 | |
---|
681 | if (EMAC_REG(EMAC_RSR) & EMAC_RSR_OVR) { |
---|
682 | printk("1: EMAC_OVR\n"); |
---|
683 | } |
---|
684 | |
---|
685 | /* clear the receive status as we do not use it anyway */ |
---|
686 | EMAC_REG(EMAC_RSR) = (EMAC_RSR_REC | EMAC_RSR_OVR | EMAC_RSR_BNA); |
---|
687 | |
---|
688 | /* scan the buffer descriptors looking for any with data in them */ |
---|
689 | while (rxbuf_hdrs[sc->rx_buf_idx].address & RXBUF_ADD_OWNED) { |
---|
690 | pktlen = rxbuf_hdrs[sc->rx_buf_idx].status & RXBUF_STAT_LEN_MASK; |
---|
691 | |
---|
692 | /* get an mbuf this packet */ |
---|
693 | MGETHDR(m, M_WAIT, MT_DATA); |
---|
694 | |
---|
695 | /* now get a cluster pointed to by the mbuf */ |
---|
696 | /* since an mbuf by itself is too small */ |
---|
697 | MCLGET(m, M_WAIT); |
---|
698 | |
---|
699 | /* set the type of mbuf to ifp (ethernet I/F) */ |
---|
700 | m->m_pkthdr.rcvif = ifp; |
---|
701 | m->m_nextpkt = 0; |
---|
702 | |
---|
703 | /* copy the packet into the cluster pointed to by the mbuf */ |
---|
704 | memcpy((char *)m->m_ext.ext_buf, |
---|
705 | (char *)(rxbuf_hdrs[sc->rx_buf_idx].address & 0xfffffffc), |
---|
706 | pktlen); |
---|
707 | |
---|
708 | /* Release the buffer ASAP back to the EMAC */ |
---|
709 | rxbuf_hdrs[sc->rx_buf_idx].address &= ~RXBUF_ADD_OWNED; |
---|
710 | |
---|
711 | /* set the length of the mbuf */ |
---|
712 | m->m_len = pktlen - (sizeof(struct ether_header) + 4); |
---|
713 | m->m_pkthdr.len = m->m_len; |
---|
714 | |
---|
715 | /* strip off the ethernet header from the mbuf */ |
---|
716 | /* but save the pointer to it */ |
---|
717 | eh = mtod (m, struct ether_header *); |
---|
718 | m->m_data += sizeof(struct ether_header); |
---|
719 | |
---|
720 | /* increment the buffer index */ |
---|
721 | sc->rx_buf_idx++; |
---|
722 | if (sc->rx_buf_idx >= NUM_RXBDS) { |
---|
723 | sc->rx_buf_idx = 0; |
---|
724 | } |
---|
725 | |
---|
726 | /* give all this stuff to the stack */ |
---|
727 | ether_input(ifp, eh, m); |
---|
728 | |
---|
729 | } /* while ADD_OWNED = 0 */ |
---|
730 | |
---|
731 | if (EMAC_REG(EMAC_RSR) & EMAC_RSR_BNA) { |
---|
732 | printk("2:EMAC_BNA\n"); |
---|
733 | } |
---|
734 | if (EMAC_REG(EMAC_RSR) & EMAC_RSR_OVR) { |
---|
735 | printk("2:EMAC_OVR\n"); |
---|
736 | } |
---|
737 | |
---|
738 | |
---|
739 | } /* for (;;) */ |
---|
740 | } /* at91rm9200_emac_rxDaemon() */ |
---|
741 | |
---|
742 | |
---|
743 | /* Show interface statistics */ |
---|
744 | void at91rm9200_emac_stats (at91rm9200_emac_softc_t *sc) |
---|
745 | { |
---|
746 | printf (" Total Interrupts:%-8lu", sc->Interrupts); |
---|
747 | printf (" Rx Interrupts:%-8lu", sc->rxInterrupts); |
---|
748 | printf (" Giant:%-8lu", sc->rxGiant); |
---|
749 | printf (" Non-octet:%-8lu\n", sc->rxNonOctet); |
---|
750 | printf (" Bad CRC:%-8lu", sc->rxBadCRC); |
---|
751 | printf (" Collision:%-8lu", sc->rxCollision); |
---|
752 | printf (" Missed:%-8lu\n", sc->rxMissed); |
---|
753 | |
---|
754 | printf ( " Tx Interrupts:%-8lu", sc->txInterrupts); |
---|
755 | printf ( " Deferred:%-8lu", sc->txDeferred); |
---|
756 | printf (" Lost Carrier:%-8lu\n", sc->txLostCarrier); |
---|
757 | printf ( "Single Collisions:%-8lu", sc->txSingleCollision); |
---|
758 | printf ( "Multiple Collisions:%-8lu", sc->txMultipleCollision); |
---|
759 | printf ("Excessive Collisions:%-8lu\n", sc->txExcessiveCollision); |
---|
760 | printf ( " Total Collisions:%-8lu", sc->txCollision); |
---|
761 | printf ( " Late Collision:%-8lu", sc->txLateCollision); |
---|
762 | printf (" Underrun:%-8lu\n", sc->txUnderrun); |
---|
763 | printf ( " Raw output wait:%-8lu\n", sc->txRawWait); |
---|
764 | } |
---|
765 | |
---|
766 | |
---|
767 | /* Enables at91rm9200_emac interrupts. */ |
---|
768 | static void at91rm9200_emac_isr_on(void) |
---|
769 | { |
---|
770 | /* Enable various TX/RX interrupts */ |
---|
771 | EMAC_REG(EMAC_IER) = (EMAC_INT_RCOM | /* Receive complete */ |
---|
772 | EMAC_INT_RBNA | /* Receive buffer not available */ |
---|
773 | EMAC_INT_TCOM | /* Transmit complete */ |
---|
774 | EMAC_INT_ROVR | /* Receive overrun */ |
---|
775 | EMAC_INT_ABT); /* Abort on DMA transfer */ |
---|
776 | |
---|
777 | return; |
---|
778 | } |
---|
779 | |
---|
780 | /* Driver ioctl handler */ |
---|
781 | static int |
---|
782 | at91rm9200_emac_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
783 | { |
---|
784 | at91rm9200_emac_softc_t *sc = ifp->if_softc; |
---|
785 | int error = 0; |
---|
786 | |
---|
787 | switch (command) { |
---|
788 | case SIOCGIFADDR: |
---|
789 | case SIOCSIFADDR: |
---|
790 | ether_ioctl (ifp, command, data); |
---|
791 | break; |
---|
792 | |
---|
793 | case SIOCSIFFLAGS: |
---|
794 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) |
---|
795 | { |
---|
796 | case IFF_RUNNING: |
---|
797 | at91rm9200_emac_stop (sc); |
---|
798 | break; |
---|
799 | |
---|
800 | case IFF_UP: |
---|
801 | at91rm9200_emac_init (sc); |
---|
802 | break; |
---|
803 | |
---|
804 | case IFF_UP | IFF_RUNNING: |
---|
805 | at91rm9200_emac_stop (sc); |
---|
806 | at91rm9200_emac_init (sc); |
---|
807 | break; |
---|
808 | |
---|
809 | default: |
---|
810 | break; |
---|
811 | } /* switch (if_flags) */ |
---|
812 | break; |
---|
813 | |
---|
814 | case SIO_RTEMS_SHOW_STATS: |
---|
815 | at91rm9200_emac_stats (sc); |
---|
816 | break; |
---|
817 | |
---|
818 | /* |
---|
819 | * FIXME: All sorts of multicast commands need to be added here! |
---|
820 | */ |
---|
821 | default: |
---|
822 | error = EINVAL; |
---|
823 | break; |
---|
824 | } /* switch (command) */ |
---|
825 | return error; |
---|
826 | } |
---|
827 | |
---|
828 | /* interrupt handler */ |
---|
829 | static void at91rm9200_emac_isr (void * unused) |
---|
830 | { |
---|
831 | unsigned long status32; |
---|
832 | |
---|
833 | /* get the ISR status and determine RX or TX */ |
---|
834 | status32 = EMAC_REG(EMAC_ISR); |
---|
835 | |
---|
836 | if (status32 & EMAC_INT_ABT) { |
---|
837 | EMAC_REG(EMAC_IDR) = EMAC_INT_ABT; /* disable it */ |
---|
838 | rtems_panic("AT91RM9200 Ethernet MAC has received an Abort.\n"); |
---|
839 | } |
---|
840 | |
---|
841 | if (status32 & (EMAC_INT_RCOM | /* Receive complete */ |
---|
842 | EMAC_INT_RBNA | /* Receive buffer not available */ |
---|
843 | EMAC_INT_ROVR)) { /* Receive overrun */ |
---|
844 | |
---|
845 | /* disable the RX interrupts */ |
---|
846 | EMAC_REG(EMAC_IDR) = (EMAC_INT_RCOM | /* Receive complete */ |
---|
847 | EMAC_INT_RBNA | /* Receive buf not available */ |
---|
848 | EMAC_INT_ROVR); /* Receive overrun */ |
---|
849 | |
---|
850 | rtems_bsdnet_event_send (softc.rxDaemonTid, START_RECEIVE_EVENT); |
---|
851 | } |
---|
852 | |
---|
853 | if (status32 & EMAC_INT_TCOM) { /* Transmit buffer register empty */ |
---|
854 | |
---|
855 | /* disable the TX interrupts */ |
---|
856 | EMAC_REG(EMAC_IDR) = EMAC_INT_TCOM; |
---|
857 | |
---|
858 | rtems_bsdnet_event_send (softc.txDaemonTid, START_TRANSMIT_EVENT); |
---|
859 | } |
---|
860 | } |
---|
861 | |
---|