source: rtems/c/src/lib/libbsp/arm/csb337/include/at91rm9200_mem.h @ b748dffe

5
Last change on this file since b748dffe was b748dffe, checked in by Sebastian Huber <sebastian.huber@…>, on 12/08/17 at 07:05:04

bsp/csb337: Move libcpu files to BSP

Update #3254.

  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*
2 * AT91RM9200 Memory Controller definitions
3 *
4 * Copyright (c) 2002 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.org/license/LICENSE.
10 */
11#ifndef AT91RM9200_MEM_H
12#define AT91RM9200_MEM_H
13
14/**********************************************************************
15 *       External Bus Interface Unit
16 **********************************************************************/
17#define EBI_CSA             0x00    /* Chip Select Assignment Register */
18#define EBI_CFGR            0x04    /* Configuration Register */
19
20/* Bit Defines */
21/* EBI_CSA - Chip Select Assignment Register */
22#define EBI_CSA_CS4_CF        BIT4    /* 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects */
23#define EBI_CSA_CS3_SMM       BIT3    /* 1 = CS3 is assigned to SmartMedia, 0 = Chip Select */
24#define EBI_CSA_CS1_SDRAM     BIT1    /* 1 = CS1 is assigned to SDRAM, 0 = Chip Select */
25#define EBI_CSA_CS0_BF        BIT0    /* 1 = CS0 is assigned to Burst Flash, 0 = Chip Select */
26
27/* EBI_CFGR     - Configuration Register */
28#define EBI_CFGR_DBPU         BIT0    /* 1 = Disable D0-15 pullups         */
29
30/***************************************************************************
31 * Static Memory Interface Unit
32 ***************************************************************************/
33#define SMC_CSR0            0x00    /* Chip Select Register 0  */
34#define SMC_CSR1            0x04    /* Chip Select Register 1  */
35#define SMC_CSR2            0x08    /* Chip Select Register 2  */
36#define SMC_CSR3            0x0C    /* Chip Select Register 3  */
37#define SMC_CSR4            0x10    /* Chip Select Register 4  */
38#define SMC_CSR5            0x14    /* Chip Select Register 5  */
39#define SMC_CSR6            0x18    /* Chip Select Register 6  */
40#define SMC_CSR7            0x1C    /* Chip Select Register 7  */
41
42/* Bit Defines */
43/* SMC_CSR0 -7 - Chip Selects 0 - 7 Register */
44#define SMC_CSR_RWHOLD(_x_)        ((_x_ & 0x3) << 28)     /* Hold CS after R/W strobes */
45#define SMC_CSR_RWSETUP(_x_)    ((_x_ & 0x3) << 24)     /* Setup CS before R/W strobes */
46#define SMC_CSR_ACSS_0        (0 << 16)           /* Setup/Hold Address 0 clocks before/after CS */
47#define SMC_CSR_ACSS_1        (1 << 16)           /* Setup/Hold Address 1 clock before/after CS */
48#define SMC_CSR_ACSS_2        (2 << 16)           /* Setup/Hold Address 2 clocks before/after CS */
49#define SMC_CSR_ACSS_3        (3 << 16)           /* Setup/Hold Address 3 clocks before/after CS */
50#define SMC_CSR_DRP_NORMAL    0                 /* 0 = normal read protocol */
51#define SMC_CSR_DRP_EARLY     BIT15          /* 1 = early read protocol */
52#define SMC_CSR_DBW_16        (1 << 13)           /* CS DataBus Width = 16-Bits */
53#define SMC_CSR_DBW_8         (2 << 13)           /* CS DataBus Width = 8 Bits */
54#define SMC_CSR_BAT_16_1      0                 /* Single 16-Bit device (when DBW is 16) */
55#define SMC_CSR_BAT_16_2      BIT12          /* Dual 8-Bit devices (when DBW is 16) */
56#define SMC_CSR_TDF(_x_)      ((_x_ & 0xf) << 8)    /* Intercycle Data Float Time */
57#define SMC_CSR_WSEN          BIT7           /* 1 = wait states are enabled */
58#define SMC_CSR_NWS(_x_)      ((_x_ & 0x7f) << 0)     /* Wait States + 1 */
59
60/* ***************************************************************************** */
61/* SDRAM Memory Interface Unit */
62/* ***************************************************************************** */
63#define SDRC_MR             0x00       /* Mode Register */
64#define SDRC_TR             0x04       /* Refresh Timer Register */
65#define SDRC_CR             0x08       /* Configuration Register */
66#define SDRC_SRR            0x0C       /* Self Refresh Register */
67#define SDRC_LPR            0x10       /* Low Power Register */
68#define SDRC_IER            0x14       /* Interrupt Enable Register */
69#define SDRC_IDR            0x18       /* Interrupt Disable Register */
70#define SDRC_IMR            0x1C       /* Interrupt Mask Register */
71#define SDRC_ISR            0x20       /* Interrupt Status Register */
72
73/* Bit Defines */
74/* SDRC_MR - Mode Register */
75#define SDRC_MR_DBW_16        BIT4       /* 1 = SDRAM is 16-bits wide, 0 = 32-bits */
76#define SDRC_MR_NORM          (0 << 0)   /* Normal Mode - All accesses to SDRAM are decoded normally */
77#define SDRC_MR_NOP         (1 << 0)   /* NOP Command is sent to SDRAM */
78#define SDRC_MR_PRE         (2 << 0)   /* Precharge All Command is sent to SDRAM */
79#define SDRC_MR_MRS         (3 << 0)   /* Mode Register Set Command is sent to SDRAM */
80#define SDRC_MR_REF         (4 << 0)   /* Refresh Command is sent to SDRAM */
81
82/* SDRC_TR - Refresh Timer Register */
83#define SDRC_TR_COUNT(_x_)    ((_x_ & 0xfff) << 0)
84
85/* SDRC_CR - Configuration Register */
86#define SDRC_CR_TXSR(_x_)     ((_x_ & 0xf) << 27)     /* CKE to ACT Time */
87#define SDRC_CR_TRAS(_x_)     ((_x_ & 0xf) << 23)     /* ACT to PRE Time */
88#define SDRC_CR_TRCD(_x_)     ((_x_ & 0xf) << 19)     /* RAS to CAS Time */
89#define SDRC_CR_TRP(_x_)      ((_x_ & 0xf) << 15)     /* PRE to ACT Time */
90#define SDRC_CR_TRC(_x_)      ((_x_ & 0xf) << 11)     /* REF to ACT Time */
91#define SDRC_CR_TWR(_x_)      ((_x_ & 0xf) << 7)      /* Write Recovery Time */
92#define SDRC_CR_CAS_2         (2 << 5)   /* Cas Delay = 2, this is the only supported value */
93#define SDRC_CR_NB_2          0        /* 2 Banks per device */
94#define SDRC_CR_NB_4          BIT4       /* 4 Banks per device */
95#define SDRC_CR_NR_11         (0 << 2)   /* Number of rows = 11 */
96#define SDRC_CR_NR_12         (1 << 2)   /* Number of rows = 12 */
97#define SDRC_CR_NR_13         (2 << 2)   /* Number of rows = 13 */
98#define SDRC_CR_NC_8          (0 << 0)   /* Number of columns = 8 */
99#define SDRC_CR_NC_9          (1 << 0)   /* Number of columns = 9 */
100#define SDRC_CR_NC_10         (2 << 0)   /* Number of columns = 10 */
101#define SDRC_CR_NC_11         (3 << 0)   /* Number of columns = 11 */
102
103/* SDRC_SRR - Self Refresh Register */
104#define SDRC_SRR_SRCB         BIT0       /* 1 = Enter Self Refresh */
105
106/* SDRC_LPR - Low Power Register */
107#define SDRC_LPR_LPCB         BIT0       /* 1 = De-assert CKE between accesses */
108
109/* SDRC_IER - Interrupt Enable Register */
110/* SDRC_IDR - Interrupt Disable Register */
111/* SDRC_ISR - Interrupt Mask Register */
112/* SDRC_IMR - Interrupt Mask Register */
113#define SDRC_INT_RES          BIT0       /* Refresh Error Status */
114
115#endif
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