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sed1356_16bit.h @ cfaa366

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Last change on this file since cfaa366 was cfaa366, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 17:55:58

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1	/*
2	* sed1356.h: SED1356 LCD/CRT Controllers for KIT637_V6 (CSB637)
3	* 16-Bit access mode
4	*
5	* Based upon code from MicroMonitor 1.17 from http://www.umonfw.com/
6	* which includes this notice:
7	*
8	**************************************************************************
9	* General notice:
10	* This code is part of a boot-monitor package developed as a generic base
11	* platform for embedded system designs. As such, it is likely to be
12	* distributed to various projects beyond the control of the original
13	* author. Please notify the author of any enhancements made or bugs found
14	* so that all may benefit from the changes. In addition, notification back
15	* to the author will allow the new user to pick up changes that may have
16	* been made by other users after this version of the code was distributed.
17	*
18	* Note1: the majority of this code was edited with 4-space tabs.
19	* Note2: as more and more contributions are accepted, the term "author"
20	* is becoming a mis-representation of credit.
21	*
22	* Original author: Ed Sutter
23	* Email: esutter@alcatel-lucent.com
24	* Phone: 908-582-2351
25	**************************************************************************
26	*
27	* Ed Sutter has been informed that this code is being used in RTEMS.
28	*
29	* The code has been reformatted by Joel Sherrill from OAR Corporation and
30	* Fernando Nicodemos <fgnicodemos@terra.com.br> from NCB - Sistemas
31	* Embarcados Ltda. (Brazil) to be more compliant with RTEMS coding standards
32	* and to eliminate C++ style comments.
33	*
34	* $Id$
35	*/
36
37	#ifndef __sed1356_16bit_h
38	#define __sed1356_16bit_h
39
40	#include "bits.h"
41	/*------------------------------------------------------------------------
42	* cpu specific code must define the following board specific macros.
43	* in cpuio.h. These examples assume the SED135x has been placed in
44	* the correct endian mode via hardware.
45	* #define SED_MEM_BASE 0xf0600000 <-- just example addresses,
46	* #define SED_REG_BASE 0xf0400000 <-- define for each board
47	* #define SED_STEP 1 <-- 1 = device is on 16-bit boundry, 2 = 32-bit boundry, 4 = 64-bit boundry
48	* #define SED_REG16(_x_) (vushortr )(SED_REG_BASE + (_x_ * SED_STEP)) // Control/Status Registers
49	* #define RD_FB16(_reg_,_val_) ((_val_) = ((vushort )((SED_MEM_BASE + (_reg_ * SED_STEP)))))
50	* #define WR_FB16(_reg_,_val_) (((vushort )((SED_MEM_BASE + (_reg_ * 2)))) = (_val_))
51	* Big endian processors
52	* #define H2SED(_x_) ((((x) & 0xff00U) >> 8) \| (((x) & 0x00ffU) << 8))
53	* Little endian
54	* #define H2SED(_x_) (_x_)
55	*
56	*/
57
58	/*
59	* SED1356 registers - 16-Bit Access Mode. The first register
60	* referenced is the even addressed register. The byte offsets
61	* of the odd registers are shown in the comments
62	*/
63	#define SED1356_REG_REV_and_MISC SED_REG16(0x00)
64	#define SED1356_REG_GPIO_CFG SED_REG16(0x04)
65	#define SED1356_REG_GPIO_CTL SED_REG16(0x08)
66	#define SED1356_REG_MD_CFG_RD_LO_and_HI SED_REG16(0x0c)
67	#define SED1356_REG_MCLK_CFG SED_REG16(0x10)
68	#define SED1356_REG_LCD_PCLK_CFG SED_REG16(0x14)
69	#define SED1356_REG_CRT_PCLK_CFG SED_REG16(0x18)
70	#define SED1356_REG_MEDIA_PCLK_CFG SED_REG16(0x1c)
71	#define SED1356_REG_WAIT_STATE SED_REG16(0x1e)
72	#define SED1356_REG_MEM_CFG_and_REF_RATE SED_REG16(0x20)
73	#define SED1356_REG_MEM_TMG0_and_1 SED_REG16(0x2a)
74	#define SED1356_REG_PANEL_TYPE_and_MOD_RATE SED_REG16(0x30)
75	/* LCD Control registers */
76	#define SED1356_REG_LCD_HOR_DISP SED_REG16(0x32)
77	#define SED1356_REG_LCD_HOR_NONDISP_and_START SED_REG16(0x34)
78	#define SED1356_REG_LCD_HOR_PULSE SED_REG16(0x36)
79	#define SED1356_REG_LCD_VER_DISP_HT_LO_and_HI SED_REG16(0x38)
80	#define SED1356_REG_LCD_VER_NONDISP_and_START SED_REG16(0x3a)
81	#define SED1356_REG_LCD_VER_PULSE SED_REG16(0x3c)
82	#define SED1356_REG_LCD_DISP_MODE_and_MISC SED_REG16(0x40)
83	#define SED1356_REG_LCD_DISP_START_LO_and_MID SED_REG16(0x42)
84	#define SED1356_REG_LCD_DISP_START_HI SED_REG16(0x44)
85	#define SED1356_REG_LCD_ADD_OFFSET_LO_and_HI SED_REG16(0x46)
86	#define SED1356_REG_LCD_PIXEL_PAN SED_REG16(0x48)
87	#define SED1356_REG_LCD_FIFO_THRESH_LO_and_HI SED_REG16(0x4a)
88	/* CRT/TV Control registers */
89	#define SED1356_REG_CRT_HOR_DISP SED_REG16(0x50)
90	#define SED1356_REG_CRT_HOR_NONDISP_and_START SED_REG16(0x52)
91	#define SED1356_REG_CRT_HOR_PULSE SED_REG16(0x54)
92	#define SED1356_REG_CRT_VER_DISP_HT_LO_and_HI SED_REG16(0x56)
93	#define SED1356_REG_CRT_VER_NONDISP_and_START SED_REG16(0x58)
94	#define SED1356_REG_CRT_VER_PULSE_and_OUT_CTL SED_REG16(0x5a)
95	#define SED1356_REG_CRT_DISP_MODE SED_REG16(0x60)
96	#define SED1356_REG_CRT_DISP_START_LO_and_MID SED_REG16(0x62)
97	#define SED1356_REG_CRT_DISP_START_HI SED_REG16(0x64)
98	#define SED1356_REG_CRT_ADD_OFFSET_LO_and_HI SED_REG16(0x66)
99	#define SED1356_REG_CRT_PIXEL_PAN SED_REG16(0x68)
100	#define SED1356_REG_CRT_FIFO_THRESH_LO_and_HI SED_REG16(0x6a)
101	/* LCD Cursor Control Registers */
102	#define SED1356_REG_LCD_CURSOR_CTL_and_START_ADD SED_REG16(0x70)
103	#define SED1356_REG_LCD_CURSOR_X_POS_LO_and_HI SED_REG16(0x72)
104	#define SED1356_REG_LCD_CURSOR_Y_POS_LO_and_HI SED_REG16(0x74)
105	#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x76)
106	#define SED1356_REG_LCD_CURSOR_RED_CLR_0 SED_REG16(0x78)
107	#define SED1356_REG_LCD_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x7a)
108	#define SED1356_REG_LCD_CURSOR_RED_CLR_1 SED_REG16(0x7c)
109	#define SED1356_REG_LCD_CURSOR_FIFO_THRESH SED_REG16(0x7e)
110	/* CRT Cursor Control Registers */
111	#define SED1356_REG_CRT_CURSOR_CTL_and_START_ADD SED_REG16(0x80)
112	#define SED1356_REG_CRT_CURSOR_X_POS_LO_and_HI SED_REG16(0x82)
113	#define SED1356_REG_CRT_CURSOR_Y_POS_LO_and_HI SED_REG16(0x84)
114	#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_0 SED_REG16(0x86)
115	#define SED1356_REG_CRT_CURSOR_RED_CLR_0 SED_REG16(0x88)
116	#define SED1356_REG_CRT_CURSOR_BLUE_and_GREEN_CLR_1 SED_REG16(0x8a)
117	#define SED1356_REG_CRT_CURSOR_RED_CLR_1 SED_REG16(0x8c)
118	#define SED1356_REG_CRT_CURSOR_FIFO_THRESH SED_REG16(0x8e)
119	/* BitBlt Control Registers */
120	#define SED1356_REG_BLT_CTL_0_and_1 SED_REG16(0x100)
121	#define SED1356_REG_BLT_ROP_CODE_and_BLT_OP SED_REG16(0x102)
122	#define SED1356_REG_BLT_SRC_START_LO_and_MID SED_REG16(0x104)
123	#define SED1356_REG_BLT_SRC_START_HI SED_REG16(0x106)
124	#define SED1356_REG_BLT_DEST_START_LO_and_MID SED_REG16(0x108)
125	#define SED1356_REG_BLT_DEST_START_HI SED_REG16(0x10a)
126	#define SED1356_REG_BLT_ADD_OFFSET_LO_and_HI SED_REG16(0x10c)
127	#define SED1356_REG_BLT_WID_LO_and_HI SED_REG16(0x110)
128	#define SED1356_REG_BLT_HGT_LO_and_HI SED_REG16(0x112)
129	#define SED1356_REG_BLT_BG_CLR_LO_and_HI SED_REG16(0x114)
130	#define SED1356_REG_BLT_FG_CLR_LO_and_HI SED_REG16(0x118)
131	/* Look-Up Table Control Registers */
132	#define SED1356_REG_LUT_MODE SED_REG16(0x1e0)
133	#define SED1356_REG_LUT_ADD SED_REG16(0x1e2)
134	#define SED1356_REG_LUT_DATA SED_REG16(0x1e4)
135	/* Power and Miscellaneous Control Registers */
136	#define SED1356_REG_PWR_CFG_and_STAT SED_REG16(0x1f0)
137	#define SED1356_REG_WATCHDOG_CTL SED_REG16(0x1f4)
138	#define SED1356_REG_DISP_MODE SED_REG16(0x1fc)
139
140	/*
141	* Bit Assignments - Little Endian, Use H2SED() macro to access
142	*
143	* SED1356_REG_REV_and_MISC - even
144	*/
145	#define SED1356_REV_ID_MASK 0xfc /* ID bits - masks off the rev bits */
146	#define SED1356_REV_ID_1356 BIT4
147	#define SED1356_REV_ID_1355 BIT3
148
149	/* SED1356_REG_REV_and_MISC - odd */
150	#define SED1356_MISC_HOST_DIS BIT7 << 8 /* 0 = enable host access, 1 = disable */
151
152	/* SED1356_REG_GPIO_CFG and SED1356_REG_GPIO_STAT */
153	#define SED1356_GPIO_GPIO3 BIT3 /* 0 = input, 1 = output, if configured as GPIO */
154	#define SED1356_GPIO_GPIO2 BIT2
155	#define SED1356_GPIO_GPIO1 BIT1
156
157	/* SED1356_REG_MCLK_CFG */
158	#define SED1356_MCLK_DIV2 BIT4
159	#define SED1356_MCLK_SRC_BCLK BIT0
160	#define SED1356_MCLK_SRC_CLKI 0x00
161
162	/* SED1356_REG_LCD_PCLK_CFG, SED1356_REG_CRT_PCLK_CFG
163	* and SED1356_REG_MEDIA_PCLK_CFG
164	*/
165	#define SED1356_PCLK_X2 BIT7 /* SED1356_REG_CRT_PCLK_CFG only */
166	#define SED1356_PCLK_DIV1 0x00 << 4
167	#define SED1356_PCLK_DIV2 0x01 << 4
168	#define SED1356_PCLK_DIV3 0x02 << 4
169	#define SED1356_PCLK_DIV4 0x03 << 4
170	#define SED1356_PCLK_SRC_CLKI 0x00
171	#define SED1356_PCLK_SRC_BCLK 0x01
172	#define SED1356_PCLK_SRC_CLKI2 0x02
173	#define SED1356_PCLK_SRC_MCLK 0x03
174
175	/* SED1356_REG_MEM_CFG_and_REF_RATE - even */
176	#define SED1356_MEM_CFG_2CAS_EDO 0x00
177	#define SED1356_MEM_CFG_2CAS_FPM 0x01
178	#define SED1356_MEM_CFG_2WE_EDO 0x02
179	#define SED1356_MEM_CFG_2WE_FPM 0x03
180	#define SED1356_MEM_CFG_MASK 0x03
181
182	/* SED1356_REG_MEM_CFG_and_REF_RATE - odd */
183	#define SED1356_REF_TYPE_CBR 0x00 << 6 << 8
184	#define SED1356_REF_TYPE_SELF 0x01 << 6 << 8
185	#define SED1356_REF_TYPE_NONE 0x02 << 6 << 8
186	#define SED1356_REF_TYPE_MASK 0x03 << 6 << 8
187	#define SED1356_REF_RATE_64 0x00 << 0 << 8 /* MCLK / 64 */
188	#define SED1356_REF_RATE_128 0x01 << 0 << 8 /* MCLK / 128 */
189	#define SED1356_REF_RATE_256 0x02 << 0 << 8 /* MCLK / 256 */
190	#define SED1356_REF_RATE_512 0x03 << 0 << 8 /* MCLK / 512 */
191	#define SED1356_REF_RATE_1024 0x04 << 0 << 8 /* MCLK / 1024 */
192	#define SED1356_REF_RATE_2048 0x05 << 0 << 8 /* MCLK / 2048 */
193	#define SED1356_REF_RATE_4096 0x06 << 0 << 8 /* MCLK / 4096 */
194	#define SED1356_REF_RATE_8192 0x07 << 0 << 8 /* MCLK / 8192 */
195	#define SED1356_REF_RATE_MASK 0x07 << 0 << 8 /* MCLK / 8192 */
196
197	/* SED1356_REG_MEM_TMG0_and_1 - even */
198	#define SED1356_MEM_TMG0_EDO50_MCLK40 0x01
199	#define SED1356_MEM_TMG0_EDO50_MCLK33 0x01
200	#define SED1356_MEM_TMG0_EDO60_MCLK33 0x01
201	#define SED1356_MEM_TMG0_EDO50_MCLK30 0x12
202	#define SED1356_MEM_TMG0_EDO60_MCLK30 0x01
203	#define SED1356_MEM_TMG0_EDO70_MCLK30 0x00
204	#define SED1356_MEM_TMG0_EDO50_MCLK25 0x12
205	#define SED1356_MEM_TMG0_EDO60_MCLK25 0x12
206	#define SED1356_MEM_TMG0_EDO70_MCLK25 0x01
207	#define SED1356_MEM_TMG0_EDO80_MCLK25 0x00
208	#define SED1356_MEM_TMG0_EDO50_MCLK20 0x12
209	#define SED1356_MEM_TMG0_EDO60_MCLK20 0x12
210	#define SED1356_MEM_TMG0_EDO70_MCLK20 0x12
211	#define SED1356_MEM_TMG0_EDO80_MCLK20 0x01
212	#define SED1356_MEM_TMG0_FPM50_MCLK25 0x12
213	#define SED1356_MEM_TMG0_FPM60_MCLK25 0x01
214	#define SED1356_MEM_TMG0_FPM50_MCLK20 0x12
215	#define SED1356_MEM_TMG0_FPM60_MCLK20 0x12
216	#define SED1356_MEM_TMG0_FPM70_MCLK20 0x11
217	#define SED1356_MEM_TMG0_FPM80_MCLK20 0x01
218
219	/* SED1356_REG_MEM_TMG0_and_1 - odd */
220	#define SED1356_MEM_TMG1_EDO50_MCLK40 0x01 << 8
221	#define SED1356_MEM_TMG1_EDO50_MCLK33 0x01 << 8
222	#define SED1356_MEM_TMG1_EDO60_MCLK33 0x01 << 8
223	#define SED1356_MEM_TMG1_EDO50_MCLK30 0x02 << 8
224	#define SED1356_MEM_TMG1_EDO60_MCLK30 0x01 << 8
225	#define SED1356_MEM_TMG1_EDO70_MCLK30 0x00 << 8
226	#define SED1356_MEM_TMG1_EDO50_MCLK25 0x02 << 8
227	#define SED1356_MEM_TMG1_EDO60_MCLK25 0x02 << 8
228	#define SED1356_MEM_TMG1_EDO70_MCLK25 0x01 << 8
229	#define SED1356_MEM_TMG1_EDO80_MCLK25 0x01 << 8
230	#define SED1356_MEM_TMG1_EDO50_MCLK20 0x02 << 8
231	#define SED1356_MEM_TMG1_EDO60_MCLK20 0x02 << 8
232	#define SED1356_MEM_TMG1_EDO70_MCLK20 0x02 << 8
233	#define SED1356_MEM_TMG1_EDO80_MCLK20 0x01 << 8
234	#define SED1356_MEM_TMG1_FPM50_MCLK25 0x02 << 8
235	#define SED1356_MEM_TMG1_FPM60_MCLK25 0x01 << 8
236	#define SED1356_MEM_TMG1_FPM50_MCLK20 0x02 << 8
237	#define SED1356_MEM_TMG1_FPM60_MCLK20 0x02 << 8
238	#define SED1356_MEM_TMG1_FPM70_MCLK20 0x02 << 8
239	#define SED1356_MEM_TMG1_FPM80_MCLK20 0x01 << 8
240
241
242	/* Bit definitions
243	*
244	* SED1356_REG_PANEL_TYPE_AND_MOD_RATE - even
245	*/
246	#define SED1356_PANEL_TYPE_EL BIT7
247	#define SED1356_PANEL_TYPE_4_9 (0x00 << 4) /* Passive 4-Bit, TFT 9-Bit */
248	#define SED1356_PANEL_TYPE_8_12 (0x01 << 4) /* Passive 8-Bit, TFT 12-Bit */
249	#define SED1356_PANEL_TYPE_16 (0x02 << 4) /* Passive 16-Bit, or TFT 18-Bit */
250	#define SED1356_PANEL_TYPE_MASK (0x03 << 4)
251	#define SED1356_PANEL_TYPE_FMT BIT3 /* 0 = Passive Format 1, 1 = Passive Format 2 */
252	#define SED1356_PANEL_TYPE_CLR BIT2 /* 0 = Passive Mono, 1 = Passive Color */
253	#define SED1356_PANEL_TYPE_DUAL BIT1 /* 0 = Passive Single, 1 = Passive Dual */
254	#define SED1356_PANEL_TYPE_TFT BIT0 /* 0 = Passive, 1 = TFT (DUAL, FMT & CLR are don't cares) */
255
256	/* SED1356_REG_CRT_HOR_PULSE, SED1356_REG_CRT_VER_PULSE,
257	* SED1356_REG_LCD_HOR_PULSE and SED1356_REG_LCD_VER_PULSE
258	*/
259	#define SED1356_PULSE_POL_HIGH BIT7 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
260	#define SED1356_PULSE_POL_LOW 0x00 /* 0 = CRT/TFT Pulse is Low, Passive is High, 1 = CRT/TFT Pulse is High, Passive is Low */
261	#define SED1356_PULSE_WID(_x_) (_x_ & 0x0f) /* Pulse Width in Pixels */
262
263	/* SED1356_LCD_DISP_MODE_and_MISC - even */
264	#define SED1356_LCD_DISP_BLANK BIT7 /* 1 = Blank LCD Display */
265	#define SED1356_LCD_DISP_SWIV_NORM (0x00 << 4) /* Used with SED1356_REG_DISP_MODE Bit 6 */
266	#define SED1356_LCD_DISP_SWIV_90 (0x00 << 4)
267	#define SED1356_LCD_DISP_SWIV_180 (0x01 << 4)
268	#define SED1356_LCD_DISP_SWIV_270 (0x01 << 4)
269	#define SED1356_LCD_DISP_SWIV_MASK (0x01 << 4)
270	#define SED1356_LCD_DISP_16BPP 0x05 /* Bit Per Pixel Selection */
271	#define SED1356_LCD_DISP_15BPP 0x04
272	#define SED1356_LCD_DISP_8BPP 0x03
273	#define SED1356_LCD_DISP_4BPP 0x02
274	#define SED1356_LCD_DISP_BPP_MASK 0x07
275
276	/* SED1356_LCD_DISP_MODE_and_MISC - odd */
277	#define SED1356_LCD_MISC_DITH BIT1 << 8 /* 1 = Dither Disable, Passive Panel Only */
278	#define SED1356_LCD_MISC_DUAL BIT0 << 8 /* 1 = Dual Panel Disable, Passive Panel Only */
279
280	/* SED1356_REG_CRT_VER_PULSE_and_OUT_CTL - odd */
281	#define SED1356_CRT_OUT_CHROM BIT5 << 8 /* 1 = TV Chrominance Filter Enable */
282	#define SED1356_CRT_OUT_LUM BIT4 << 8 /* 1 = TV Luminance Filter Enable */
283	#define SED1356_CRT_OUT_DAC_LVL BIT3 << 8 /* 1 = 4.6ma IREF, 0 = 9.2 IREF */
284	#define SED1356_CRT_OUT_SVIDEO BIT1 << 8 /* 1 = S-Video Output, 0 = Composite Video Output */
285	#define SED1356_CRT_OUT_PAL BIT0 << 8 /* 1 = PAL Format Output, 0 = NTSC Format Output */
286
287	/* SED1356_REG_CRT_DISP_MODE */
288	#define SED1356_CRT_DISP_BLANK BIT7 /* 1 = Blank CRT Display */
289	#define SED1356_CRT_DISP_16BPP 0x05 /* Bit Per Pixel Selection */
290	#define SED1356_CRT_DISP_15BPP 0x04
291	#define SED1356_CRT_DISP_8BPP 0x03
292	#define SED1356_CRT_DISP_4BPP 0x02
293	#define SED1356_CRT_DISP_BPP_MASK 0x07
294
295	/* SED1356_DISP_MODE */
296	#define SED1356_DISP_SWIV_NORM (0x00 << 6) /* Used with SED1356_LCD_DISP_MODE Bit 4 */
297	#define SED1356_DISP_SWIV_90 (0x01 << 6)
298	#define SED1356_DISP_SWIV_180 (0x00 << 6)
299	#define SED1356_DISP_SWIV_270 (0x01 << 6)
300	#define SED1356_DISP_MODE_OFF 0x00 /* All Displays Off */
301	#define SED1356_DISP_MODE_LCD 0x01 /* LCD Only */
302	#define SED1356_DISP_MODE_CRT 0x02 /* CRT Only */
303	#define SED1356_DISP_MODE_LCD_CRT 0x03 /* Simultaneous LCD and CRT */
304	#define SED1356_DISP_MODE_TV 0x04 /* TV Only, Flicker Filter Off */
305	#define SED1356_DISP_MODE_TV_LCD 0x05 /* Simultaneous LCD and TV, Flicker Filter Off */
306	#define SED1356_DISP_MODE_TV_FLICK 0x06 /* TV Only, Flicker Filter On */
307	#define SED1356_DISP_MODE_TV_LCD_FLICK 0x07 /* Simultaneous LCD and TV, Flicker Filter On */
308
309	/* SED1356_REG_PWR_CFG and SED1356_REG_PWR_STAT */
310	#define SED1356_PWR_PCLK BIT1 /* SED1356_REG_PWR_STAT only */
311	#define SED1356_PWR_MCLK BIT0
312
313	/* SED1356_REG_VER_NONDISP */
314	#define SED1356_VER_NONDISP BIT7 /* vertical retrace status 1 = in retrace */
315
316	/* Display size defines */
317	extern long PIXELS_PER_ROW;
318	extern long PIXELS_PER_COL;
319	#define BYTES_PER_PIXEL 2
320	extern long COLS_PER_SCREEN;
321	extern long ROWS_PER_SCREEN;
322
323	/* 16-bit pixels are RGB 565 - LSB of RED and BLUE are tied low at the */
324	/* LCD Interface, while the LSB of GREEN is loaded as 0 */
325	#define RED_SUBPIXEL(n) ((n & 0x1f) << 11)
326	#define GREEN_SUBPIXEL(n) ((n & 0x1f) << 5)
327	#define BLUE_SUBPIXEL(n) ((n & 0x1f) << 0)
328
329	/* define a simple VGA style 16-color pallette */
330	#if 0
331	#define LU_BLACK (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x00))
332	#define LU_BLUE (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x0f))
333	#define LU_GREEN (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x0f) \| BLUE_SUBPIXEL(0x00))
334	#define LU_CYAN (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x0f) \| BLUE_SUBPIXEL(0x0f))
335	#define LU_RED (RED_SUBPIXEL(0x0f) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x00))
336	#define LU_VIOLET (RED_SUBPIXEL(0x0f) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x0f))
337	#define LU_YELLOW (RED_SUBPIXEL(0x0f) \| GREEN_SUBPIXEL(0x0f) \| BLUE_SUBPIXEL(0x00))
338	#define LU_GREY (RED_SUBPIXEL(0x0f) \| GREEN_SUBPIXEL(0x0f) \| BLUE_SUBPIXEL(0x0f))
339	#define LU_WHITE (RED_SUBPIXEL(0x17) \| GREEN_SUBPIXEL(0x17) \| BLUE_SUBPIXEL(0x17))
340	#define LU_BRT_BLUE (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x1f))
341	#define LU_BRT_GREEN (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x1f) \| BLUE_SUBPIXEL(0x00))
342	#define LU_BRT_CYAN (RED_SUBPIXEL(0x00) \| GREEN_SUBPIXEL(0x1f) \| BLUE_SUBPIXEL(0x1f))
343	#define LU_BRT_RED (RED_SUBPIXEL(0x1f) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x00))
344	#define LU_BRT_VIOLET (RED_SUBPIXEL(0x1f) \| GREEN_SUBPIXEL(0x00) \| BLUE_SUBPIXEL(0x1f))
345	#define LU_BRT_YELLOW (RED_SUBPIXEL(0x1f) \| GREEN_SUBPIXEL(0x1f) \| BLUE_SUBPIXEL(0x00))
346	#define LU_BRT_WHITE (RED_SUBPIXEL(0x1f) \| GREEN_SUBPIXEL(0x1f) \| BLUE_SUBPIXEL(0x1f))
347	/* RED, GREEN, BLUE Entry */
348	{ 0x00, 0x00, 0x00, }, /* LU_BLACK */
349	{ 0x00, 0x00, 0xA0, }, /* LU_BLUE */
350	{ 0x00, 0xA0, 0x00, }, /* LU_GREEN */
351	{ 0x00, 0xA0, 0xA0, }, /* LU_CYAN */
352	{ 0xA0, 0x00, 0x00, }, /* LU_RED */
353	{ 0xA0, 0x00, 0xA0, }, /* LU_VIOLET */
354	{ 0xA0, 0xA0, 0x00, }, /* LU_YELLOW */
355	{ 0xA0, 0xA0, 0xA0, }, /* LU_WHITE */
356	{ 0x50, 0x50, 0x50, }, /* LU_GREY */
357	{ 0x50, 0x50, 0xF0, }, /* LU_BRT_BLUE */
358	{ 0x50, 0xF0, 0x50, }, /* LU_BRT_GREEN */
359	{ 0x50, 0xF0, 0xF0, }, /* LU_BRT_CYAN */
360	{ 0xF0, 0x50, 0x50, }, /* LU_BRT_RED */
361	{ 0xF0, 0x50, 0xF0, }, /* LU_BRT_VIOLET */
362	{ 0xF0, 0xF0, 0x50, }, /* LU_BRT_YELLOW */
363	{ 0xF0, 0xF0, 0xF0, }, /* LU_BRT_WHITE */
364	#endif
365
366	#define BLUE (0x14 << 0)
367	#define GREEN (0x14 << 6)
368	#define RED (0x14 << 11)
369
370	#define HALF_BLUE (0x0a << 0)
371	#define HALF_GREEN (0x0a << 6)
372	#define HALF_RED (0x0a << 11)
373
374
375	#define BRT_BLUE (0x1e << 0)
376	#define BRT_GREEN (0x1e << 6)
377	#define BRT_RED (0x1e << 11)
378
379	#define LU_BLACK 0
380	#define LU_BLUE (BLUE)
381	#define LU_GREEN (GREEN)
382	#define LU_CYAN (GREEN \| BLUE)
383	#define LU_RED (RED)
384	#define LU_VIOLET (RED \| BLUE)
385	#define LU_YELLOW (RED \| GREEN)
386	#define LU_WHITE (RED \| GREEN \| BLUE)
387	#define LU_GREY (HALF_RED \| HALF_GREEN \| HALF_BLUE)
388	#define LU_BRT_BLUE (HALF_RED \| HALF_GREEN \| BRT_BLUE)
389	#define LU_BRT_GREEN (HALF_RED \| BRT_GREEN \| HALF_BLUE)
390	#define LU_BRT_CYAN (HALF_RED \| BRT_GREEN \| BRT_BLUE)
391	#define LU_BRT_RED (BRT_RED \| HALF_GREEN \| HALF_BLUE)
392	#define LU_BRT_VIOLET (BRT_RED \| HALF_GREEN \| BRT_BLUE)
393	#define LU_BRT_YELLOW (BRT_RED \| BRT_GREEN \| HALF_BLUE)
394	#define LU_BRT_WHITE (BRT_RED \| BRT_GREEN \| BRT_BLUE)
395
396	const ushort vga_lookup[] = {
397	LU_BLACK, /* 0 */
398	LU_BLUE, /* 1 */
399	LU_GREEN, /* 2 */
400	LU_CYAN, /* 3 */
401	LU_RED, /* 4 */
402	LU_VIOLET, /* 5 */
403	LU_YELLOW, /* 6 */
404	LU_WHITE, /* 7 */
405	LU_GREY, /* 8 */
406	LU_BRT_BLUE, /* 9 */
407	LU_BRT_GREEN, /* 10 */
408	LU_BRT_CYAN, /* 11 */
409	LU_BRT_RED, /* 12 */
410	LU_BRT_VIOLET, /* 13 */
411	LU_BRT_YELLOW, /* 14 */
412	LU_BRT_WHITE /* 15 */
413	};
414
415	/* default foreground and background colors */
416	#define SED_BG_DEF 1
417	#define SED_FG_DEF 14
418
419	/* Draw defines */
420	#define TOP 0
421	#define BOTTOM (PIXELS_PER_COL-1)
422	#define LEFT 0
423	#define RIGHT (PIXELS_PER_ROW-1)
424	#define CENTER_X (PIXELS_PER_ROW/2)
425	#define CENTER_Y (PIXELS_PER_COL/2)
426
427
428	/* Vertical and Horizontal Pulse, Start and Non-Display values vary depending
429	* upon the mode. The following section gives some insight into how the
430	* values are arrived at.
431	* ms = milliseconds, us = microseconds, ns = nanoseconds
432	* Mhz = Megaherz, Khz = Kiloherz, Hz = Herz
433	*
434	* ***************************************************************************************************
435	* CRT Mode is 640x480 @ 72Hz VESA compatible timing. PCLK = 31.5Mhz (31.75ns)
436	* ***************************************************************************************************
437	*
438	* CRT MODE HORIZONTAL TIMING PARAMETERS
439	*
440	* \|<-------Tha------->\|
441	* \|___________________\| ______
442	* Display Enable _____________________\| \|____________________\|
443	* \| \|
444	* Horizontal Pulse __ ________\|___________________\|________ __________
445	* \|_________\| \| \| \|________\|
446	* \|<- Thp ->\| \| \| \|
447	* \| \|<-Thbp->\| \| \|
448	* \| \|<-Thfp->\|
449	* \|<----------------------Tht-------------------->\|
450	*
451	* Tha - Active Display Time = 640 pixels
452	* Thp - Horizontal Pulse = 1.27us/31.75ns = 40 pixels
453	* Thbp - Horizontal Front Porch = 1.016us/31.75ns = 32 pixels
454	* Thfp - Horizontal Back Porch = 3.8us/31.75ns = 120 pixels
455	* Tht - Total Horizontal Time = 832 pixels x 32.75ns/pixel = 26.416us or 38.785Khz
456	*
457	* Correlation between horizontal timing parameters and SED registers
458	*/
459	#define SED_HOR_PULSE_WIDTH_CRT 0x07 /* Horizontal Pulse Width Register = (Thp/8) - 1 */
460	#define SED_HOR_PULSE_START_CRT 0x02 /* Horizontal Pulse Start Position Register = ((Thfp + 2)/8) - 1 */
461	#define SED_HOR_NONDISP_CRT 0x17 /* Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1 */
462	/*
463	* CRT MODE VERTICAL TIMING PARAMTERS
464	*
465	* \|<-------Tva------->\|
466	* \|___________________\| ______
467	* Display Enable _____________________\| \|_____________________\|
468	* \| \|
469	* Vertical Pulse __ ________\|___________________\|________ __________
470	* \|_________\| \| \| \|________\|
471	* \|<- Tvp ->\| \| \| \|
472	* \| \|<-Tvbp->\| \| \|
473	* \| \|<-Tvfp->\|
474	* \|<----------------------Tvt-------------------->\|
475	*
476	* Tva - Active Display Time = 480 lines
477	* Tvp - Vertical Pulse = 3 lines
478	* Tvfp - Vertical Front Porch = 9 lines
479	* Tvbp - Vertical Back Porch = 28 lines
480	* Tvt - Total Horizontal Time = 520 lines x 26.416us/line = 13.73632ms or 72.8Hz
481	*
482	* Correlation between vertical timing parameters and SED registers
483	*/
484	#define SED_VER_PULSE_WIDTH_CRT 0x02 // VRTC/FPFRAME Pulse Width Register = Tvp - 1
485	#define SED_VER_PULSE_START_CRT 0x08 // VRTC/FPFRAME Start Position Register = Tvfp - 1
486	#define SED_VER_NONDISP_CRT 0x27 // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
487	/*
488	*****************************************************************************************************
489	* DUAL LCD Mode is 640x480 @ 60Hz VGA compatible timing. PCLK = 25.175Mhz (39.722ns)
490	*****************************************************************************************************
491	*
492	* LCD MODE HORIZONTAL TIMING PARAMTERS
493	*
494	* \|<-------Tha------->\|
495	* \|___________________\| ______
496	* Display Enable _____________________\| \|____________________\|
497	* \| \|
498	* Horizontal Pulse __ ________\|___________________\|________ __________
499	* \|_________\| \| \| \|________\|
500	* \|<- Thp ->\| \| \| \|
501	* \| \|<-Thbp->\| \| \|
502	* \| \|<-Thfp->\|
503	* \|<----------------------Tht-------------------->\|
504	*
505	* Tha - Active Display Time = 640 pixels
506	* Thp - Horizontal Pulse = 3.8us/39.72ns = 96 pixels
507	* Thfp - Horizontal Front Porch = .595us/39.72ns = 16 pixels
508	* Thbp - Horizontal Backporch = 1.9us/39.72ns = 48 pixels
509	* Tht - Total Horizontal Time = = 800 pixels @ 39.72ns/pixel = 31.776us or 31.47Khz
510	*
511	* Correlation between horizontal timing parameters and SED registers
512	*#define SED_HOR_PULSE_WIDTH_LCD 0x0b // HRTC/FPLINE Pulse Width Register = (Thp/8) - 1
513	*#define SED_HOR_PULSE_START_LCD 0x02 // HRTC/FPLINE Start Position Register = (Thfp/8) - 2
514	*#define SED_HOR_NONDISP_LCD 0x13 // Horizontal Non-Display Period Register = ((Thp + Thfp + Thbp)/8) - 1
515	*/
516	extern long SED_HOR_PULSE_WIDTH_LCD;
517	extern long SED_HOR_PULSE_START_LCD;
518	extern long SED_HOR_NONDISP_LCD;
519
520	/*
521	*
522	* LCD MODE VERTICAL TIMING PARAMTERS
523	*
524	* \|<-------Tva------->\|
525	* \|___________________\| ______
526	* Display Enable _____________________\| \|_____________________\|
527	* \| \|
528	* Vertical Pulse __ ________\|___________________\|________ __________
529	* \|_________\| \| \| \|________\|
530	* \|<- Tvp ->\| \| \| \|
531	* \| \|<-Tvbp->\| \| \|
532	* \| \|<-Tvfp->\|
533	* \|<----------------------Tvt-------------------->\|
534	*
535	* Tva - Active Display Time = 480 lines
536	* Tvp - Vertical Pulse = 2 lines
537	* Tvfp - Vertical Front Porch = 10 lines
538	* Tvbp - Vertical Backporch = 33 lines
539	* Tvt - Total Horizontal Time = 525 lines @ 31.776us/line = 16.682ms or 60Hz
540	*
541	* Correlation between vertical timing parameters and SED registers
542	*#define SED_VER_PULSE_WIDTH_LCD 0x01 // VRTC/FPFRAME Pulse Width Register = Tvp - 1
543	*#define SED_VER_PULSE_START_LCD 0x09 // VRTC/FPFRAME Start Position Register = Tvfp - 1
544	*#define SED_VER_NONDISP_LCD 0x2c // Vertical Non-Display Period Register = (Tvp + Tvfp + Tvbp) - 1
545	*/
546	extern long SED_VER_PULSE_WIDTH_LCD;
547	extern long SED_VER_PULSE_START_LCD;
548	extern long SED_VER_NONDISP_LCD;
549
550	#endif

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source: rtems/c/src/lib/libbsp/arm/csb337/console/sed1356_16bit.h @ cfaa366

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