1 | /* |
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2 | * CSB336 Memory Map |
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3 | * |
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4 | * Copyright (c) 2004 by Cogent Computer Systems |
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5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | #include <rtems.h> |
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14 | #include <libcpu/mmu.h> |
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15 | |
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16 | /* Remember, the ARM920 has 64 TLBs. If you have more 1MB sections than |
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17 | * that, you'll have TLB lookups, which could hurt performance. |
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18 | */ |
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19 | mmu_sect_map_t mem_map[] = { |
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20 | /* <phys addr> <virt addr> <size> <flags> */ |
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21 | {0x08200000, 0x00000000, 1, MMU_CACHE_NONE}, /* Mirror of SDRAM */ |
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22 | {0x00100000, 0x00100000, 1, MMU_CACHE_NONE}, /* Bootstrap ROM */ |
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23 | {0x00200000, 0x00200000, 1, MMU_CACHE_NONE}, /* Internal Regs */ |
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24 | {0x08000000, 0x08000000, 32, MMU_CACHE_WTHROUGH}, /* SDRAM */ |
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25 | {0x10000000, 0x10000000, 8, MMU_CACHE_NONE}, /* CS0 - Flash */ |
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26 | {0x12000000, 0x12000000, 1, MMU_CACHE_NONE}, /* CS1 - enet */ |
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27 | {0x13000000, 0x13000000, 1, MMU_CACHE_NONE}, /* CS2 - */ |
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28 | {0x14000000, 0x14000000, 1, MMU_CACHE_NONE}, /* CS3 - */ |
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29 | {0x15000000, 0x15000000, 1, MMU_CACHE_NONE}, /* CS4 - */ |
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30 | {0x16000000, 0x16000000, 1, MMU_CACHE_NONE}, /* CS5 - */ |
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31 | {0x50000000, 0x50000000, 1, MMU_CACHE_NONE}, /* ARM Test Regs */ |
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32 | {0x00000000, 0x00000000, 0, 0} /* The end */ |
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33 | }; |
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