source: rtems/c/src/lib/libbsp/arm/csb336/startup/bspstart.c @ c193baad

4.104.11
Last change on this file since c193baad was c193baad, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 9, 2010 at 8:24:57 PM

unify irq data types and code, merge s3c2400/s3c2410 support

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 * Cogent CSB336 - MC9328MXL SBC startup code
3 *
4 * Copyright (c) 2004 by Cogent Computer Systems
5 * Written by Jay Monkman <jtm@lopingdog.com>
6 *
7 * The license and distribution terms for this file may be
8 * found in the file LICENSE in this distribution or at
9 * http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <bsp.h>
15#include <rtems/bspIo.h>
16#include <mc9328mxl.h>
17
18extern void rtems_irq_mngt_init(void);
19extern void rtems_exception_init_mngt(void);
20
21extern void mmu_set_cpu_async_mode(void);
22
23/*
24 * bsp_start_default - BSP initialization function
25 *
26 *   This function is called before RTEMS is initialized and used
27 *   adjust the kernel's configuration.
28 *
29 *   This function also configures the CPU's memory protection unit.
30 *
31 * RESTRICTIONS/LIMITATIONS:
32 *   Since RTEMS is not configured, no RTEMS functions can be called.
33 *
34 */
35void bsp_start_default( void )
36{
37  int i;
38
39  /* Set the MCU prescaler to divide by 1 */
40  MC9328MXL_PLL_CSCR &= ~MC9328MXL_PLL_CSCR_PRESC;
41
42  /* Enable the MCU PLL */
43  MC9328MXL_PLL_CSCR |= MC9328MXL_PLL_CSCR_MPEN;
44
45  /* Delay to allow time for PLL to get going */
46  for (i = 0; i < 100; i++) {
47    asm volatile ("nop\n");
48  }
49
50  /* Set the CPU to asynchrous clock mode, so it uses its fastest clock */
51  mmu_set_cpu_async_mode();
52
53  /* disable interrupts */
54  MC9328MXL_AITC_INTENABLEL = 0;
55  MC9328MXL_AITC_INTENABLEH = 0;
56
57  /* Set interrupt priority to -1 (allow all priorities) */
58  MC9328MXL_AITC_NIMASK = 0x1f;
59
60  /*
61   * Init rtems exceptions management
62   */
63  rtems_exception_init_mngt();
64
65  /*
66   * Init rtems interrupt management
67   */
68  rtems_irq_mngt_init();
69} /* bsp_start */
70
71/* Calcuate the frequency for perclk1 */
72int get_perclk1_freq(void)
73{
74  unsigned int fin;
75  unsigned int fpll;
76  unsigned int pd;
77  unsigned int mfd;
78  unsigned int mfi;
79  unsigned int mfn;
80  uint32_t reg;
81  int perclk1;
82
83  if (MC9328MXL_PLL_CSCR & MC9328MXL_PLL_CSCR_SYSSEL) {
84    /* Use external oscillator */
85    fin = BSP_OSC_FREQ;
86  } else {
87    /* Use scaled xtal freq */
88    fin = BSP_XTAL_FREQ * 512;
89  }
90
91  /* calculate the output of the system PLL */
92  reg = MC9328MXL_PLL_SPCTL0;
93  pd = ((reg & MC9328MXL_PLL_SPCTL_PD_MASK) >>
94        MC9328MXL_PLL_SPCTL_PD_SHIFT);
95  mfd = ((reg & MC9328MXL_PLL_SPCTL_MFD_MASK) >>
96         MC9328MXL_PLL_SPCTL_MFD_SHIFT);
97  mfi = ((reg & MC9328MXL_PLL_SPCTL_MFI_MASK) >>
98         MC9328MXL_PLL_SPCTL_MFI_SHIFT);
99  mfn = ((reg & MC9328MXL_PLL_SPCTL_MFN_MASK) >>
100         MC9328MXL_PLL_SPCTL_MFN_SHIFT);
101
102#if 0
103  printk("fin = %d\n", fin);
104  printk("pd = %d\n", pd);
105  printk("mfd = %d\n", mfd);
106  printk("mfi = %d\n", mfi);
107  printk("mfn = %d\n", mfn);
108  printk("rounded (fin * mfi) / (pd + 1) = %d\n", (fin * mfi) / (pd + 1));
109  printk("rounded (fin * mfn) / ((pd + 1) * (mfd + 1)) = %d\n",
110         ((long long)fin * mfn) / ((pd + 1) * (mfd + 1)));
111#endif
112
113  fpll = 2 * ( ((fin * mfi  + (pd + 1) / 2) / (pd + 1)) +
114               (((long long)fin * mfn + ((pd + 1) * (mfd + 1)) / 2) /
115               ((pd + 1) * (mfd + 1))) );
116
117  /* calculate the output of the PERCLK1 divider */
118  reg = MC9328MXL_PLL_PCDR;
119  perclk1 = fpll / (1 + ((reg & MC9328MXL_PLL_PCDR_PCLK1_MASK) >>
120                         MC9328MXL_PLL_PCDR_PCLK1_SHIFT));
121
122  return perclk1;
123}
124
125/*
126 *  By making this a weak alias for bsp_start_default, a brave soul
127 *  can override the actual bsp_start routine used.
128 */
129void bsp_start (void) __attribute__ ((weak, alias("bsp_start_default")));
130
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