1 | /* |
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2 | * Cogent CSB336 - MC9328MXL SBC startup code |
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3 | */ |
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4 | |
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5 | /* |
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6 | * Copyright (c) 2004 by Cogent Computer Systems |
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7 | * Written by Jay Monkman <jtm@lopingdog.com> |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #include <bsp.h> |
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15 | #include <bsp/irq-generic.h> |
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16 | #include <rtems/bspIo.h> |
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17 | #include <mc9328mxl.h> |
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18 | #include <libcpu/mmu.h> |
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19 | |
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20 | /* |
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21 | * bsp_start_default - BSP initialization function |
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22 | * |
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23 | * This function is called before RTEMS is initialized and used |
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24 | * adjust the kernel's configuration. |
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25 | * |
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26 | * This function also configures the CPU's memory protection unit. |
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27 | * |
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28 | * RESTRICTIONS/LIMITATIONS: |
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29 | * Since RTEMS is not configured, no RTEMS functions can be called. |
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30 | * |
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31 | */ |
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32 | static void bsp_start_default( void ) |
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33 | { |
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34 | int i; |
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35 | |
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36 | /* Set the MCU prescaler to divide by 1 */ |
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37 | MC9328MXL_PLL_CSCR &= ~MC9328MXL_PLL_CSCR_PRESC; |
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38 | |
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39 | /* Enable the MCU PLL */ |
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40 | MC9328MXL_PLL_CSCR |= MC9328MXL_PLL_CSCR_MPEN; |
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41 | |
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42 | /* Delay to allow time for PLL to get going */ |
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43 | for (i = 0; i < 100; i++) { |
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44 | __asm__ volatile ("nop\n"); |
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45 | } |
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46 | |
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47 | /* Set the CPU to asynchrous clock mode, so it uses its fastest clock */ |
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48 | mmu_set_cpu_async_mode(); |
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49 | |
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50 | /* disable interrupts */ |
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51 | MC9328MXL_AITC_INTENABLEL = 0; |
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52 | MC9328MXL_AITC_INTENABLEH = 0; |
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53 | |
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54 | /* Set interrupt priority to -1 (allow all priorities) */ |
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55 | MC9328MXL_AITC_NIMASK = 0x1f; |
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56 | |
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57 | /* |
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58 | * Init rtems interrupt management |
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59 | */ |
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60 | bsp_interrupt_initialize(); |
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61 | } /* bsp_start */ |
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62 | |
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63 | /* Calcuate the frequency for perclk1 */ |
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64 | int get_perclk1_freq(void) |
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65 | { |
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66 | unsigned int fin; |
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67 | unsigned int fpll; |
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68 | unsigned int pd; |
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69 | unsigned int mfd; |
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70 | unsigned int mfi; |
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71 | unsigned int mfn; |
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72 | uint32_t reg; |
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73 | int perclk1; |
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74 | |
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75 | if (MC9328MXL_PLL_CSCR & MC9328MXL_PLL_CSCR_SYSSEL) { |
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76 | /* Use external oscillator */ |
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77 | fin = BSP_OSC_FREQ; |
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78 | } else { |
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79 | /* Use scaled xtal freq */ |
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80 | fin = BSP_XTAL_FREQ * 512; |
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81 | } |
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82 | |
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83 | /* calculate the output of the system PLL */ |
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84 | reg = MC9328MXL_PLL_SPCTL0; |
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85 | pd = ((reg & MC9328MXL_PLL_SPCTL_PD_MASK) >> |
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86 | MC9328MXL_PLL_SPCTL_PD_SHIFT); |
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87 | mfd = ((reg & MC9328MXL_PLL_SPCTL_MFD_MASK) >> |
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88 | MC9328MXL_PLL_SPCTL_MFD_SHIFT); |
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89 | mfi = ((reg & MC9328MXL_PLL_SPCTL_MFI_MASK) >> |
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90 | MC9328MXL_PLL_SPCTL_MFI_SHIFT); |
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91 | mfn = ((reg & MC9328MXL_PLL_SPCTL_MFN_MASK) >> |
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92 | MC9328MXL_PLL_SPCTL_MFN_SHIFT); |
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93 | |
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94 | #if 0 |
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95 | printk("fin = %d\n", fin); |
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96 | printk("pd = %d\n", pd); |
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97 | printk("mfd = %d\n", mfd); |
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98 | printk("mfi = %d\n", mfi); |
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99 | printk("mfn = %d\n", mfn); |
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100 | printk("rounded (fin * mfi) / (pd + 1) = %d\n", (fin * mfi) / (pd + 1)); |
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101 | printk("rounded (fin * mfn) / ((pd + 1) * (mfd + 1)) = %d\n", |
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102 | ((long long)fin * mfn) / ((pd + 1) * (mfd + 1))); |
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103 | #endif |
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104 | |
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105 | fpll = 2 * ( ((fin * mfi + (pd + 1) / 2) / (pd + 1)) + |
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106 | (((long long)fin * mfn + ((pd + 1) * (mfd + 1)) / 2) / |
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107 | ((pd + 1) * (mfd + 1))) ); |
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108 | |
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109 | /* calculate the output of the PERCLK1 divider */ |
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110 | reg = MC9328MXL_PLL_PCDR; |
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111 | perclk1 = fpll / (1 + ((reg & MC9328MXL_PLL_PCDR_PCLK1_MASK) >> |
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112 | MC9328MXL_PLL_PCDR_PCLK1_SHIFT)); |
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113 | |
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114 | return perclk1; |
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115 | } |
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116 | |
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117 | /* |
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118 | * By making this a weak alias for bsp_start_default, a brave soul |
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119 | * can override the actual bsp_start routine used. |
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120 | */ |
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121 | void bsp_start (void) __attribute__ ((weak, alias("bsp_start_default"))); |
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122 | |
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