[1a3d1f3e] | 1 | /* |
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| 2 | * Cogent CSB336 - MC9328MXL SBC startup code |
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| 3 | * |
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| 4 | * Copyright (c) 2004 by Cogent Computer Systems |
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| 5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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[b7774253] | 6 | * |
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[1a3d1f3e] | 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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[0c0ae29] | 9 | * http://www.rtems.com/license/LICENSE. |
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[1a3d1f3e] | 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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[b7774253] | 13 | |
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[1a3d1f3e] | 14 | #include <bsp.h> |
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[b1cc4ec9] | 15 | #include <rtems/bspIo.h> |
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[1a3d1f3e] | 16 | #include <mc9328mxl.h> |
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| 17 | |
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| 18 | extern void rtems_irq_mngt_init(void); |
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[b7774253] | 19 | extern void mmu_set_cpu_async_mode(void); |
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| 20 | |
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| 21 | /* |
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| 22 | * bsp_start_default - BSP initialization function |
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| 23 | * |
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| 24 | * This function is called before RTEMS is initialized and used |
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| 25 | * adjust the kernel's configuration. |
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| 26 | * |
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| 27 | * This function also configures the CPU's memory protection unit. |
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| 28 | * |
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| 29 | * RESTRICTIONS/LIMITATIONS: |
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| 30 | * Since RTEMS is not configured, no RTEMS functions can be called. |
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| 31 | * |
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| 32 | */ |
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[1a3d1f3e] | 33 | void bsp_start_default( void ) |
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| 34 | { |
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[b7774253] | 35 | int i; |
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| 36 | |
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| 37 | /* Set the MCU prescaler to divide by 1 */ |
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| 38 | MC9328MXL_PLL_CSCR &= ~MC9328MXL_PLL_CSCR_PRESC; |
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| 39 | |
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| 40 | /* Enable the MCU PLL */ |
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| 41 | MC9328MXL_PLL_CSCR |= MC9328MXL_PLL_CSCR_MPEN; |
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| 42 | |
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| 43 | /* Delay to allow time for PLL to get going */ |
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| 44 | for (i = 0; i < 100; i++) { |
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| 45 | asm volatile ("nop\n"); |
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| 46 | } |
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[1a3d1f3e] | 47 | |
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[b7774253] | 48 | /* Set the CPU to asynchrous clock mode, so it uses its fastest clock */ |
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| 49 | mmu_set_cpu_async_mode(); |
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[1a3d1f3e] | 50 | |
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[b7774253] | 51 | /* disable interrupts */ |
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| 52 | MC9328MXL_AITC_INTENABLEL = 0; |
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| 53 | MC9328MXL_AITC_INTENABLEH = 0; |
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| 54 | |
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| 55 | /* Set interrupt priority to -1 (allow all priorities) */ |
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| 56 | MC9328MXL_AITC_NIMASK = 0x1f; |
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| 57 | |
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| 58 | /* |
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| 59 | * Init rtems exceptions management |
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| 60 | */ |
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| 61 | rtems_exception_init_mngt(); |
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| 62 | |
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| 63 | /* |
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| 64 | * Init rtems interrupt management |
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| 65 | */ |
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| 66 | rtems_irq_mngt_init(); |
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| 67 | } /* bsp_start */ |
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[1a3d1f3e] | 68 | |
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| 69 | /* Calcuate the frequency for perclk1 */ |
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| 70 | int get_perclk1_freq(void) |
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| 71 | { |
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[b7774253] | 72 | unsigned int fin; |
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| 73 | unsigned int fpll; |
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| 74 | unsigned int pd; |
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| 75 | unsigned int mfd; |
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| 76 | unsigned int mfi; |
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| 77 | unsigned int mfn; |
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| 78 | uint32_t reg; |
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| 79 | int perclk1; |
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| 80 | |
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| 81 | if (MC9328MXL_PLL_CSCR & MC9328MXL_PLL_CSCR_SYSSEL) { |
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| 82 | /* Use external oscillator */ |
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| 83 | fin = BSP_OSC_FREQ; |
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| 84 | } else { |
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| 85 | /* Use scaled xtal freq */ |
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| 86 | fin = BSP_XTAL_FREQ * 512; |
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| 87 | } |
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| 88 | |
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| 89 | /* calculate the output of the system PLL */ |
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| 90 | reg = MC9328MXL_PLL_SPCTL0; |
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| 91 | pd = ((reg & MC9328MXL_PLL_SPCTL_PD_MASK) >> |
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| 92 | MC9328MXL_PLL_SPCTL_PD_SHIFT); |
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| 93 | mfd = ((reg & MC9328MXL_PLL_SPCTL_MFD_MASK) >> |
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| 94 | MC9328MXL_PLL_SPCTL_MFD_SHIFT); |
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| 95 | mfi = ((reg & MC9328MXL_PLL_SPCTL_MFI_MASK) >> |
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| 96 | MC9328MXL_PLL_SPCTL_MFI_SHIFT); |
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| 97 | mfn = ((reg & MC9328MXL_PLL_SPCTL_MFN_MASK) >> |
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| 98 | MC9328MXL_PLL_SPCTL_MFN_SHIFT); |
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[1a3d1f3e] | 99 | |
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| 100 | #if 0 |
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[b7774253] | 101 | printk("fin = %d\n", fin); |
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| 102 | printk("pd = %d\n", pd); |
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| 103 | printk("mfd = %d\n", mfd); |
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| 104 | printk("mfi = %d\n", mfi); |
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| 105 | printk("mfn = %d\n", mfn); |
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| 106 | printk("rounded (fin * mfi) / (pd + 1) = %d\n", (fin * mfi) / (pd + 1)); |
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| 107 | printk("rounded (fin * mfn) / ((pd + 1) * (mfd + 1)) = %d\n", |
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| 108 | ((long long)fin * mfn) / ((pd + 1) * (mfd + 1))); |
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[1a3d1f3e] | 109 | #endif |
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| 110 | |
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[b7774253] | 111 | fpll = 2 * ( ((fin * mfi + (pd + 1) / 2) / (pd + 1)) + |
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| 112 | (((long long)fin * mfn + ((pd + 1) * (mfd + 1)) / 2) / |
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| 113 | ((pd + 1) * (mfd + 1))) ); |
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[1a3d1f3e] | 114 | |
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[b7774253] | 115 | /* calculate the output of the PERCLK1 divider */ |
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| 116 | reg = MC9328MXL_PLL_PCDR; |
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| 117 | perclk1 = fpll / (1 + ((reg & MC9328MXL_PLL_PCDR_PCLK1_MASK) >> |
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| 118 | MC9328MXL_PLL_PCDR_PCLK1_SHIFT)); |
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[1a3d1f3e] | 119 | |
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[b7774253] | 120 | return perclk1; |
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[1a3d1f3e] | 121 | } |
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| 122 | |
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| 123 | /* |
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| 124 | * By making this a weak alias for bsp_start_default, a brave soul |
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| 125 | * can override the actual bsp_start routine used. |
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| 126 | */ |
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| 127 | void bsp_start (void) __attribute__ ((weak, alias("bsp_start_default"))); |
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| 128 | |
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