source: rtems/c/src/lib/libbsp/arm/csb336/start/start.S @ 8d992be9

4.115
Last change on this file since 8d992be9 was 8d992be9, checked in by Sebastian Huber <sebastian.huber@…>, on 12/03/10 at 10:52:07

2010-12-03 Sebastian Huber <sebastian.huber@…>

  • bsp_specs, start/start.S, startup/linkcmds: Use linker command base file.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 * Cogent CSB336 startup code
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 *
9 * http://www.rtems.com/license/LICENSE.
10 *
11 *
12 * $Id$
13 */
14
15#include <bsp/linker-symbols.h>
16
17/* Some standard definitions...*/
18.equ PSR_MODE_USR,       0x10
19.equ PSR_MODE_FIQ,       0x11
20.equ PSR_MODE_IRQ,       0x12
21.equ PSR_MODE_SVC,       0x13
22.equ PSR_MODE_ABT,       0x17
23.equ PSR_MODE_UNDEF,     0x1B
24.equ PSR_MODE_SYS,       0x1F
25
26.equ PSR_I,              0x80
27.equ PSR_F,              0x40
28.equ PSR_T,              0x20
29
30.text
31.globl  _start
32_start:
33        /*
34         * Since I don't plan to return to the bootloader,
35         * I don't have to save the registers.
36         *
37         * I'll just set the CPSR for SVC mode, interrupts
38         * off, and ARM instructions.
39         */
40        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
41        msr     cpsr, r0
42
43        /* zero the bss */
44        ldr     r1, =bsp_section_bss_end
45        ldr     r0, =bsp_section_bss_begin
46
47_bss_init:
48        mov     r2, #0
49        cmp     r0, r1
50        strlot  r2, [r0], #4
51        blo     _bss_init        /* loop while r0 < r1 */
52
53
54        /* --- Initialize stack pointer registers */
55        /* Enter IRQ mode and set up the IRQ stack pointer */
56        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
57        msr     cpsr, r0
58        ldr     r1, =bsp_stack_irq_size
59        ldr     sp, =bsp_stack_irq_begin
60        add     sp, sp, r1
61
62        /* Enter FIQ mode and set up the FIQ stack pointer */
63        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
64        msr     cpsr, r0
65        ldr     r1, =bsp_stack_fiq_size
66        ldr     sp, =bsp_stack_fiq_begin
67        add     sp, sp, r1
68
69        /* Enter ABT mode and set up the ABT stack pointer */
70        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
71        msr     cpsr, r0
72        ldr     r1, =bsp_stack_abt_size
73        ldr     sp, =bsp_stack_abt_begin
74        add     sp, sp, r1
75
76        /* Enter UNDEF mode and set up the UNDEF stack pointer */
77        mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)     /* No interrupts */
78        msr     cpsr, r0
79        ldr     r1, =bsp_stack_und_size
80        ldr     sp, =bsp_stack_und_begin
81        add     sp, sp, r1
82
83        /* Set up the SVC stack pointer last and stay in SVC mode */
84        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
85        msr     cpsr, r0
86        ldr     r1, =bsp_stack_svc_size
87        ldr     sp, =bsp_stack_svc_begin
88        add     sp, sp, r1
89        sub     sp, sp, #0x64
90
91        /*
92         * Initialize the MMU. After we return, the MMU is enabled,
93         * and memory may be remapped. I hope we don't remap this
94         * memory away.
95         */
96        ldr     r0, =mem_map
97        bl      mmu_init
98
99        /*
100         * Initialize the exception vectors. This includes the
101         * exceptions vectors (0x00000000-0x0000001c), and the
102         * pointers to the exception handlers (0x00000020-0x0000003c).
103         */
104        mov     r0, #0
105        adr     r1, vector_block
106        ldmia   r1!, {r2-r9}
107        stmia   r0!, {r2-r9}
108        ldmia   r1!, {r2-r9}
109        stmia   r0!, {r2-r9}
110
111        /* Now we are prepared to start the BSP's C code */
112        mov     r0, #0
113        bl      boot_card
114
115        /*
116         * Theoretically, we could return to what started us up,
117         * but we'd have to have saved the registers and stacks.
118         * Instead, we'll just reset.
119         */
120        bl      bsp_reset
121
122        /* We shouldn't get here. If we do, hang */
123_hang:  b       _hang
124
125
126/*
127 * This is the exception vector table and the pointers to
128 * the functions that handle the exceptions. It's a total
129 * of 16 words (64 bytes)
130 */
131vector_block:
132        ldr     pc, Reset_Handler
133        ldr     pc, Undefined_Handler
134        ldr     pc, SWI_Handler
135        ldr     pc, Prefetch_Handler
136        ldr     pc, Abort_Handler
137        nop
138        ldr     pc, IRQ_Handler
139        ldr     pc, FIQ_Handler
140
141Reset_Handler:          b       bsp_reset
142Undefined_Handler:      b       Undefined_Handler
143SWI_Handler:            b       SWI_Handler
144Prefetch_Handler:       b       Prefetch_Handler
145Abort_Handler:          b       Abort_Handler
146                        nop
147IRQ_Handler:            b       IRQ_Handler
148FIQ_Handler:            b       FIQ_Handler
149
150.globl Reset_Handler
151.globl Undefined_Handler
152.globl SWI_Handler
153.globl Prefetch_Handler
154.globl Abort_Handler
155.globl IRQ_Handler
156.globl FIQ_Handler
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