source: rtems/c/src/lib/libbsp/arm/csb336/start/start.S @ 0afac6a

4.115
Last change on this file since 0afac6a was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.
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File size: 4.7 KB
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1/*
2 * Cogent CSB336 startup code
3 *
4 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rtems.org/license/LICENSE.
9 */
10
11#include <bsp/linker-symbols.h>
12
13/* Some standard definitions...*/
14.equ PSR_MODE_USR,       0x10
15.equ PSR_MODE_FIQ,       0x11
16.equ PSR_MODE_IRQ,       0x12
17.equ PSR_MODE_SVC,       0x13
18.equ PSR_MODE_ABT,       0x17
19.equ PSR_MODE_UNDEF,     0x1B
20.equ PSR_MODE_SYS,       0x1F
21
22.equ PSR_I,              0x80
23.equ PSR_F,              0x40
24.equ PSR_T,              0x20
25
26.section .bsp_start_text,"ax"
27         .code 32
28_start_jump_at_origin:
29        ldr     pc, _start_address
30_start_address:
31        .word   _start
32
33.text
34.globl  _start
35_start:
36        /*
37         * Since I don't plan to return to the bootloader,
38         * I don't have to save the registers.
39         *
40         * I'll just set the CPSR for SVC mode, interrupts
41         * off, and ARM instructions.
42         */
43        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
44        msr     cpsr, r0
45
46        /* zero the bss */
47        ldr     r1, =bsp_section_bss_end
48        ldr     r0, =bsp_section_bss_begin
49
50_bss_init:
51        mov     r2, #0
52        cmp     r0, r1
53        strlot  r2, [r0], #4
54        blo     _bss_init        /* loop while r0 < r1 */
55
56
57        /* --- Initialize stack pointer registers */
58        /* Enter IRQ mode and set up the IRQ stack pointer */
59        mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)     /* No interrupts */
60        msr     cpsr, r0
61        ldr     r1, =bsp_stack_irq_size
62        ldr     sp, =bsp_stack_irq_begin
63        add     sp, sp, r1
64
65        /* Enter FIQ mode and set up the FIQ stack pointer */
66        mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)     /* No interrupts */
67        msr     cpsr, r0
68        ldr     r1, =bsp_stack_fiq_size
69        ldr     sp, =bsp_stack_fiq_begin
70        add     sp, sp, r1
71
72        /* Enter ABT mode and set up the ABT stack pointer */
73        mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)     /* No interrupts */
74        msr     cpsr, r0
75        ldr     r1, =bsp_stack_abt_size
76        ldr     sp, =bsp_stack_abt_begin
77        add     sp, sp, r1
78
79        /* Enter UNDEF mode and set up the UNDEF stack pointer */
80        mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)     /* No interrupts */
81        msr     cpsr, r0
82        ldr     r1, =bsp_stack_und_size
83        ldr     sp, =bsp_stack_und_begin
84        add     sp, sp, r1
85
86        /* Set up the SVC stack pointer last and stay in SVC mode */
87        mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)     /* No interrupts */
88        msr     cpsr, r0
89        ldr     r1, =bsp_stack_svc_size
90        ldr     sp, =bsp_stack_svc_begin
91        add     sp, sp, r1
92        sub     sp, sp, #0x64
93
94        /*
95         * Initialize the MMU. After we return, the MMU is enabled,
96         * and memory may be remapped. I hope we don't remap this
97         * memory away.
98         */
99        ldr     r0, =mem_map
100        bl      mmu_init
101
102        /*
103         * Initialize the exception vectors. This includes the
104         * exceptions vectors (0x00000000-0x0000001c), and the
105         * pointers to the exception handlers (0x00000020-0x0000003c).
106         */
107        mov     r0, #0
108        adr     r1, vector_block
109        ldmia   r1!, {r2-r9}
110        stmia   r0!, {r2-r9}
111        ldmia   r1!, {r2-r9}
112        stmia   r0!, {r2-r9}
113
114        /* Now we are prepared to start the BSP's C code */
115        mov     r0, #0
116        bl      boot_card
117
118        /*
119         * Theoretically, we could return to what started us up,
120         * but we'd have to have saved the registers and stacks.
121         * Instead, we'll just reset.
122         */
123        bl      bsp_reset
124
125        /* We shouldn't get here. If we do, hang */
126_hang:  b       _hang
127
128
129/*
130 * This is the exception vector table and the pointers to
131 * the functions that handle the exceptions. It's a total
132 * of 16 words (64 bytes)
133 */
134vector_block:
135        ldr     pc, Reset_Handler
136        ldr     pc, Undefined_Handler
137        ldr     pc, SWI_Handler
138        ldr     pc, Prefetch_Handler
139        ldr     pc, Abort_Handler
140        nop
141        ldr     pc, IRQ_Handler
142        ldr     pc, FIQ_Handler
143
144Reset_Handler:          b       bsp_reset
145Undefined_Handler:      b       Undefined_Handler
146SWI_Handler:            b       SWI_Handler
147Prefetch_Handler:       b       Prefetch_Handler
148Abort_Handler:          b       Abort_Handler
149                        nop
150IRQ_Handler:            b       IRQ_Handler
151FIQ_Handler:            b       FIQ_Handler
152
153.globl Reset_Handler
154.globl Undefined_Handler
155.globl SWI_Handler
156.globl Prefetch_Handler
157.globl Abort_Handler
158.globl IRQ_Handler
159.globl FIQ_Handler
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