[1a3d1f3e] | 1 | /* |
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| 2 | * Helper functions for SMSC LAN91C11x |
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| 3 | * |
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| 4 | * Copyright (c) 2004 by Cogent Computer Systems |
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| 5 | * Written by Jay Monkman <jtm@lopingdog.com> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * |
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[0c0ae29] | 10 | * http://www.rtems.com/license/LICENSE. |
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[1a3d1f3e] | 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | #include <rtems.h> |
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| 15 | #include "lan91c11x.h" |
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| 16 | |
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| 17 | uint16_t lan91c11x_read_reg(int reg) |
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| 18 | { |
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| 19 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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| 20 | uint16_t old_bank; |
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| 21 | uint16_t val; |
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| 22 | rtems_interrupt_level level; |
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| 23 | |
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[f3343c6e] | 24 | rtems_interrupt_disable(level); |
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[1a3d1f3e] | 25 | |
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| 26 | /* save the bank register */ |
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| 27 | old_bank = ptr[7] & 0x7; |
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| 28 | |
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| 29 | /* set the bank register */ |
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| 30 | ptr[7] = (reg >> 4) & 0x7; |
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| 31 | |
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| 32 | val = ptr[((reg & 0xf) >> 1)]; |
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| 33 | |
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| 34 | /* restore the bank register */ |
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| 35 | ptr[7] = old_bank; |
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| 36 | |
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[f3343c6e] | 37 | rtems_interrupt_enable(level); |
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[1a3d1f3e] | 38 | return val; |
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| 39 | } |
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| 40 | |
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| 41 | void lan91c11x_write_reg(int reg, uint16_t value) |
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| 42 | { |
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| 43 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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| 44 | uint16_t old_bank; |
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| 45 | rtems_interrupt_level level; |
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| 46 | |
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[f3343c6e] | 47 | rtems_interrupt_disable(level); |
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[1a3d1f3e] | 48 | |
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| 49 | /* save the bank register */ |
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| 50 | old_bank = ptr[7] & 0x7; |
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| 51 | |
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| 52 | /* set the bank register */ |
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| 53 | ptr[7] = (reg >> 4) & 0x7; |
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| 54 | |
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| 55 | ptr[((reg & 0xf) >> 1)] = value; |
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| 56 | |
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| 57 | /* restore the bank register */ |
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| 58 | ptr[7] = old_bank; |
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| 59 | |
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[f3343c6e] | 60 | rtems_interrupt_enable(level); |
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[1a3d1f3e] | 61 | } |
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| 62 | |
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| 63 | uint16_t lan91c11x_read_reg_fast(int reg) |
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| 64 | { |
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| 65 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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| 66 | uint16_t val; |
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| 67 | |
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| 68 | val = ptr[((reg & 0xf) >> 1)]; |
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| 69 | |
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| 70 | return val; |
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| 71 | } |
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| 72 | |
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| 73 | void lan91c11x_write_reg_fast(int reg, uint16_t value) |
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| 74 | { |
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| 75 | volatile uint16_t *ptr = (uint16_t *)LAN91C11X_BASE_ADDR; |
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| 76 | |
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| 77 | ptr[((reg & 0xf) >> 1)] = value; |
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| 78 | } |
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| 79 | |
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| 80 | |
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| 81 | uint16_t lan91c11x_read_phy_reg(int reg) |
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| 82 | { |
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| 83 | int i; |
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| 84 | uint16_t mask; |
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| 85 | uint16_t bits[64]; |
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| 86 | int clk_idx = 0; |
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| 87 | int input_idx = 0; |
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| 88 | uint16_t phydata; |
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| 89 | |
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| 90 | /* 32 consecutive ones on MDO to establish sync */ |
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| 91 | for (i = 0; i < 32; ++i) { |
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| 92 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 93 | } |
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| 94 | |
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| 95 | /* Start code <01> */ |
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| 96 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 97 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 98 | |
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| 99 | /* Read command <10> */ |
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| 100 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 101 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 102 | |
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| 103 | /* Output the PHY address, msb first - Internal PHY is address 0 */ |
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| 104 | for (i = 0; i < 5; ++i) { |
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| 105 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 106 | } |
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| 107 | |
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| 108 | /* Output the phy register number, msb first */ |
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| 109 | mask = 0x10; |
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| 110 | for (i = 0; i < 5; ++i) { |
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| 111 | if (reg & mask) { |
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| 112 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 113 | } else { |
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| 114 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 115 | } |
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| 116 | |
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| 117 | |
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| 118 | /* Shift to next lowest bit */ |
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| 119 | mask >>= 1; |
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| 120 | } |
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| 121 | |
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| 122 | /* 1 bit time for turnaround */ |
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| 123 | bits[clk_idx++] = 0; |
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| 124 | |
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| 125 | /* Input starts at this bit time */ |
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| 126 | input_idx = clk_idx; |
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| 127 | |
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| 128 | /* Will input 16 bits */ |
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| 129 | for (i = 0; i < 16; ++i) { |
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| 130 | bits[clk_idx++] = 0; |
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| 131 | } |
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| 132 | |
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| 133 | /* Final clock bit */ |
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| 134 | bits[clk_idx++] = 0; |
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| 135 | |
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| 136 | /* Turn off all MII Interface bits */ |
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| 137 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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| 138 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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| 139 | |
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| 140 | /* Clock all 64 cycles */ |
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| 141 | for (i = 0; i < sizeof bits; ++i) { |
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| 142 | /* Clock Low - output data */ |
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| 143 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]); |
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| 144 | rtems_task_wake_after(1); |
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| 145 | |
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| 146 | /* Clock Hi - input data */ |
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| 147 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK); |
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| 148 | rtems_task_wake_after(1); |
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| 149 | bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI; |
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| 150 | } |
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| 151 | |
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| 152 | /* Return to idle state */ |
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| 153 | /* Set clock to low, data to low, and output tristated */ |
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| 154 | lan91c11x_write_reg(LAN91C11X_MGMT, lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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| 155 | rtems_task_wake_after(1); |
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| 156 | |
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| 157 | /* Recover input data */ |
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| 158 | phydata = 0; |
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| 159 | for (i = 0; i < 16; ++i) { |
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| 160 | phydata <<= 1; |
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| 161 | |
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| 162 | if (bits[input_idx++] & LAN91C11X_MGMT_MDI) { |
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| 163 | phydata |= 0x0001; |
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| 164 | } |
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| 165 | } |
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| 166 | |
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| 167 | return phydata; |
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| 168 | } |
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| 169 | |
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| 170 | |
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| 171 | |
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| 172 | void lan91c11x_write_phy_reg(int reg, uint16_t phydata) |
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| 173 | { |
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| 174 | int i; |
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| 175 | ushort mask; |
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| 176 | ushort bits[64]; |
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| 177 | int clk_idx = 0; |
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| 178 | |
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| 179 | /* 32 consecutive ones on MDO to establish sync */ |
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| 180 | for (i = 0; i < 32; ++i) { |
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| 181 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 182 | } |
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| 183 | |
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| 184 | /* Start code <01> */ |
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| 185 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 186 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 187 | |
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| 188 | /* Write command <01> */ |
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| 189 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 190 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 191 | |
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| 192 | /* Output the PHY address, msb first - Internal PHY is address 0 */ |
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| 193 | for (i = 0; i < 5; ++i) { |
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| 194 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 195 | } |
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| 196 | |
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| 197 | /* Output the phy register number, msb first */ |
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| 198 | mask = 0x10; |
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| 199 | for (i = 0; i < 5; ++i) { |
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| 200 | if (reg & mask) { |
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| 201 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 202 | } else { |
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| 203 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 204 | } |
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| 205 | |
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| 206 | /* Shift to next lowest bit */ |
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| 207 | mask >>= 1; |
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| 208 | } |
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| 209 | |
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| 210 | /* 2 extra bit times for turnaround */ |
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| 211 | bits[clk_idx++] = 0; |
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| 212 | bits[clk_idx++] = 0; |
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| 213 | |
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| 214 | /* Write out 16 bits of data, msb first */ |
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| 215 | mask = 0x8000; |
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| 216 | for (i = 0; i < 16; ++i) { |
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| 217 | if (phydata & mask) { |
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| 218 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE | LAN91C11X_MGMT_MDO; |
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| 219 | } else { |
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| 220 | bits[clk_idx++] = LAN91C11X_MGMT_MDOE; |
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| 221 | } |
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| 222 | |
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| 223 | /* Shift to next lowest bit */ |
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| 224 | mask >>= 1; |
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| 225 | } |
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| 226 | |
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| 227 | /* Turn off all MII Interface bits */ |
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| 228 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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| 229 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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| 230 | |
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| 231 | /* Clock all 64 cycles */ |
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| 232 | for (i = 0; i < sizeof bits; ++i) { |
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| 233 | /* Clock Low - output data */ |
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| 234 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i]); |
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| 235 | rtems_task_wake_after(1); |
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| 236 | |
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| 237 | /* Clock Hi - input data */ |
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| 238 | lan91c11x_write_reg(LAN91C11X_MGMT, bits[i] | LAN91C11X_MGMT_MCLK); |
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| 239 | rtems_task_wake_after(1); |
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| 240 | bits[i] |= lan91c11x_read_reg(LAN91C11X_MGMT) & LAN91C11X_MGMT_MDI; |
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| 241 | } |
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| 242 | |
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| 243 | /* Return to idle state */ |
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| 244 | /* Set clock to low, data to low, and output tristated */ |
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| 245 | lan91c11x_write_reg(LAN91C11X_MGMT, |
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| 246 | lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0); |
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| 247 | rtems_task_wake_after(1); |
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| 248 | |
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| 249 | } |
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| 250 | |
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| 251 | |
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| 252 | |
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