[1cfcfd3] | 1 | /* |
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| 2 | * Interrupt handler Header file |
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| 3 | * |
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[f4dc319a] | 4 | * Copyright (c) 2010 embedded brains GmbH. |
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| 5 | * |
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[1cfcfd3] | 6 | * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com> |
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[359e537] | 7 | * |
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[1cfcfd3] | 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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[c499856] | 10 | * http://www.rtems.org/license/LICENSE. |
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[1cfcfd3] | 11 | */ |
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| 12 | |
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| 13 | #ifndef __IRQ_H__ |
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| 14 | #define __IRQ_H__ |
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| 15 | |
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| 16 | #ifndef __asm__ |
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| 17 | |
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| 18 | #include <rtems.h> |
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[f4dc319a] | 19 | #include <rtems/irq.h> |
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| 20 | #include <rtems/irq-extension.h> |
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[1cfcfd3] | 21 | |
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[f4dc319a] | 22 | #endif /* __asm__ */ |
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[1cfcfd3] | 23 | |
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[7afe5a2] | 24 | /* possible interrupt sources on the MC9328MXL */ |
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[359e537] | 25 | #define BSP_INT_UART3_PFERR 0 |
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| 26 | #define BSP_INT_UART3_RTS 1 |
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| 27 | #define BSP_INT_UART3_DTR 2 |
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| 28 | #define BSP_INT_UART3_UARTC 3 |
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| 29 | #define BSP_INT_UART3_TX 4 |
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| 30 | #define BSP_INT_PEN_UP 5 |
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[2c24794] | 31 | #define BSP_INT_CSI 6 |
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[359e537] | 32 | #define BSP_INT_MMA_MAC 7 |
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[2c24794] | 33 | #define BSP_INT_MMA 8 |
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| 34 | #define BSP_INT_COMP 9 |
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[359e537] | 35 | #define BSP_INT_MSIRQ 10 |
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| 36 | #define BSP_INT_GPIO_PORTA 11 |
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| 37 | #define BSP_INT_GPIO_PORTB 12 |
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| 38 | #define BSP_INT_GPIO_PORTC 13 |
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| 39 | #define BSP_INT_LCDC 14 |
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| 40 | #define BSP_INT_SIM_IRQ 15 |
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| 41 | #define BSP_INT_SIM_DATA 16 |
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[2c24794] | 42 | #define BSP_INT_RTC 17 |
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[359e537] | 43 | #define BSP_INT_RTC_SAM 18 |
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| 44 | #define BSP_INT_UART2_PFERR 19 |
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| 45 | #define BSP_INT_UART2_RTS 20 |
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| 46 | #define BSP_INT_UART2_DTR 21 |
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| 47 | #define BSP_INT_UART2_UARTC 22 |
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| 48 | #define BSP_INT_UART2_TX 23 |
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| 49 | #define BSP_INT_UART2_RX 24 |
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| 50 | #define BSP_INT_UART1_PFERR 25 |
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| 51 | #define BSP_INT_UART1_RTS 26 |
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| 52 | #define BSP_INT_UART1_DTR 27 |
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| 53 | #define BSP_INT_UART1_UARTC 28 |
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| 54 | #define BSP_INT_UART1_TX 29 |
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| 55 | #define BSP_INT_UART1_RX 30 |
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| 56 | #define BSP_INT_RES31 31 |
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| 57 | #define BSP_INT_RES32 32 |
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| 58 | #define BSP_INT_PEN_DATA 33 |
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[2c24794] | 59 | #define BSP_INT_PWM 34 |
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[359e537] | 60 | #define BSP_INT_MMC_IRQ 35 |
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| 61 | #define BSP_INT_SSI2_TX 36 |
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| 62 | #define BSP_INT_SSI2_RX 37 |
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| 63 | #define BSP_INT_SSI2_ERR 38 |
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[2c24794] | 64 | #define BSP_INT_I2C 39 |
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| 65 | #define BSP_INT_SPI2 40 |
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| 66 | #define BSP_INT_SPI1 41 |
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[359e537] | 67 | #define BSP_INT_SSI_TX 42 |
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| 68 | #define BSP_INT_SSI_TX_ERR 43 |
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| 69 | #define BSP_INT_SSI_RX 44 |
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| 70 | #define BSP_INT_SSI_RX_ERR 45 |
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| 71 | #define BSP_INT_TOUCH 46 |
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| 72 | #define BSP_INT_USBD0 47 |
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| 73 | #define BSP_INT_USBD1 48 |
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| 74 | #define BSP_INT_USBD2 49 |
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| 75 | #define BSP_INT_USBD3 50 |
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| 76 | #define BSP_INT_USBD4 51 |
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| 77 | #define BSP_INT_USBD5 52 |
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| 78 | #define BSP_INT_USBD6 53 |
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| 79 | #define BSP_INT_UART3_RX 54 |
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| 80 | #define BSP_INT_BTSYS 55 |
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| 81 | #define BSP_INT_BTTIM 56 |
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| 82 | #define BSP_INT_BTWUI 57 |
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| 83 | #define BSP_INT_TIMER2 58 |
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| 84 | #define BSP_INT_TIMER1 59 |
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| 85 | #define BSP_INT_DMA_ERR 60 |
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[2c24794] | 86 | #define BSP_INT_DMA 61 |
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[359e537] | 87 | #define BSP_INT_GPIO_PORTD 62 |
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[2c24794] | 88 | #define BSP_INT_WDT 63 |
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| 89 | #define BSP_MAX_INT 64 |
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[359e537] | 90 | |
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[f4dc319a] | 91 | #define BSP_INTERRUPT_VECTOR_MIN 0 |
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[1cfcfd3] | 92 | |
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[f4dc319a] | 93 | #define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1) |
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[1cfcfd3] | 94 | |
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| 95 | #endif /* __IRQ_H__ */ |
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