1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_beagle |
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5 | * |
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6 | * @brief Support for PWM for the BeagleBone Black. |
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7 | */ |
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8 | |
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9 | /** |
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10 | * Copyright (c) 2016 Punit Vara <punitvara@gmail.com> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | |
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17 | /** This file is based on |
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18 | * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c |
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19 | */ |
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20 | |
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21 | #include <libcpu/am335x.h> |
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22 | #include <stdio.h> |
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23 | #include <bsp/gpio.h> |
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24 | #include <bsp/bbb-gpio.h> |
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25 | #include <bsp.h> |
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26 | #include <bsp/bbb-pwm.h> |
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27 | #include <bsp/beagleboneblack.h> |
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28 | |
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29 | /* Currently these definitions are for BeagleBone Black board only |
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30 | * Later on Beagle-xM board support can be added in this code. |
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31 | * After support gets added if condition should be removed |
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32 | */ |
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33 | #if IS_AM335X |
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34 | |
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35 | /* |
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36 | * @brief This function selects EPWM module to be enabled |
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37 | * |
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38 | * @param pwm_id It is the instance number of EPWM of pwm sub system. |
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39 | * |
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40 | * @return Base Address of respective pwm instant. |
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41 | */ |
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42 | static uint32_t select_pwm(BBB_PWMSS pwm_id) |
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43 | { |
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44 | uint32_t baseAddr=0; |
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45 | |
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46 | if (pwm_id == BBB_PWMSS0) { |
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47 | baseAddr = AM335X_EPWM_0_REGS; |
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48 | } else if (pwm_id == BBB_PWMSS1) { |
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49 | baseAddr = AM335X_EPWM_1_REGS; |
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50 | } else if (pwm_id == BBB_PWMSS2) { |
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51 | baseAddr = AM335X_EPWM_2_REGS; |
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52 | } else { |
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53 | baseAddr = 0; |
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54 | } |
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55 | return baseAddr; |
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56 | } |
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57 | |
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58 | /* |
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59 | * @brief This function selects PWM Sub system to be enabled |
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60 | * |
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61 | * @param pwmss_id The instance number of ePWMSS whose system clocks |
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62 | * have to be configured. |
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63 | * |
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64 | * @return Base Address of respective pwmss instant. |
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65 | */ |
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66 | static uint32_t select_pwmss(BBB_PWMSS pwmss_id) |
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67 | { |
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68 | uint32_t baseAddr=0; |
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69 | |
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70 | if (pwmss_id == BBB_PWMSS0) { |
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71 | baseAddr = AM335X_PWMSS0_MMAP_ADDR; |
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72 | } else if (pwmss_id == BBB_PWMSS1) { |
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73 | baseAddr = AM335X_PWMSS1_MMAP_ADDR; |
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74 | } else if (pwmss_id == BBB_PWMSS2) { |
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75 | baseAddr = AM335X_PWMSS2_MMAP_ADDR; |
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76 | } else { |
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77 | baseAddr = 0; |
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78 | } |
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79 | return baseAddr; |
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80 | } |
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81 | |
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82 | bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id) |
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83 | { |
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84 | bool is_valid = true; |
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85 | |
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86 | if(pwm_id == BBB_PWMSS0) { |
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87 | if (pin_no == BBB_P9_21_0B) { |
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88 | REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(BBB_P9_21_MUX_PWM); |
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89 | } else if (pin_no == BBB_P9_22_0A) { |
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90 | REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(BBB_P9_22_MUX_PWM); |
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91 | } else if (pin_no == BBB_P9_29_0B) { |
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92 | REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(BBB_P9_29_MUX_PWM); |
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93 | } else if (pin_no == BBB_P9_31_0A) { |
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94 | REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(BBB_P9_31_MUX_PWM); |
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95 | } else { |
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96 | is_valid = false; |
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97 | } |
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98 | |
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99 | } else if (pwm_id == BBB_PWMSS1) { |
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100 | if (pin_no == BBB_P8_34_1B) { |
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101 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(BBB_P8_34_MUX_PWM); |
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102 | } else if (pin_no == BBB_P8_36_1A) { |
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103 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(BBB_P8_36_MUX_PWM); |
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104 | } else if (pin_no == BBB_P9_14_1A) { |
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105 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(2)) = BBB_MUXMODE(BBB_P9_14_MUX_PWM); |
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106 | } else if (pin_no == BBB_P9_16_1B) { |
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107 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(3)) = BBB_MUXMODE(BBB_P9_16_MUX_PWM); |
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108 | } else { |
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109 | is_valid = false; |
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110 | } |
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111 | } else if (pwm_id == BBB_PWMSS2) { |
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112 | if (pin_no == BBB_P8_13_2B) { |
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113 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(BBB_P8_13_MUX_PWM); |
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114 | } else if (pin_no == BBB_P8_19_2A) { |
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115 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(BBB_P8_19_MUX_PWM); |
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116 | } else if (pin_no == BBB_P8_45_2A) { |
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117 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(BBB_P8_45_MUX_PWM); |
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118 | } else if (pin_no == BBB_P8_46_2B) { |
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119 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(BBB_P8_46_MUX_PWM); |
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120 | } else { |
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121 | is_valid = false; |
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122 | } |
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123 | } else { |
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124 | is_valid = false; |
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125 | } |
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126 | return is_valid; |
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127 | } |
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128 | |
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129 | /** |
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130 | * @brief This function Enables TBCLK(Time Base Clock) for specific |
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131 | * EPWM instance of pwmsubsystem. |
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132 | * |
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133 | * @param instance It is the instance number of EPWM of pwmsubsystem. |
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134 | * |
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135 | * @return true if successful |
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136 | * false if unsuccessful |
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137 | **/ |
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138 | static bool pwmss_tbclk_enable(BBB_PWMSS instance) |
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139 | { |
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140 | uint32_t enable_bit; |
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141 | bool is_valid = true; |
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142 | |
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143 | if (instance == BBB_PWMSS0) { |
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144 | enable_bit = AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN; |
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145 | } else if (instance == BBB_PWMSS1) { |
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146 | enable_bit = AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN; |
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147 | } else if (instance == BBB_PWMSS2) { |
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148 | enable_bit = AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN; |
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149 | } else { |
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150 | is_valid = false; |
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151 | } |
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152 | |
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153 | if (is_valid) |
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154 | { |
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155 | REG(AM335X_PADCONF_BASE + AM335X_PWMSS_CTRL) |= enable_bit; |
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156 | } |
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157 | |
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158 | return is_valid; |
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159 | } |
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160 | |
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161 | /** |
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162 | * @brief This functions enables clock for EHRPWM module in PWMSS subsystem. |
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163 | * |
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164 | * @param pwm_id It is the instance number of EPWM of pwm sub system. |
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165 | * |
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166 | * @return true if successful |
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167 | * false if unsuccessful |
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168 | * |
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169 | **/ |
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170 | static bool pwm_clock_enable(BBB_PWMSS pwm_id) |
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171 | { |
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172 | const bool id_is_valid = pwm_id < BBB_PWMSS_COUNT; |
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173 | bool status = true; |
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174 | |
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175 | if (id_is_valid) { |
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176 | const uint32_t baseAddr = select_pwmss(pwm_id); |
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177 | REG(baseAddr + AM335X_PWMSS_CLKCONFIG) |= AM335X_PWMSS_CLK_EN_ACK; |
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178 | } else { |
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179 | status = false; |
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180 | } |
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181 | return status; |
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182 | } |
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183 | |
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184 | /** |
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185 | * @brief This function configures the L3 and L4_PER system clocks. |
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186 | * It also configures the system clocks for the specified ePWMSS |
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187 | * instance. |
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188 | * |
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189 | * @param pwmss_id The instance number of ePWMSS whose system clocks |
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190 | * have to be configured. |
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191 | * |
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192 | * 'pwmss_id' can take one of the following values: |
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193 | * (0 <= pwmss_id <= 2) |
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194 | * |
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195 | * @return True if successful |
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196 | * False if Unsuccessful |
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197 | */ |
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198 | static bool pwmss_module_clk_config(BBB_PWMSS pwmss_id) |
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199 | { |
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200 | bool is_valid = true; |
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201 | |
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202 | if(pwmss_id == BBB_PWMSS0) { |
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203 | const uint32_t is_functional = AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC << |
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204 | AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT; |
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205 | const uint32_t clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL; |
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206 | const uint32_t idle_bits = AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST; |
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207 | const uint32_t is_enable = AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE; |
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208 | const uint32_t module_mode = AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE; |
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209 | |
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210 | REG(clkctrl) |= is_enable; |
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211 | while((REG(clkctrl) & module_mode) != is_enable); |
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212 | while((REG(clkctrl) & idle_bits) != is_functional); |
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213 | } |
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214 | else if(pwmss_id == BBB_PWMSS1) { |
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215 | const uint32_t is_functional = AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC << |
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216 | AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT; |
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217 | const uint32_t clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL; |
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218 | const uint32_t idle_bits = AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST; |
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219 | const uint32_t is_enable = AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE; |
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220 | const uint32_t module_mode = AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE; |
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221 | |
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222 | REG(clkctrl) |= is_enable; |
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223 | while((REG(clkctrl) & module_mode) != is_enable); |
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224 | while((REG(clkctrl) & idle_bits) != is_functional); |
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225 | } else if(pwmss_id == BBB_PWMSS2) { |
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226 | const uint32_t is_functional = AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC << |
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227 | AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT; |
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228 | const uint32_t clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL; |
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229 | const uint32_t idle_bits = AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST; |
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230 | const uint32_t is_enable = AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE; |
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231 | const uint32_t module_mode = AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE; |
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232 | |
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233 | REG(clkctrl) |= is_enable; |
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234 | while((REG(clkctrl) & module_mode) != is_enable); |
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235 | while((REG(clkctrl) & idle_bits) != is_functional); |
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236 | } else |
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237 | is_valid = false; |
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238 | return is_valid; |
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239 | } |
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240 | |
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241 | bool beagle_pwm_init(BBB_PWMSS pwmss_id) |
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242 | { |
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243 | const bool id_is_valid = pwmss_id < BBB_PWMSS_COUNT; |
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244 | bool status = true; |
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245 | |
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246 | if(id_is_valid) { |
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247 | pwmss_module_clk_config(pwmss_id); |
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248 | pwm_clock_enable(pwmss_id); |
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249 | pwmss_tbclk_enable(pwmss_id); |
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250 | } else { |
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251 | status =false; |
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252 | } |
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253 | return status; |
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254 | } |
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255 | |
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256 | int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b) |
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257 | { |
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258 | uint32_t baseAddr; |
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259 | int status = 1; |
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260 | float cycle = 0.0f,divisor = 0; |
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261 | unsigned int i,j; |
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262 | const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0}; |
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263 | const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0}; |
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264 | int NearCLKDIV =7,NearHSPCLKDIV =7,NearTBPRD =0; |
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265 | |
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266 | if (pwm_freq <= BBB_PWM_FREQ_THRESHOLD) { |
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267 | status =0; |
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268 | } |
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269 | |
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270 | if (duty_a < 0.0f || duty_a > 100.0f || duty_b < 0.0f || duty_b > 100.0f) { |
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271 | status = 0; |
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272 | } |
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273 | duty_a /= 100.0f; |
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274 | duty_b /= 100.0f; |
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275 | |
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276 | /** 10^9 /Hz compute time per cycle (ns) */ |
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277 | cycle = 1000000000.0f / pwm_freq; |
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278 | |
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279 | /** am335x provide (128* 14) divider and per TBPRD means 10ns when divider |
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280 | * and max TBPRD is 65535 so max cycle is 128 * 8 * 14 * 65535 * 10ns */ |
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281 | divisor = (cycle / 655350.0f); |
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282 | if (divisor > (128 * 14)) { |
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283 | return 0; |
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284 | } |
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285 | else { |
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286 | for (i=0;i<8;i++) { |
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287 | for(j=0 ; j<8; j++) { |
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288 | if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV] |
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289 | * HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > divisor)) { |
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290 | NearCLKDIV = i; |
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291 | NearHSPCLKDIV = j; |
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292 | } |
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293 | } |
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294 | } |
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295 | |
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296 | baseAddr = select_pwm(pwm_id); |
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297 | |
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298 | REG16(baseAddr + AM335X_EPWM_TBCTL) &= ~(AM335X_TBCTL_CLKDIV_MASK | AM335X_TBCTL_HSPCLKDIV_MASK); |
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299 | const uint16_t clkdiv_clear = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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300 | (~AM335X_EPWM_TBCTL_CLKDIV)); |
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301 | const uint16_t clkdiv_write = ((NearCLKDIV |
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302 | << AM335X_EPWM_TBCTL_CLKDIV_SHIFT) & AM335X_EPWM_TBCTL_CLKDIV); |
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303 | REG16(baseAddr + AM335X_EPWM_TBCTL) = clkdiv_clear | clkdiv_write; |
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304 | const uint16_t hspclkdiv_clear = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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305 | (~AM335X_EPWM_TBCTL_HSPCLKDIV)); |
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306 | const uint16_t hspclkdiv_write = ((NearHSPCLKDIV << |
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307 | AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT) & AM335X_EPWM_TBCTL_HSPCLKDIV); |
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308 | REG16(baseAddr + AM335X_EPWM_TBCTL) = hspclkdiv_clear | hspclkdiv_write; |
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309 | NearTBPRD = (cycle / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV])); |
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310 | const uint16_t shadow_mask = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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311 | (~AM335X_EPWM_PRD_LOAD_SHADOW_MASK)); |
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312 | const uint16_t shadow_disable = (((bool)AM335X_EPWM_SHADOW_WRITE_DISABLE << |
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313 | AM335X_EPWM_TBCTL_PRDLD_SHIFT) & AM335X_EPWM_PRD_LOAD_SHADOW_MASK); |
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314 | REG16(baseAddr + AM335X_EPWM_TBCTL) = shadow_mask | shadow_disable; |
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315 | const uint16_t counter_mask = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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316 | (~AM335X_EPWM_COUNTER_MODE_MASK)); |
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317 | const uint16_t counter_shift = (((unsigned int)AM335X_EPWM_COUNT_UP << |
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318 | AM335X_TBCTL_CTRMODE_SHIFT) & AM335X_EPWM_COUNTER_MODE_MASK); |
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319 | REG16(baseAddr + AM335X_EPWM_TBCTL) = counter_mask | counter_shift; |
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320 | /*setting clock divider and freeze time base*/ |
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321 | REG16(baseAddr + AM335X_EPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * duty_b); |
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322 | REG16(baseAddr + AM335X_EPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * duty_a); |
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323 | REG16(baseAddr + AM335X_EPWM_TBPRD) = (unsigned short)NearTBPRD; |
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324 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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325 | } |
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326 | return status; |
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327 | } |
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328 | |
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329 | bool beagle_pwm_enable(BBB_PWMSS pwmid) |
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330 | { |
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331 | const bool id_is_valid = pwmid < BBB_PWMSS_COUNT; |
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332 | bool status = true; |
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333 | |
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334 | if (id_is_valid) { |
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335 | const uint32_t baseAddr = select_pwm(pwmid); |
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336 | /* Initially set EPWMxA o/p high , when increasing counter = CMPA toggle o/p of EPWMxA */ |
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337 | REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XAHIGH | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT); |
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338 | /* Initially set EPWMxB o/p high , when increasing counter = CMPA toggle o/p of EPWMxB */ |
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339 | REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLB_ZRO_XBHIGH | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT); |
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340 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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341 | /* Set counter mode : Up-count mode */ |
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342 | REG16(baseAddr + AM335X_EPWM_TBCTL) |= AM335X_TBCTL_FREERUN | AM335X_TBCTL_CTRMODE_UP; |
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343 | } else { |
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344 | status =false; |
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345 | } |
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346 | return status; |
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347 | } |
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348 | |
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349 | bool beagle_pwm_disable(BBB_PWMSS pwmid) |
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350 | { |
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351 | const bool id_is_valid = pwmid < BBB_PWMSS_COUNT; |
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352 | bool status = true; |
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353 | |
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354 | if (id_is_valid) { |
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355 | const uint32_t baseAddr = select_pwm(pwmid); |
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356 | REG16(baseAddr + AM335X_EPWM_TBCTL) = AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE; |
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357 | REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XALOW | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT); |
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358 | REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLA_ZRO_XBLOW | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT); |
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359 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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360 | } else { |
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361 | status = false; |
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362 | } |
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363 | return status; |
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364 | } |
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365 | |
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366 | /** |
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367 | * @brief This functions determines whether time base clock is enabled for EPWMSS |
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368 | * |
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369 | * @param pwmss_id The instance number of ePWMSS whose time base clock need to |
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370 | * be checked |
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371 | * |
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372 | * @return returns 4 for PWMSS_ID = 2 |
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373 | * returns 2 for PWMSS_ID = 1 |
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374 | * returns 1 for PWMSS_ID = 0 |
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375 | **/ |
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376 | static int pwmss_tb_clock_check(unsigned int pwmss_id) |
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377 | { |
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378 | unsigned int reg_value; |
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379 | |
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380 | /*control module check*/ |
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381 | reg_value = REG(AM335X_CONTROL_MODULE + AM335X_PWMSS_CTRL); |
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382 | return (reg_value & (1 << pwmss_id)); |
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383 | } |
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384 | |
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385 | /** |
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386 | * @brief This functions determines whether clock for EPWMSS is enabled or not. |
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387 | * |
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388 | * @param It is the Memory address of the PWMSS instance used. |
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389 | * |
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390 | * @return |
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391 | * |
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392 | **/ |
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393 | static unsigned int pwmss_clock_en_status(unsigned int pwmid) |
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394 | { |
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395 | unsigned int status; |
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396 | const uint32_t baseAddr = select_pwmss(pwmid); |
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397 | |
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398 | status = REG(baseAddr + AM335X_PWMSS_CLKSTATUS); |
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399 | status = status >> 8 & 0x1; |
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400 | return status; |
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401 | } |
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402 | |
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403 | bool beagle_pwmss_is_running(unsigned int pwmss_id) |
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404 | { |
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405 | const bool id_is_valid = pwmss_id < BBB_PWMSS_COUNT; |
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406 | bool status=true; |
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407 | |
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408 | if (id_is_valid) { |
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409 | status = pwmss_clock_en_status(pwmss_id); |
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410 | if(status){ |
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411 | status = pwmss_tb_clock_check(pwmss_id); |
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412 | } else { |
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413 | status = false; |
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414 | } |
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415 | } else { |
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416 | status = false; |
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417 | } |
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418 | return status; |
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419 | } |
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420 | |
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421 | #endif |
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422 | |
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423 | /* For support of BeagleboardxM */ |
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424 | #if IS_DM3730 |
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425 | |
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426 | /* Currently this section is just to satisfy |
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427 | * GPIO API and to make the build successful. |
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428 | * Later on support can be added here. |
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429 | */ |
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430 | bool beagle_pwm_init(BBB_PWMSS pwmss_id) |
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431 | { |
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432 | return false; |
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433 | } |
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434 | bool beagle_pwm_disable(BBB_PWMSS pwmid) |
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435 | { |
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436 | return false; |
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437 | } |
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438 | bool beagle_pwm_enable(BBB_PWMSS pwmid) |
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439 | { |
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440 | return false; |
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441 | } |
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442 | int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b) |
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443 | { |
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444 | return -1; |
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445 | } |
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446 | bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id) |
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447 | { |
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448 | return false; |
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449 | } |
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450 | bool beagle_pwmss_is_running(unsigned int pwmss_id) |
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451 | { |
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452 | return false; |
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453 | } |
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454 | #endif |
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