1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_beagle |
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5 | * |
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6 | * @brief Support for PWM for the BeagleBone Black. |
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7 | */ |
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8 | |
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9 | /** |
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10 | * Copyright (c) 2016 Punit Vara <punitvara at gmail.com> |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.org/license/LICENSE. |
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15 | */ |
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16 | |
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17 | /** This file is based on |
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18 | * https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c |
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19 | */ |
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20 | |
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21 | #include <libcpu/am335x.h> |
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22 | #include <stdio.h> |
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23 | #include <bsp/gpio.h> |
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24 | #include <bsp/bbb-gpio.h> |
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25 | #include <bsp.h> |
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26 | #include <bsp/bbb-pwm.h> |
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27 | |
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28 | /* Currently these definitions are for BeagleBone Black board only |
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29 | * Later on Beagle-xM board support can be added in this code. |
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30 | * After support gets added if condition should be removed |
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31 | */ |
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32 | #if IS_AM335X |
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33 | |
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34 | /* |
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35 | * @brief This function select PWM module to be enabled |
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36 | * |
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37 | * @param pwm_id It is the instance number of EPWM of pwm sub system. |
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38 | * |
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39 | * @return Base Address of respective pwm instant. |
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40 | */ |
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41 | static uint32_t select_pwmss(uint32_t pwm_id) |
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42 | { |
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43 | uint32_t baseAddr=0; |
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44 | if (pwm_id == BBB_PWMSS0) |
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45 | { |
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46 | baseAddr = AM335X_EPWM_0_REGS; |
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47 | return baseAddr; |
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48 | } |
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49 | else if (pwm_id == BBB_PWMSS1) |
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50 | { |
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51 | baseAddr = AM335X_EPWM_1_REGS; |
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52 | return baseAddr; |
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53 | } |
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54 | else if (pwm_id == BBB_PWMSS2) |
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55 | { |
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56 | baseAddr = AM335X_EPWM_2_REGS; |
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57 | return baseAddr; |
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58 | } |
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59 | else |
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60 | { |
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61 | printf("Invalid PWM Id\n"); |
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62 | return 0; |
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63 | } |
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64 | } |
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65 | |
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66 | bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id) |
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67 | { |
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68 | switch(pwm_id) { |
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69 | case BBB_PWMSS2: |
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70 | switch(pin_no) { |
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71 | case BBB_P8_13_2B: |
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72 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(BBB_MUX4); |
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73 | break; |
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74 | case BBB_P8_19_2A: |
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75 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(BBB_MUX4); |
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76 | break; |
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77 | case BBB_P8_45_2A: |
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78 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(BBB_MUX3); |
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79 | break; |
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80 | case BBB_P8_46_2B: |
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81 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(BBB_MUX3); |
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82 | break; |
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83 | default : |
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84 | printf("Invalid pin for module 2\n"); |
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85 | return false; |
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86 | } |
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87 | break; |
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88 | case BBB_PWMSS1: |
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89 | switch(pin_no) { |
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90 | case BBB_P8_34_1B: |
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91 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(BBB_MUX2); |
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92 | break; |
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93 | case BBB_P8_36_1A: |
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94 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(BBB_MUX2); |
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95 | break; |
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96 | case BBB_P9_14_1A: |
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97 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(2)) = BBB_MUXMODE(BBB_MUX6); |
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98 | break; |
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99 | case BBB_P9_16_1B: |
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100 | REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(3)) = BBB_MUXMODE(BBB_MUX6); |
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101 | break; |
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102 | default : |
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103 | printf("Invalid pin for module 1\n"); |
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104 | return false; |
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105 | } |
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106 | break; |
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107 | case BBB_PWMSS0: |
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108 | switch(pin_no) { |
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109 | case BBB_P9_21_0B: |
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110 | REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(BBB_MUX3); |
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111 | break; |
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112 | case BBB_P9_22_0A: |
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113 | REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(BBB_MUX3); |
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114 | break; |
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115 | case BBB_P9_29_0B: |
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116 | REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(BBB_MUX1); |
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117 | break; |
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118 | case BBB_P9_31_0A: |
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119 | REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(BBB_MUX1); |
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120 | break; |
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121 | default: |
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122 | printf("Invalid pin for module 0\n"); |
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123 | return false; |
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124 | } |
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125 | break; |
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126 | |
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127 | default: |
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128 | printf("Invalid PWM sub system\n"); |
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129 | return false; |
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130 | } |
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131 | } |
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132 | |
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133 | /** |
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134 | * @brief This function Enables TBCLK(Time Base Clock) for specific |
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135 | * EPWM instance of pwmsubsystem. |
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136 | * |
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137 | * @param instance It is the instance number of EPWM of pwmsubsystem. |
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138 | * |
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139 | * @return true if successful |
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140 | **/ |
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141 | static bool pwmss_tbclk_enable(unsigned int instance) |
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142 | { |
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143 | uint32_t enable_bit; |
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144 | bool is_valid = true; |
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145 | |
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146 | if (instance == BBB_PWMSS0) |
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147 | { |
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148 | enable_bit = AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN; |
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149 | } |
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150 | else if (instance == BBB_PWMSS1) |
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151 | { |
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152 | enable_bit = AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN; |
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153 | } |
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154 | else if (instance == BBB_PWMSS2) |
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155 | { |
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156 | enable_bit = AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN; |
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157 | } |
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158 | else |
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159 | { |
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160 | is_valid = false; |
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161 | } |
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162 | |
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163 | if (is_valid) |
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164 | { |
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165 | REG(AM335X_PADCONF_BASE + AM335X_PWMSS_CTRL) |= enable_bit; |
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166 | } |
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167 | |
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168 | return is_valid; |
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169 | } |
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170 | |
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171 | /** |
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172 | * @brief This functions enables clock for EHRPWM module in PWMSS subsystem. |
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173 | * |
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174 | * @param pwm_id It is the instance number of EPWM of pwm sub system. |
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175 | * |
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176 | * @return None. |
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177 | * |
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178 | **/ |
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179 | static void epwm_clock_enable(uint32_t pwm_id) |
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180 | { |
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181 | if((pwm_id <3) && (pwm_id >=0)) { |
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182 | uint32_t baseAddr; |
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183 | baseAddr = select_pwmss(pwm_id); |
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184 | REG(baseAddr - AM335X_EPWM_REGS + AM335X_PWMSS_CLKCONFIG) |= AM335X_PWMSS_CLK_EN_ACK; |
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185 | } else { |
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186 | printf("Invalid pwm_id\n"); |
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187 | } |
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188 | } |
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189 | |
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190 | /** |
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191 | * @brief This function configures the L3 and L4_PER system clocks. |
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192 | * It also configures the system clocks for the specified ePWMSS |
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193 | * instance. |
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194 | * |
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195 | * @param pwmss_id The instance number of ePWMSS whose system clocks |
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196 | * have to be configured. |
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197 | * |
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198 | * 'pwmss_id' can take one of the following values: |
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199 | * (0 <= pwmss_id <= 2) |
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200 | * |
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201 | * @return None. |
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202 | * |
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203 | */ |
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204 | static void module_clk_config(uint32_t pwmss_id) |
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205 | { |
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206 | if(pwmss_id == 0) |
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207 | { |
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208 | REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) |= |
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209 | AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE; |
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210 | |
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211 | while(AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE != |
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212 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) & |
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213 | AM335X_CM_PER_EPWMSS0_CLKCTRL_MODULEMODE)); |
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214 | |
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215 | while((AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC << |
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216 | AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT) != |
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217 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL) & |
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218 | AM335X_CM_PER_EPWMSS0_CLKCTRL_IDLEST)); |
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219 | } |
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220 | else if(pwmss_id == 1) |
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221 | { |
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222 | REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) |= |
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223 | AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE; |
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224 | while(AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE != |
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225 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) & |
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226 | AM335X_CM_PER_EPWMSS1_CLKCTRL_MODULEMODE)); |
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227 | |
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228 | while((AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC << |
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229 | AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT) != |
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230 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL) & |
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231 | AM335X_CM_PER_EPWMSS1_CLKCTRL_IDLEST)); |
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232 | } |
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233 | else if(pwmss_id == 2) |
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234 | { |
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235 | REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) |= |
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236 | AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE; |
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237 | while(AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE != |
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238 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) & |
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239 | AM335X_CM_PER_EPWMSS2_CLKCTRL_MODULEMODE)); |
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240 | |
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241 | while((AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC << |
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242 | AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT) != |
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243 | (REG(AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL) & |
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244 | AM335X_CM_PER_EPWMSS2_CLKCTRL_IDLEST)); |
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245 | } |
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246 | else |
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247 | { |
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248 | printf("Please enter valid pwm Id \n"); |
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249 | } |
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250 | } |
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251 | |
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252 | bool beagle_pwm_init(uint32_t pwmss_id) |
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253 | { |
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254 | bool status = true; |
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255 | if((pwmss_id <3) && (pwmss_id >=0)) |
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256 | { |
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257 | module_clk_config(pwmss_id); |
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258 | epwm_clock_enable(pwmss_id); |
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259 | pwmss_tbclk_enable(pwmss_id); |
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260 | return status; |
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261 | } |
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262 | else { |
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263 | status =false; |
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264 | return status; |
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265 | } |
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266 | } |
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267 | |
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268 | int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB) |
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269 | { |
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270 | uint32_t baseAddr; |
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271 | int status = 1; |
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272 | |
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273 | if(pwm_freq <= 0.5) { |
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274 | status =0; |
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275 | return status; |
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276 | } |
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277 | if(dutyA < 0.0f || dutyA > 100.0f || dutyB < 0.0f || dutyB > 100.0f) { |
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278 | status = 0; |
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279 | return status; |
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280 | } |
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281 | dutyA /= 100.0f; |
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282 | dutyB /= 100.0f; |
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283 | |
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284 | /*Compute necessary TBPRD*/ |
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285 | float Cyclens = 0.0f; |
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286 | float Divisor =0; |
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287 | int i,j; |
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288 | const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0}; |
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289 | const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0}; |
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290 | int NearCLKDIV =7; |
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291 | int NearHSPCLKDIV =7; |
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292 | int NearTBPRD =0; |
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293 | |
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294 | /** 10^9 /Hz compute time per cycle (ns) */ |
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295 | Cyclens = 1000000000.0f / pwm_freq; |
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296 | |
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297 | /** am335x provide (128* 14) divider and per TBPRD means 10ns when divider |
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298 | * and max TBPRD is 65535 so max cycle is 128 * 8 * 14 * 65535 * 10ns */ |
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299 | Divisor = (Cyclens / 655350.0f); |
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300 | |
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301 | if(Divisor > (128 * 14)) { |
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302 | printf("Can't generate %f HZ",pwm_freq); |
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303 | return 0; |
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304 | } |
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305 | else { |
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306 | for (i=0;i<8;i++) { |
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307 | for(j=0 ; j<8; j++) { |
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308 | if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV] |
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309 | * HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > Divisor)) { |
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310 | NearCLKDIV = i; |
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311 | NearHSPCLKDIV = j; |
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312 | } |
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313 | } |
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314 | } |
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315 | baseAddr = select_pwmss(pwm_id); |
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316 | REG16(baseAddr + AM335X_EPWM_TBCTL) &= ~(AM335X_TBCTL_CLKDIV_MASK | AM335X_TBCTL_HSPCLKDIV_MASK); |
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317 | |
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318 | REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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319 | (~AM335X_EPWM_TBCTL_CLKDIV)) | ((NearCLKDIV |
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320 | << AM335X_EPWM_TBCTL_CLKDIV_SHIFT) & AM335X_EPWM_TBCTL_CLKDIV); |
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321 | |
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322 | REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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323 | (~AM335X_EPWM_TBCTL_HSPCLKDIV)) | ((NearHSPCLKDIV << |
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324 | AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT) & AM335X_EPWM_TBCTL_HSPCLKDIV); |
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325 | |
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326 | NearTBPRD = (Cyclens / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV])); |
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327 | |
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328 | REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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329 | (~AM335X_EPWM_PRD_LOAD_SHADOW_MASK)) | (((bool)AM335X_EPWM_SHADOW_WRITE_DISABLE << |
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330 | AM335X_EPWM_TBCTL_PRDLD_SHIFT) & AM335X_EPWM_PRD_LOAD_SHADOW_MASK); |
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331 | |
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332 | REG16(baseAddr + AM335X_EPWM_TBCTL) = (REG16(baseAddr + AM335X_EPWM_TBCTL) & |
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333 | (~AM335X_EPWM_COUNTER_MODE_MASK)) | (((unsigned int)AM335X_EPWM_COUNT_UP << |
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334 | AM335X_TBCTL_CTRMODE_SHIFT) & AM335X_EPWM_COUNTER_MODE_MASK); |
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335 | |
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336 | /*setting clock divider and freeze time base*/ |
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337 | REG16(baseAddr + AM335X_EPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * dutyB); |
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338 | REG16(baseAddr + AM335X_EPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * dutyA); |
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339 | REG16(baseAddr + AM335X_EPWM_TBPRD) = (unsigned short)NearTBPRD; |
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340 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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341 | } |
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342 | return status; |
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343 | } |
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344 | |
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345 | bool beagle_ehrpwm_enable(uint32_t pwmid) |
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346 | { |
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347 | bool status = true; |
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348 | uint32_t baseAddr; |
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349 | if((pwmid<3) && (pwmid >=0)) { |
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350 | baseAddr = select_pwmss(pwmid); |
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351 | REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XAHIGH | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT); |
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352 | REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLB_ZRO_XBHIGH | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT); |
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353 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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354 | REG16(baseAddr + AM335X_EPWM_TBCTL) |= AM335X_TBCTL_FREERUN | AM335X_TBCTL_CTRMODE_UP; |
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355 | return status; |
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356 | } |
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357 | else { |
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358 | status =false; |
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359 | return status; |
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360 | } |
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361 | } |
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362 | |
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363 | bool beagle_ehrpwm_disable(uint32_t pwmid) |
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364 | { |
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365 | bool status = true; |
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366 | uint32_t baseAddr; |
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367 | if((pwmid<3) && (pwmid >=0)) { |
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368 | baseAddr = select_pwmss(pwmid); |
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369 | REG16(baseAddr + AM335X_EPWM_TBCTL) = AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE; |
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370 | REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XALOW | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT); |
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371 | REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLA_ZRO_XBLOW | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT); |
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372 | REG16(baseAddr + AM335X_EPWM_TBCNT) = 0; |
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373 | return status; |
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374 | } |
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375 | else { |
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376 | status = false; |
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377 | return status; |
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378 | } |
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379 | } |
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380 | |
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381 | #endif |
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382 | |
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383 | /* For support of BeagleboardxM */ |
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384 | #if IS_DM3730 |
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385 | |
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386 | /* Currently this section is just to satisfy |
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387 | * GPIO API and to make the build successful. |
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388 | * Later on support can be added here. |
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389 | */ |
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390 | uint32_t select_pwmss(uint32_t pwm_id) |
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391 | { |
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392 | return -1; |
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393 | } |
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394 | bool pwmss_tbclk_enable(unsigned int instance) |
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395 | { |
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396 | return false; |
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397 | } |
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398 | bool beagle_pwm_init(uint32_t pwmss_id) |
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399 | { |
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400 | return false; |
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401 | } |
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402 | bool beagle_ehrpwm_disable(uint32_t pwmid) |
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403 | { |
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404 | return false; |
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405 | } |
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406 | bool beagle_ehrpwm_enable(uint32_t pwmid) |
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407 | { |
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408 | return false; |
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409 | } |
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410 | int beagle_pwmss_setting(uint32_t pwm_id, float pwm_freq, float dutyA, float dutyB) |
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411 | { |
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412 | return -1; |
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413 | } |
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414 | bool beagle_epwm_pinmux_setup(uint32_t pin_no, uint32_t pwm_id) |
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415 | { |
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416 | return false; |
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417 | } |
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418 | |
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419 | #endif |
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