[55bde66] | 1 | Pulse Width Modulation subsystem includes EPWM, ECAP , EQEP. There are |
---|
| 2 | different instances available for each one. For PWM there are three |
---|
| 3 | different individual EPWM module 0 , 1 and 2. So wherever pwmss word is |
---|
| 4 | used that affects whole PWM sub system such as EPWM, ECAP and EQEP. This code |
---|
| 5 | has only implementation Non high resolution PWM module. APIs for high |
---|
| 6 | resolution PWM has been yet to develop. |
---|
| 7 | |
---|
| 8 | For Each EPWM instance, has two PWM channels, e.g. EPWM0 has two channel |
---|
| 9 | EPWM0A and EPWM0B. If you configure two PWM outputs(e.g. EPWM0A , EPWM0B) |
---|
| 10 | in the same device, then they *must* be configured with the same frequency. |
---|
| 11 | Changing frequency on one channel (e.g EPWMxA) will automatically change |
---|
| 12 | frequency on another channel(e.g. EPWMxB). However, it is possible to set |
---|
| 13 | different pulse-width/duty cycle to different channel at a time. So always |
---|
| 14 | set the frequency first and then pulse-width/duty cycle. |
---|
| 15 | |
---|
| 16 | For more you can refer : |
---|
| 17 | http://www.ofitselfso.com/BBBCSIO/Source/PWMPortEnum.cs.html |
---|
| 18 | |
---|
| 19 | Pulse Width Modulation uses the system frequency of Beagle Bone Black. |
---|
| 20 | |
---|
| 21 | System frequency = SYSCLKOUT, that is, CPU clock. TBCLK = SYSCLKOUT(By Default) |
---|
| 22 | SYCLKOUT = 100 MHz |
---|
| 23 | |
---|
| 24 | Please visit following link to check why SYSCLKDIV = 100MHz: |
---|
| 25 | https://groups.google.com/forum/#!topic/beagleboard/Ed2J9Txe_E4 |
---|
| 26 | (Refer Technical Reference Manual (TRM) Table 15-41 as well) |
---|
| 27 | |
---|
| 28 | To generate different frequencies with the help of PWM module , SYSCLKOUT |
---|
| 29 | need to be scaled down, which will act as TBCLK and TBCLK will be base clock |
---|
| 30 | for the pwm subsystem. |
---|
| 31 | |
---|
| 32 | TBCLK = SYSCLKOUT/(HSPCLKDIV * CLKDIV) |
---|
| 33 | |
---|
| 34 | |----------------| |
---|
| 35 | | clock | |
---|
| 36 | SYSCLKOUT---> | |---> TBCLK |
---|
| 37 | | prescale | |
---|
| 38 | |----------------| |
---|
| 39 | ^ ^ |
---|
| 40 | | | |
---|
| 41 | TBCTL[CLKDIV]----- ------TBCTL[HSPCLKDIV] |
---|
| 42 | |
---|
| 43 | |
---|
| 44 | CLKDIV and HSPCLKDIV bits are part of the TBCTL register (Refer TRM). |
---|
| 45 | CLKDIV - These bits determine part of the time-base clock prescale value. |
---|
| 46 | Please use the following values of CLKDIV to scale down sysclk respectively. |
---|
| 47 | 0h (R/W) = /1 |
---|
| 48 | 1h (R/W) = /2 |
---|
| 49 | 2h (R/W) = /4 |
---|
| 50 | 3h (R/W) = /8 |
---|
| 51 | 4h (R/W) = /16 |
---|
| 52 | 5h (R/W) = /32 |
---|
| 53 | 6h (R/W) = /64 |
---|
| 54 | 7h (R/W) = /128 |
---|
| 55 | |
---|
| 56 | These bits determine part of the time-base clock prescale value. |
---|
| 57 | Please use following value of HSPCLKDIV to scale down sysclk respectively |
---|
| 58 | 0h (R/W) = /1 |
---|
| 59 | 1h (R/W) = /2 |
---|
| 60 | 2h (R/W) = /4 |
---|
| 61 | 3h (R/W) = /6 |
---|
| 62 | 4h (R/W) = /8 |
---|
| 63 | 5h (R/W) = /10 |
---|
| 64 | 6h (R/W) = /12 |
---|
| 65 | 7h (R/W) = /14 |
---|
| 66 | |
---|
| 67 | For example, if you set CLKDIV = 3h and HSPCLKDIV= 2h Then |
---|
| 68 | SYSCLKOUT will be divided by (1/8)(1/4). It means SYSCLKOUT/32 |
---|
| 69 | |
---|
| 70 | How to generate frequency ? |
---|
| 71 | |
---|
| 72 | freq = 1/Period |
---|
| 73 | |
---|
| 74 | TBPRD register is responsible to generate the frequency. These bits determine |
---|
| 75 | the period of the time-base counter. |
---|
| 76 | |
---|
| 77 | By default TBCLK = SYSCLKOUT = 100 MHz |
---|
| 78 | |
---|
| 79 | Here by default period is 1/100MHz = 10 nsec |
---|
| 80 | |
---|
| 81 | Following example shows value to be loaded into TBPRD |
---|
| 82 | |
---|
| 83 | e.g. TBPRD = 1 = 1 count |
---|
| 84 | count x Period = 1 x 1ns = 1ns |
---|
| 85 | freq = 1/Period = 1 / 1ns = 100 MHz |
---|
| 86 | |
---|
| 87 | For duty cycle CMPA and CMPB are the responsible registers. |
---|
| 88 | |
---|
| 89 | To generate single with 50% Duty cycle & 100MHz freq. |
---|
| 90 | |
---|
| 91 | CMPA = count x Duty Cycle |
---|
| 92 | = TBPRD x Duty Cycle |
---|
| 93 | = 1 x 50/100 |
---|
| 94 | = 0.2 |
---|
| 95 | |
---|
| 96 | The value in the active CMPA register is continuously compared to |
---|
| 97 | the time-base counter (TBCNT). When the values are equal, the |
---|
| 98 | counter-compare module generates a "time-base counter equal to |
---|
| 99 | counter compare A" event. This event is sent to the action-qualifier |
---|
| 100 | where it is qualified and converted it into one or more actions. |
---|
| 101 | These actions can be applied to either the EPWMxA or the |
---|
| 102 | EPWMxB output depending on the configuration of the AQCTLA and |
---|
| 103 | AQCTLB registers. |
---|
| 104 | |
---|
| 105 | List of pins for that can be used for different PWM instance : |
---|
| 106 | |
---|
| 107 | ------------------------------------------------ |
---|
| 108 | | EPWM2 | EPWM1 | EPWM0 | |
---|
| 109 | ------------------------------------------------ |
---|
| 110 | | BBB_P8_13_2B | BBB_P8_34_1B | BBB_P9_21_0B | |
---|
| 111 | | BBB_P8_19_2A | BBB_P8_36_1A | BBB_P9_22_0A | |
---|
| 112 | | BBB_P8_45_2A | BBB_P9_14_1A | BBB_P9_29_0B | |
---|
| 113 | | BBB_P8_46_2B | BBB_P9_16_1B | BBB_P9_31_0A | |
---|
| 114 | ------------------------------------------------ |
---|
| 115 | BBB_P8_13_2B represents P8 Header , pin number 13 , 2nd PWM instance and B channel. |
---|
| 116 | |
---|
| 117 | Following sample program can be used to generate 7 Hz frequency. |
---|
| 118 | |
---|
| 119 | #ifdef HAVE_CONFIG_H |
---|
| 120 | #include "config.h" |
---|
| 121 | #endif |
---|
| 122 | |
---|
| 123 | #include <rtems/test.h> |
---|
| 124 | #include <bsp.h> |
---|
| 125 | #include <bsp/gpio.h> |
---|
| 126 | #include <stdio.h> |
---|
| 127 | #include <stdlib.h> |
---|
| 128 | #include <bsp/bbb-pwm.h> |
---|
| 129 | |
---|
| 130 | const char rtems_test_name[] = "Testing PWM driver"; |
---|
| 131 | rtems_printer rtems_test_printer; |
---|
| 132 | |
---|
| 133 | static void inline delay_sec(int sec) |
---|
| 134 | { |
---|
| 135 | rtems_task_wake_after(sec*rtems_clock_get_ticks_per_second()); |
---|
| 136 | } |
---|
| 137 | |
---|
| 138 | rtems_task Init(rtems_task_argument argument); |
---|
| 139 | |
---|
| 140 | rtems_task Init( |
---|
| 141 | rtems_task_argument ignored |
---|
| 142 | ) |
---|
| 143 | { |
---|
| 144 | rtems_test_begin(); |
---|
| 145 | printf("Starting PWM Testing"); |
---|
| 146 | |
---|
| 147 | /*Initialize GPIO pins in BBB*/ |
---|
| 148 | rtems_gpio_initialize(); |
---|
| 149 | |
---|
| 150 | /* Set P9 Header , 21 Pin number , PWM B channel and 0 PWM instance to generate frequency*/ |
---|
| 151 | beagle_epwm_pinmux_setup(BBB_P9_21_0B,BBB_PWMSS0); |
---|
| 152 | |
---|
| 153 | /** Initialize clock for PWM sub system |
---|
| 154 | * Turn on time base clock for PWM o instance |
---|
| 155 | */ |
---|
| 156 | beagle_pwm_init(BBB_PWMSS0); |
---|
| 157 | |
---|
| 158 | float PWM_HZ = 7.0f ; /* 7 Hz */ |
---|
| 159 | float duty_A = 20.0f ; /* 20% Duty cycle for PWM 0_A output */ |
---|
| 160 | const float duty_B = 50.0f ; /* 50% Duty cycle for PWM 0_B output*/ |
---|
| 161 | |
---|
| 162 | /*Note: Always check whether pwmss clocks are enabled or not before configuring PWM*/ |
---|
| 163 | bool is_running = beagle_pwmss_is_running(BBB_PWMSS2); |
---|
| 164 | |
---|
| 165 | if(is_running) { |
---|
| 166 | |
---|
| 167 | /*To analyse the two different duty cycle Output should be observed at P8_45 and P8_46 pin number */ |
---|
| 168 | beagle_pwm_configure(BBB_PWMSS0, PWM_HZ ,duty_A , duty_B); |
---|
| 169 | printf("PWM enable for 10s ....\n"); |
---|
| 170 | |
---|
| 171 | /*Set Up counter and enable pwm module */ |
---|
| 172 | beagle_pwm_enable(BBB_PWMSS0); |
---|
| 173 | delay_sec(10); |
---|
| 174 | |
---|
| 175 | /*freeze the counter and disable pwm module*/ |
---|
| 176 | beagle_epwm_disable(BBB_PWMSS0); |
---|
| 177 | } |
---|
| 178 | } |
---|
| 179 | |
---|
| 180 | /* NOTICE: the clock driver is enabled */ |
---|
| 181 | #define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER |
---|
| 182 | #define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER |
---|
| 183 | |
---|
| 184 | #define CONFIGURE_MAXIMUM_TASKS 1 |
---|
| 185 | #define CONFIGURE_USE_DEVFS_AS_BASE_FILESYSTEM |
---|
| 186 | |
---|
| 187 | #define CONFIGURE_MAXIMUM_SEMAPHORES 1 |
---|
| 188 | |
---|
| 189 | #define CONFIGURE_RTEMS_INIT_TASKS_TABLE |
---|
| 190 | |
---|
| 191 | #define CONFIGURE_EXTRA_TASK_STACKS (2 * RTEMS_MINIMUM_STACK_SIZE) |
---|
| 192 | |
---|
| 193 | #define CONFIGURE_INITIAL_EXTENSIONS RTEMS_TEST_INITIAL_EXTENSION |
---|
| 194 | |
---|
| 195 | #define CONFIGURE_INIT |
---|
| 196 | #include <rtems/confdefs.h> |
---|
| 197 | |
---|