1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup bsp_interrupt |
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5 | * @ingroup arm_beagle |
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6 | * |
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7 | * @brief Interrupt support. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2014 Ben Gras <beng@shrike-systems.com>. All rights reserved. |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <bsp.h> |
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19 | #include <bsp/irq-generic.h> |
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20 | #include <bsp/linker-symbols.h> |
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21 | #include <bsp/fatal.h> |
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22 | |
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23 | #include <rtems/score/armv4.h> |
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24 | |
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25 | #include <libcpu/arm-cp15.h> |
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26 | |
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27 | struct omap_intr |
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28 | { |
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29 | uint32_t base; |
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30 | int size; |
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31 | }; |
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32 | |
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33 | #if IS_DM3730 |
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34 | static struct omap_intr omap_intr = { |
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35 | .base = OMAP3_DM37XX_INTR_BASE, |
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36 | .size = 0x1000, |
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37 | }; |
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38 | #endif |
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39 | |
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40 | #if IS_AM335X |
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41 | static struct omap_intr omap_intr = { |
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42 | .base = OMAP3_AM335X_INTR_BASE, |
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43 | .size = 0x1000, |
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44 | }; |
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45 | #endif |
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46 | |
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47 | /* Enables interrupts at the Interrupt Controller side. */ |
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48 | static inline void omap_irq_ack(void) |
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49 | { |
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50 | mmio_write(omap_intr.base + OMAP3_INTCPS_CONTROL, OMAP3_INTR_NEWIRQAGR); |
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51 | |
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52 | /* Flush data cache to make sure all the previous writes are done |
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53 | before re-enabling interrupts. */ |
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54 | flush_data_cache(); |
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55 | } |
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56 | |
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57 | void bsp_interrupt_dispatch(void) |
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58 | { |
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59 | const uint32_t reg = mmio_read(omap_intr.base + OMAP3_INTCPS_SIR_IRQ); |
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60 | |
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61 | if ((reg & OMAP3_INTR_SPURIOUSIRQ_MASK) != OMAP3_INTR_SPURIOUSIRQ_MASK) { |
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62 | const rtems_vector_number irq = reg & OMAP3_INTR_ACTIVEIRQ_MASK; |
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63 | |
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64 | bsp_interrupt_handler_dispatch(irq); |
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65 | } else { |
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66 | /* Ignore spurious interrupts. We'll still ACK it so new interrupts |
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67 | can be generated. */ |
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68 | } |
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69 | |
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70 | omap_irq_ack(); |
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71 | } |
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72 | |
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73 | /* There are 4 32-bit interrupt mask registers for a total of 128 interrupts. |
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74 | The IRQ number tells us which register to use. */ |
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75 | static uint32_t omap_get_mir_reg(rtems_vector_number vector, uint32_t *const mask) |
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76 | { |
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77 | uint32_t mir_reg; |
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78 | |
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79 | /* Select which bit to set/clear in the MIR register. */ |
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80 | *mask = 1ul << (vector % 32u); |
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81 | |
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82 | if (vector < 32u) { |
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83 | mir_reg = OMAP3_INTCPS_MIR0; |
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84 | } else if (vector < 64u) { |
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85 | mir_reg = OMAP3_INTCPS_MIR1; |
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86 | } else if (vector < 96u) { |
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87 | mir_reg = OMAP3_INTCPS_MIR2; |
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88 | } else if (vector < 128u) { |
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89 | mir_reg = OMAP3_INTCPS_MIR3; |
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90 | } else { |
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91 | /* Invalid IRQ number. This should never happen. */ |
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92 | bsp_fatal(0); |
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93 | } |
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94 | |
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95 | return mir_reg; |
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96 | } |
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97 | |
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98 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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99 | { |
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100 | uint32_t mask, cur; |
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101 | uint32_t mir_reg = omap_get_mir_reg(vector, &mask); |
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102 | |
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103 | cur = mmio_read(omap_intr.base + mir_reg); |
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104 | mmio_write(omap_intr.base + mir_reg, cur & ~mask); |
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105 | flush_data_cache(); |
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106 | |
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107 | return RTEMS_SUCCESSFUL; |
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108 | } |
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109 | |
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110 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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111 | { |
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112 | uint32_t mask, cur; |
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113 | uint32_t mir_reg = omap_get_mir_reg(vector, &mask); |
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114 | |
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115 | cur = mmio_read(omap_intr.base + mir_reg); |
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116 | mmio_write(omap_intr.base + mir_reg, cur | mask); |
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117 | flush_data_cache(); |
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118 | |
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119 | return RTEMS_SUCCESSFUL; |
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120 | } |
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121 | |
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122 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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123 | { |
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124 | int i; |
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125 | uint32_t intc_ilrx; |
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126 | |
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127 | /* AM335X TRM 6.2.1 Initialization Sequence */ |
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128 | mmio_write(omap_intr.base + OMAP3_INTCPS_SYSCONFIG, OMAP3_SYSCONFIG_AUTOIDLE); |
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129 | mmio_write(omap_intr.base + OMAP3_INTCPS_IDLE, 0); |
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130 | /* priority 0 to all IRQs */ |
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131 | for(intc_ilrx = 0x100; intc_ilrx <= 0x2fc; intc_ilrx += 4) { |
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132 | mmio_write(omap_intr.base + intc_ilrx, 0); |
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133 | } |
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134 | |
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135 | /* Mask all interrupts */ |
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136 | for(i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; i++) |
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137 | bsp_interrupt_vector_disable(i); |
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138 | |
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139 | /* Install generic interrupt handler */ |
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140 | arm_cp15_set_exception_handler(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt); |
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141 | arm_cp15_set_vector_base_address(bsp_vector_table_begin); |
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142 | |
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143 | return RTEMS_SUCCESSFUL; |
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144 | } |
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