1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup arm_beagle |
---|
5 | * |
---|
6 | * @brief I2C support API. |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (c) 2012 Claas Ziemke. All rights reserved. |
---|
11 | * |
---|
12 | * Claas Ziemke |
---|
13 | * Kernerstrasse 11 |
---|
14 | * 70182 Stuttgart |
---|
15 | * Germany |
---|
16 | * <claas.ziemke@gmx.net> |
---|
17 | * |
---|
18 | * The license and distribution terms for this file may be |
---|
19 | * found in the file LICENSE in this distribution or at |
---|
20 | * http://www.rtems.com/license/LICENSE. |
---|
21 | */ |
---|
22 | |
---|
23 | #ifndef LIBBSP_ARM_BEAGLE_I2C_H |
---|
24 | #define LIBBSP_ARM_BEAGLE_I2C_H |
---|
25 | |
---|
26 | #include <rtems.h> |
---|
27 | |
---|
28 | #include <bsp.h> |
---|
29 | |
---|
30 | #ifdef __cplusplus |
---|
31 | extern "C" { |
---|
32 | #endif /* __cplusplus */ |
---|
33 | |
---|
34 | |
---|
35 | /* I2C Configuration Register (I2C_CON): */ |
---|
36 | |
---|
37 | #define I2C_CON_EN (1 << 15) /* I2C module enable */ |
---|
38 | #define I2C_CON_BE (1 << 14) /* Big endian mode */ |
---|
39 | #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ |
---|
40 | #define I2C_CON_MST (1 << 10) /* Master/slave mode */ |
---|
41 | #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ |
---|
42 | /* (master mode only) */ |
---|
43 | #define I2C_CON_XA (1 << 8) /* Expand address */ |
---|
44 | #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ |
---|
45 | #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ |
---|
46 | |
---|
47 | /* I2C Status Register (I2C_STAT): */ |
---|
48 | |
---|
49 | #define I2C_STAT_SBD (1 << 15) /* Single byte data */ |
---|
50 | #define I2C_STAT_BB (1 << 12) /* Bus busy */ |
---|
51 | #define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
---|
52 | #define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
---|
53 | #define I2C_STAT_AAS (1 << 9) /* Address as slave */ |
---|
54 | #define I2C_STAT_GC (1 << 5) |
---|
55 | #define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ |
---|
56 | #define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ |
---|
57 | #define I2C_STAT_ARDY (1 << 2) /* Register access ready */ |
---|
58 | #define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ |
---|
59 | #define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ |
---|
60 | |
---|
61 | /* I2C Interrupt Enable Register (I2C_IE): */ |
---|
62 | #define I2C_IE_GC_IE (1 << 5) |
---|
63 | #define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ |
---|
64 | #define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ |
---|
65 | #define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ |
---|
66 | #define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ |
---|
67 | #define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ |
---|
68 | /* |
---|
69 | * The equation for the low and high time is |
---|
70 | * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed |
---|
71 | * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed |
---|
72 | * |
---|
73 | * If the duty cycle is 50% |
---|
74 | * |
---|
75 | * tlow = scll + scll_trim = sampling clock / (2 * speed) |
---|
76 | * thigh = sclh + sclh_trim = sampling clock / (2 * speed) |
---|
77 | * |
---|
78 | * In TRM |
---|
79 | * scll_trim = 7 |
---|
80 | * sclh_trim = 5 |
---|
81 | * |
---|
82 | * The linux 2.6.30 kernel uses |
---|
83 | * scll_trim = 6 |
---|
84 | * sclh_trim = 6 |
---|
85 | * |
---|
86 | * These are the trim values for standard and fast speed |
---|
87 | */ |
---|
88 | #ifndef I2C_FASTSPEED_SCLL_TRIM |
---|
89 | #define I2C_FASTSPEED_SCLL_TRIM 6 |
---|
90 | #endif |
---|
91 | #ifndef I2C_FASTSPEED_SCLH_TRIM |
---|
92 | #define I2C_FASTSPEED_SCLH_TRIM 6 |
---|
93 | #endif |
---|
94 | |
---|
95 | /* These are the trim values for high speed */ |
---|
96 | #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM |
---|
97 | #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM |
---|
98 | #endif |
---|
99 | #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM |
---|
100 | #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM |
---|
101 | #endif |
---|
102 | #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM |
---|
103 | #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM |
---|
104 | #endif |
---|
105 | #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM |
---|
106 | #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM |
---|
107 | #endif |
---|
108 | |
---|
109 | #define OMAP_I2C_STANDARD 100000 |
---|
110 | #define OMAP_I2C_FAST_MODE 400000 |
---|
111 | #define OMAP_I2C_HIGH_SPEED 3400000 |
---|
112 | |
---|
113 | |
---|
114 | /* Use the reference value of 96MHz if not explicitly set by the board */ |
---|
115 | #ifndef I2C_IP_CLK |
---|
116 | #define I2C_IP_CLK SYSTEM_CLOCK_96 |
---|
117 | #endif |
---|
118 | |
---|
119 | /* |
---|
120 | * The reference minimum clock for high speed is 19.2MHz. |
---|
121 | * The linux 2.6.30 kernel uses this value. |
---|
122 | * The reference minimum clock for fast mode is 9.6MHz |
---|
123 | * The reference minimum clock for standard mode is 4MHz |
---|
124 | * In TRM, the value of 12MHz is used. |
---|
125 | */ |
---|
126 | #ifndef I2C_INTERNAL_SAMPLING_CLK |
---|
127 | #define I2C_INTERNAL_SAMPLING_CLK 19200000 |
---|
128 | #endif |
---|
129 | |
---|
130 | #define I2C_PSC_MAX 0x0f |
---|
131 | #define I2C_PSC_MIN 0x00 |
---|
132 | |
---|
133 | |
---|
134 | #define DISP_LINE_LEN 128 |
---|
135 | #define I2C_TIMEOUT 1000 |
---|
136 | |
---|
137 | #define I2C_BUS_MAX 3 |
---|
138 | |
---|
139 | #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x070000) |
---|
140 | |
---|
141 | #define I2C_DEFAULT_BASE I2C_BASE1 |
---|
142 | |
---|
143 | #define I2C_SYSS_RDONE (1 << 0) /* Internel reset monitoring */ |
---|
144 | |
---|
145 | #define CONFIG_SYS_I2C_SPEED 100000 |
---|
146 | #define CONFIG_SYS_I2C_SLAVE 1 |
---|
147 | |
---|
148 | struct i2c { |
---|
149 | unsigned short rev; /* 0x00 */ |
---|
150 | unsigned short res1; |
---|
151 | unsigned short ie; /* 0x04 */ |
---|
152 | unsigned short res2; |
---|
153 | unsigned short stat; /* 0x08 */ |
---|
154 | unsigned short res3; |
---|
155 | unsigned short iv; /* 0x0C */ |
---|
156 | unsigned short res4; |
---|
157 | unsigned short syss; /* 0x10 */ |
---|
158 | unsigned short res4a; |
---|
159 | unsigned short buf; /* 0x14 */ |
---|
160 | unsigned short res5; |
---|
161 | unsigned short cnt; /* 0x18 */ |
---|
162 | unsigned short res6; |
---|
163 | unsigned short data; /* 0x1C */ |
---|
164 | unsigned short res7; |
---|
165 | unsigned short sysc; /* 0x20 */ |
---|
166 | unsigned short res8; |
---|
167 | unsigned short con; /* 0x24 */ |
---|
168 | unsigned short res9; |
---|
169 | unsigned short oa; /* 0x28 */ |
---|
170 | unsigned short res10; |
---|
171 | unsigned short sa; /* 0x2C */ |
---|
172 | unsigned short res11; |
---|
173 | unsigned short psc; /* 0x30 */ |
---|
174 | unsigned short res12; |
---|
175 | unsigned short scll; /* 0x34 */ |
---|
176 | unsigned short res13; |
---|
177 | unsigned short sclh; /* 0x38 */ |
---|
178 | unsigned short res14; |
---|
179 | unsigned short systest; /* 0x3c */ |
---|
180 | unsigned short res15; |
---|
181 | }; |
---|
182 | |
---|
183 | static unsigned short wait_for_pin( void ); |
---|
184 | |
---|
185 | static void wait_for_bb( void ); |
---|
186 | |
---|
187 | static void flush_fifo( void ); |
---|
188 | |
---|
189 | void i2c_init( int speed, int slaveadd ); |
---|
190 | |
---|
191 | static int i2c_read_byte( |
---|
192 | unsigned char devaddr, |
---|
193 | unsigned char regoffset, |
---|
194 | unsigned char *value |
---|
195 | ); |
---|
196 | |
---|
197 | int i2c_write( |
---|
198 | unsigned char chip, |
---|
199 | unsigned int addr, |
---|
200 | int alen, |
---|
201 | unsigned char *buffer, |
---|
202 | int len |
---|
203 | ); |
---|
204 | |
---|
205 | int i2c_read( |
---|
206 | unsigned char chip, |
---|
207 | uint addr, |
---|
208 | int alen, |
---|
209 | unsigned char *buffer, |
---|
210 | int len |
---|
211 | ); |
---|
212 | |
---|
213 | static int imw ( unsigned char chip, unsigned long addr, unsigned char byte ); |
---|
214 | |
---|
215 | static int imd( unsigned char chip, unsigned int addr, unsigned int length ); |
---|
216 | |
---|
217 | /** |
---|
218 | * @brief Initializes the I2C module @a i2c. |
---|
219 | * |
---|
220 | * Valid @a clock_in_hz values are 100000 and 400000. |
---|
221 | * |
---|
222 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
223 | * @retval RTEMS_INVALID_ID Invalid @a i2c value. |
---|
224 | * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. |
---|
225 | */ |
---|
226 | rtems_status_code beagle_i2c_init( |
---|
227 | volatile beagle_i2c *i2c, |
---|
228 | unsigned clock_in_hz |
---|
229 | ); |
---|
230 | |
---|
231 | /** |
---|
232 | * @brief Resets the I2C module @a i2c. |
---|
233 | */ |
---|
234 | void beagle_i2c_reset(volatile beagle_i2c *i2c); |
---|
235 | |
---|
236 | /** |
---|
237 | * @brief Sets the I2C module @a i2c clock. |
---|
238 | * |
---|
239 | * Valid @a clock_in_hz values are 100000 and 400000. |
---|
240 | * |
---|
241 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
242 | * @retval RTEMS_INVALID_CLOCK Invalid @a clock_in_hz value. |
---|
243 | */ |
---|
244 | rtems_status_code beagle_i2c_clock( |
---|
245 | volatile beagle_i2c *i2c, |
---|
246 | unsigned clock_in_hz |
---|
247 | ); |
---|
248 | |
---|
249 | /** |
---|
250 | * @brief Starts a write transaction on the I2C module @a i2c. |
---|
251 | * |
---|
252 | * The address parameter @a addr must not contain the read/write bit. |
---|
253 | * |
---|
254 | * The error status may be delayed to the next |
---|
255 | * beagle_i2c_write_with_optional_stop() due to controller flaws. |
---|
256 | * |
---|
257 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
258 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
259 | */ |
---|
260 | rtems_status_code beagle_i2c_write_start( |
---|
261 | volatile beagle_i2c *i2c, |
---|
262 | unsigned addr |
---|
263 | ); |
---|
264 | |
---|
265 | /** |
---|
266 | * @brief Writes data via the I2C module @a i2c with optional stop. |
---|
267 | * |
---|
268 | * The error status may be delayed to the next |
---|
269 | * beagle_i2c_write_with_optional_stop() due to controller flaws. |
---|
270 | * |
---|
271 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
272 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
273 | */ |
---|
274 | rtems_status_code beagle_i2c_write_with_optional_stop( |
---|
275 | volatile beagle_i2c *i2c, |
---|
276 | const uint8_t *out, |
---|
277 | size_t n, |
---|
278 | bool stop |
---|
279 | ); |
---|
280 | |
---|
281 | /** |
---|
282 | * @brief Starts a read transaction on the I2C module @a i2c. |
---|
283 | * |
---|
284 | * The address parameter @a addr must not contain the read/write bit. |
---|
285 | * |
---|
286 | * The error status may be delayed to the next |
---|
287 | * beagle_i2c_read_with_optional_stop() due to controller flaws. |
---|
288 | * |
---|
289 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
290 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
291 | */ |
---|
292 | rtems_status_code beagle_i2c_read_start( |
---|
293 | volatile beagle_i2c *i2c, |
---|
294 | unsigned addr |
---|
295 | ); |
---|
296 | |
---|
297 | /** |
---|
298 | * @brief Reads data via the I2C module @a i2c with optional stop. |
---|
299 | * |
---|
300 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
301 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
302 | * @retval RTEMS_NOT_IMPLEMENTED Stop is @a false. |
---|
303 | */ |
---|
304 | rtems_status_code beagle_i2c_read_with_optional_stop( |
---|
305 | volatile beagle_i2c *i2c, |
---|
306 | uint8_t *in, |
---|
307 | size_t n, |
---|
308 | bool stop |
---|
309 | ); |
---|
310 | |
---|
311 | /** |
---|
312 | * @brief Writes and reads data via the I2C module @a i2c. |
---|
313 | * |
---|
314 | * This will be one bus transaction. |
---|
315 | * |
---|
316 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
317 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
318 | */ |
---|
319 | rtems_status_code beagle_i2c_write_and_read( |
---|
320 | volatile beagle_i2c *i2c, |
---|
321 | unsigned addr, |
---|
322 | const uint8_t *out, |
---|
323 | size_t out_size, |
---|
324 | uint8_t *in, |
---|
325 | size_t in_size |
---|
326 | ); |
---|
327 | |
---|
328 | /** |
---|
329 | * @brief Writes data via the I2C module @a i2c. |
---|
330 | * |
---|
331 | * This will be one bus transaction. |
---|
332 | * |
---|
333 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
334 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
335 | */ |
---|
336 | static inline rtems_status_code beagle_i2c_write( |
---|
337 | volatile beagle_i2c *i2c, |
---|
338 | unsigned addr, |
---|
339 | const uint8_t *out, |
---|
340 | size_t out_size |
---|
341 | ) |
---|
342 | { |
---|
343 | return beagle_i2c_write_and_read(i2c, addr, out, out_size, NULL, 0); |
---|
344 | } |
---|
345 | |
---|
346 | /** |
---|
347 | * @brief Reads data via the I2C module @a i2c. |
---|
348 | * |
---|
349 | * This will be one bus transaction. |
---|
350 | * |
---|
351 | * @retval RTEMS_SUCCESSFUL Successful operation. |
---|
352 | * @retval RTEMS_IO_ERROR Received a NACK from the slave. |
---|
353 | */ |
---|
354 | static inline rtems_status_code beagle_i2c_read( |
---|
355 | volatile beagle_i2c *i2c, |
---|
356 | unsigned addr, |
---|
357 | uint8_t *in, |
---|
358 | size_t in_size |
---|
359 | ) |
---|
360 | { |
---|
361 | return beagle_i2c_write_and_read(i2c, addr, NULL, 0, in, in_size); |
---|
362 | } |
---|
363 | |
---|
364 | #ifdef __cplusplus |
---|
365 | } |
---|
366 | #endif /* __cplusplus */ |
---|
367 | |
---|
368 | #endif /* LIBBSP_ARM_BEAGLE_I2C_H */ |
---|