source: rtems/c/src/lib/libbsp/arm/beagle/include/beagle.h @ 7a66986

4.115
Last change on this file since 7a66986 was 7a66986, checked in by Claas Ziemke <ziemke@…>, on 08/22/12 at 12:39:02

Added BeagleBoard? BSP

Coding done in course of GSoC2012.

Commit edited to be brought up-to-date with mainline by
Ben Gras <beng@…>.

  • Property mode set to 100644
File size: 22.8 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup beagle_reg
5 *
6 * @brief Register base addresses.
7 */
8
9/*
10 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
11 *
12 *  Claas Ziemke
13 *  Kernerstrasse 11
14 *  70182 Stuttgart
15 *  Germany
16 *  <claas.ziemke@gmx.net>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_BEAGLE_BEAGLE_H
24#define LIBBSP_ARM_BEAGLE_BEAGLE_H
25
26#include <stdint.h>
27
28#include <bsp/beagle-timer.h>
29
30#define __arch_getb(a)      (*(volatile unsigned char *)(a))
31#define __arch_getw(a)      (*(volatile unsigned short *)(a))
32#define __arch_getl(a)      (*(volatile unsigned int *)(a))
33
34#define __arch_putb(v,a)    (*(volatile unsigned char *)(a) = (v))
35#define __arch_putw(v,a)    (*(volatile unsigned short *)(a) = (v))
36#define __arch_putl(v,a)    (*(volatile unsigned int *)(a) = (v))
37/*
38 * TODO: do we need a barrier here?
39 */
40
41#define writeb(v,c) ({ unsigned char  __v = v; __arch_putb(__v,c); __v; })
42#define writew(v,c) ({ unsigned short __v = v; __arch_putw(__v,c); __v; })
43#define writel(v,c) ({ unsigned int __v = v; __arch_putl(__v,c); __v; })
44
45#define readb(c)  ({ unsigned char  __v = __arch_getb(c); __v; })
46#define readw(c)  ({ unsigned short __v = __arch_getw(c); __v; })
47#define readl(c)  ({ unsigned int __v = __arch_getl(c); __v; })
48
49#define SYSTEM_CLOCK_12       12000000
50#define SYSTEM_CLOCK_13       13000000
51#define SYSTEM_CLOCK_192      19200000
52#define SYSTEM_CLOCK_96       96000000
53
54#define OMAP34XX_CORE_L4_IO_BASE  0x48000000
55
56#define BEAGLE_BASE_UART_1 0x4806A000
57#define BEAGLE_BASE_UART_2 0x4806C000
58#define BEAGLE_BASE_UART_3 0x49020000
59#define BEAGLE_BASE_UART_4 0x49020000
60#define BEAGLE_BASE_UART_5 0x49020000
61#define BEAGLE_BASE_UART_5 0x49020000
62#define BEAGLE_BASE_UART_6 0x49020000
63#define BEAGLE_BASE_UART_7 0x49020000
64
65#define BEAGLE_UART_DLL_REG_OFFSET 0x000
66#define BEAGLE_UART_RHR_REG_OFFSET 0x000
67#define BEAGLE_UART_THR_REG_OFFSET 0x000
68#define BEAGLE_UART_DLH_REG_OFFSET 0x004
69#define BEAGLE_UART_IER_REG_OFFSET 0x004
70#define BEAGLE_UART_IIR_REG_OFFSET 0x008
71#define BEAGLE_UART_FCR_REG_OFFSET 0x008
72#define BEAGLE_UART_EFR_REG_OFFSET 0x008
73#define BEAGLE_UART_LCR_REG_OFFSET 0x00C
74#define BEAGLE_UART_MCR_REG_OFFSET 0x010
75#define BEAGLE_UART_XON1_ADDR1_REG_OFFSET 0x010
76#define BEAGLE_UART_LSR_REG_OFFSET 0x014
77#define BEAGLE_UART_XON2_ADDR2_REG_OFFSET 0x014
78#define BEAGLE_UART_MSR_REG_OFFSET 0x018
79#define BEAGLE_UART_TCR_REG_OFFSET 0x018
80#define BEAGLE_UART_XOFF1_REG_OFFSET 0x018
81#define BEAGLE_UART_SPR_REG_OFFSET 0x01C
82#define BEAGLE_UART_TLR_REG_OFFSET 0x01C
83#define BEAGLE_UART_XOFF2_REG_OFFSET 0x01C
84#define BEAGLE_UART_MDR1_REG_OFFSET 0x020
85#define BEAGLE_UART_MDR2_REG_OFFSET 0x024
86#define BEAGLE_UART_SFLSR_REG_OFFSET 0x028
87#define BEAGLE_UART_TXFLL_REG_OFFSET 0x028
88#define BEAGLE_UART_RESUME_REG_OFFSET 0x02C
89#define BEAGLE_UART_TXFLH_REG_OFFSET 0x02C
90#define BEAGLE_UART_SFREGL_REG_OFFSET 0x030
91#define BEAGLE_UART_RXFLL_REG_OFFSET 0x030
92#define BEAGLE_UART_SFREGH_REG_OFFSET 0x034
93#define BEAGLE_UART_RXFLH_REG_OFFSET 0x034
94#define BEAGLE_UART_UASR_REG_OFFSET 0x038
95#define BEAGLE_UART_BLR_REG_OFFSET 0x038
96#define BEAGLE_UART_ACREG_REG_OFFSET 0x03C
97#define BEAGLE_UART_SCR_REG_OFFSET 0x040
98#define BEAGLE_UART_SSR_REG_OFFSET 0x044
99#define BEAGLE_UART_EBLR_REG_OFFSET 0x048
100#define BEAGLE_UART_MVR_REG_OFFSET 0x050
101#define BEAGLE_UART_SYSC_REG_OFFSET 0x054
102#define BEAGLE_UART_SYSS_REG_OFFSET 0x058
103#define BEAGLE_UART_WER_REG_OFFSET 0x05C
104#define BEAGLE_UART_CFPS_REG_OFFSET 0x060
105
106#define BEAGLE_UART5_DLL = BAGLE_BASE_UART5 + BEAGLE_UART_DLL_REG_OFFSET
107#define BEAGLE_UART5_RHR = BAGLE_BASE_UART5 + \
108  BEAGLE_UART_BEAGLE_UART_RHR_REG_OFFSET
109#define BEAGLE_UART5_THR = BAGLE_BASE_UART5 + BEAGLE_UART_THR_REG_OFFSET
110#define BEAGLE_UART5_DLH = BAGLE_BASE_UART5 + BEAGLE_UART_DLH_REG_OFFSET
111#define BEAGLE_UART5_IER = BAGLE_BASE_UART5 + BEAGLE_UART_IER_REG_OFFSET
112#define BEAGLE_UART5_IIR = BAGLE_BASE_UART5 + BEAGLE_UART_IIR_REG_OFFSET
113#define BEAGLE_UART5_FCR = BAGLE_BASE_UART5 + BEAGLE_UART_FCR_REG_OFFSET
114#define BEAGLE_UART5_EFR = BAGLE_BASE_UART5 + BEAGLE_UART_EFR_REG_OFFSET
115#define BEAGLE_UART5_LCR = BAGLE_BASE_UART5 + BEAGLE_UART_LCR_REG_OFFSET
116#define BEAGLE_UART5_MCR = BAGLE_BASE_UART5 + BEAGLE_UART_MCR_REG_OFFSET
117#define BEAGLE_UART5_XON1_ADDR1 = BAGLE_BASE_UART5 + \
118  BEAGLE_UART_XON1_ADDR1_REG_OFFSET
119#define BEAGLE_UART5_LSR = BAGLE_BASE_UART5 + BEAGLE_UART_LSR_REG_OFFSET
120#define BEAGLE_UART5_XON2_ADDR2 = BAGLE_BASE_UART5 + \
121  BEAGLE_UART_XON2_ADDR2_REG_OFFSET
122#define BEAGLE_UART5_MSR = BAGLE_BASE_UART5 + BEAGLE_UART_MSR_REG_OFFSET
123#define BEAGLE_UART5_TCR = BAGLE_BASE_UART5 + BEAGLE_UART_TCR_REG_OFFSET
124#define BEAGLE_UART5_XOFF1 = BAGLE_BASE_UART5 + BEAGLE_UART_XOFF1_REG_OFFSET
125#define BEAGLE_UART5_SPR = BAGLE_BASE_UART5 + BEAGLE_UART_SPR_REG_OFFSET
126#define BEAGLE_UART5_TLR = BAGLE_BASE_UART5 + BEAGLE_UART_TLR_REG_OFFSET
127#define BEAGLE_UART5_XOFF2 = BAGLE_BASE_UART5 + BEAGLE_UART_XOFF2_REG_OFFSET
128#define BEAGLE_UART5_MDR1 = BAGLE_BASE_UART5 + BEAGLE_UART_MDR1_REG_OFFSET
129#define BEAGLE_UART5_MDR2 = BAGLE_BASE_UART5 + BEAGLE_UART_MDR2_REG_OFFSET
130#define BEAGLE_UART5_SFLSR = BAGLE_BASE_UART5 + BEAGLE_UART_SFLSR_REG_OFFSET
131#define BEAGLE_UART5_TXFLL = BAGLE_BASE_UART5 + BEAGLE_UART_TXFLL_REG_OFFSET
132#define BEAGLE_UART5_RESUME = BAGLE_BASE_UART5 + BEAGLE_UART_RESUME_REG_OFFSET
133#define BEAGLE_UART5_TXFLH = BAGLE_BASE_UART5 + BEAGLE_UART_TXFLH_REG_OFFSET
134#define BEAGLE_UART5_SFREGL = BAGLE_BASE_UART5 + BEAGLE_UART_SFREGL_REG_OFFSET
135#define BEAGLE_UART5_RXFLL = BAGLE_BASE_UART5 + BEAGLE_UART_RXFLL_REG_OFFSET
136#define BEAGLE_UART5_SFREGH = BAGLE_BASE_UART5 + BEAGLE_UART_SFREGH_REG_OFFSET
137#define BEAGLE_UART5_RXFLH = BAGLE_BASE_UART5 + BEAGLE_UART_RXFLH_REG_OFFSET
138#define BEAGLE_UART5_UASR = BAGLE_BASE_UART5 + BEAGLE_UART_UASR_REG_OFFSET
139#define BEAGLE_UART5_BLR = BAGLE_BASE_UART5 + BEAGLE_UART_BLR_REG_OFFSET
140#define BEAGLE_UART5_ACREG = BAGLE_BASE_UART5 + BEAGLE_UART_ACREG_REG_OFFSET
141#define BEAGLE_UART5_SCR = BAGLE_BASE_UART5 + BEAGLE_UART_SCR_REG_OFFSET
142#define BEAGLE_UART5_SSR = BAGLE_BASE_UART5 + BEAGLE_UART_SSR_REG_OFFSET
143#define BEAGLE_UART5_EBLR = BAGLE_BASE_UART5 + BEAGLE_UART_EBLR_REG_OFFSET
144#define BEAGLE_UART5_MVR = BAGLE_BASE_UART5 + BEAGLE_UART_MVR_REG_OFFSET
145#define BEAGLE_UART5_SYSC = BAGLE_BASE_UART5 + BEAGLE_UART_SYSC_REG_OFFSET
146#define BEAGLE_UART5_SYSS = BAGLE_BASE_UART5 + BEAGLE_UART_SYSS_REG_OFFSET
147#define BEAGLE_UART5_WER = BAGLE_BASE_UART5 + BEAGLE_UART_WER_REG_OFFSET
148#define BEAGLE_UART5_CFPS = BAGLE_BASE_UART5 + BEAGLE_UART_CFPS_REG_OFFSET
149
150/**
151 * @defgroup beagle_reg Register Definitions
152 *
153 * @ingroup beagle
154 *
155 * @brief Register definitions.
156 *
157 * @{
158 */
159
160/**
161 * @name Register Base Addresses
162 *
163 * @{
164 */
165
166#define BEAGLE_BASE_ADC 0x40048000
167#define BEAGLE_BASE_SYSCON 0x40004000
168#define BEAGLE_BASE_DEBUG_CTRL 0x40040000
169#define BEAGLE_BASE_DMA 0x31000000
170#define BEAGLE_BASE_EMC 0x31080000
171#define BEAGLE_BASE_EMC_CS_0 0xe0000000
172#define BEAGLE_BASE_EMC_CS_1 0xe1000000
173#define BEAGLE_BASE_EMC_CS_2 0xe2000000
174#define BEAGLE_BASE_EMC_CS_3 0xe3000000
175#define BEAGLE_BASE_EMC_DYCS_0 0x80000000
176#define BEAGLE_BASE_EMC_DYCS_1 0xa0000000
177#define BEAGLE_BASE_ETB_CFG 0x310c0000
178#define BEAGLE_BASE_ETB_DATA 0x310e0000
179#define BEAGLE_BASE_ETHERNET 0x31060000
180#define BEAGLE_BASE_GPIO 0x40028000
181#define BEAGLE_BASE_I2C_1 0x400a0000
182#define BEAGLE_BASE_I2C_2 0x400a8000
183#define BEAGLE_BASE_I2S_0 0x20094000
184#define BEAGLE_BASE_I2S_1 0x2009c000
185#define BEAGLE_BASE_IRAM 0x08000000
186#define BEAGLE_BASE_IROM 0x0c000000
187#define BEAGLE_BASE_KEYSCAN 0x40050000
188#define BEAGLE_BASE_LCD 0x31040000
189#define BEAGLE_BASE_MCPWM 0x400e8000
190#define BEAGLE_BASE_MIC 0x40008000
191#define BEAGLE_BASE_NAND_MLC 0x200a8000
192#define BEAGLE_BASE_NAND_SLC 0x20020000
193#define BEAGLE_BASE_PWM_1 0x4005c000
194#define BEAGLE_BASE_PWM_2 0x4005c004
195#define BEAGLE_BASE_PWM_3 0x4002c000
196#define BEAGLE_BASE_PWM_4 0x40030000
197#define BEAGLE_BASE_RTC 0x40024000
198#define BEAGLE_BASE_RTC_RAM 0x40024080
199#define BEAGLE_BASE_SDCARD 0x20098000
200#define BEAGLE_BASE_SIC_1 0x4000c000
201#define BEAGLE_BASE_SIC_2 0x40010000
202#define BEAGLE_BASE_SPI_1 0x20088000
203#define BEAGLE_BASE_SPI_2 0x20090000
204#define BEAGLE_BASE_SSP_0 0x20084000
205#define BEAGLE_BASE_SSP_1 0x2008c000
206#define BEAGLE_BASE_TIMER_0 0x40044000
207#define BEAGLE_BASE_TIMER_1 0x4004c000
208#define BEAGLE_BASE_TIMER_2 0x40058000
209#define BEAGLE_BASE_TIMER_3 0x40060000
210#define BEAGLE_BASE_TIMER_5 0x4002c000
211#define BEAGLE_BASE_TIMER_6 0x40030000
212#define BEAGLE_BASE_TIMER_HS 0x40038000
213#define BEAGLE_BASE_TIMER_MS 0x40034000
214
215//#define BEAGLE_BASE_UART_1 0x40014000
216//#define BEAGLE_BASE_UART_2 0x40018000
217//#define BEAGLE_BASE_UART_3 0x40080000
218//#define BEAGLE_BASE_UART_4 0x40088000
219//#define BEAGLE_BASE_UART_5 0x40090000
220//#define BEAGLE_BASE_UART_5 0x49020000
221//#define BEAGLE_BASE_UART_6 0x40098000
222//#define BEAGLE_BASE_UART_7 0x4001c000
223
224#define BEAGLE_BASE_USB 0x31020000
225#define BEAGLE_BASE_USB_OTG_I2C 0x31020300
226#define BEAGLE_BASE_WDT 0x4003c000
227
228/** @} */
229
230/**
231 * @name Miscanellanous Registers
232 *
233 * @{
234 */
235
236#define BEAGLE_U3CLK (*(volatile uint32_t *) 0x400040d0)
237#define BEAGLE_U4CLK (*(volatile uint32_t *) 0x400040d4)
238#define BEAGLE_U5CLK (*(volatile uint32_t *) 0x400040d8)
239#define BEAGLE_U6CLK (*(volatile uint32_t *) 0x400040dc)
240#define BEAGLE_IRDACLK (*(volatile uint32_t *) 0x400040e0)
241#define BEAGLE_UART_CTRL (*(volatile uint32_t *) 0x40054000)
242#define BEAGLE_UART_CLKMODE (*(volatile uint32_t *) 0x40054004)
243#define BEAGLE_UART_LOOP (*(volatile uint32_t *) 0x40054008)
244
245#define BEAGLE_SW_INT (*(volatile uint32_t *) 0x400040a8)
246#define BEAGLE_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
247#define BEAGLE_USB_DIV (*(volatile uint32_t *) 0x4000401c)
248#define BEAGLE_OTG_CLK_CTRL (*(volatile uint32_t *) 0x31020ff4)
249#define BEAGLE_OTG_CLK_STAT (*(volatile uint32_t *) 0x31020ff8)
250#define BEAGLE_OTG_STAT_CTRL (*(volatile uint32_t *) 0x31020110)
251#define BEAGLE_I2C_RX (*(volatile uint32_t *) 0x31020300)
252#define BEAGLE_I2C_TX (*(volatile uint32_t *) 0x31020300)
253#define BEAGLE_I2C_STS (*(volatile uint32_t *) 0x31020304)
254#define BEAGLE_I2C_CTL (*(volatile uint32_t *) 0x31020308)
255#define BEAGLE_I2C_CLKHI (*(volatile uint32_t *) 0x3102030c)
256#define BEAGLE_I2C_CLKLO (*(volatile uint32_t *) 0x31020310)
257#define BEAGLE_PWR_CTRL (*(volatile uint32_t *) 0x40004044)
258#define BEAGLE_OSC_CTRL (*(volatile uint32_t *) 0x4000404c)
259#define BEAGLE_SYSCLK_CTRL (*(volatile uint32_t *) 0x40004050)
260#define BEAGLE_PLL397_CTRL (*(volatile uint32_t *) 0x40004048)
261#define BEAGLE_HCLKPLL_CTRL (*(volatile uint32_t *) 0x40004058)
262#define BEAGLE_HCLKDIV_CTRL (*(volatile uint32_t *) 0x40004040)
263#define BEAGLE_TEST_CLK (*(volatile uint32_t *) 0x400040a4)
264#define BEAGLE_AUTOCLK_CTRL (*(volatile uint32_t *) 0x400040ec)
265#define BEAGLE_START_ER_PIN (*(volatile uint32_t *) 0x40004030)
266#define BEAGLE_START_ER_INT (*(volatile uint32_t *) 0x40004020)
267#define BEAGLE_P0_INTR_ER (*(volatile uint32_t *) 0x40004018)
268#define BEAGLE_START_SR_PIN (*(volatile uint32_t *) 0x40004038)
269#define BEAGLE_START_SR_INT (*(volatile uint32_t *) 0x40004028)
270#define BEAGLE_START_RSR_PIN (*(volatile uint32_t *) 0x40004034)
271#define BEAGLE_START_RSR_INT (*(volatile uint32_t *) 0x40004024)
272#define BEAGLE_START_APR_PIN (*(volatile uint32_t *) 0x4000403c)
273#define BEAGLE_START_APR_INT (*(volatile uint32_t *) 0x4000402c)
274#define BEAGLE_USB_CTRL (*(volatile uint32_t *) 0x40004064)
275#define BEAGLE_USBDIV_CTRL (*(volatile uint32_t *) 0x4000401c)
276#define BEAGLE_MS_CTRL (*(volatile uint32_t *) 0x40004080)
277#define BEAGLE_DMACLK_CTRL (*(volatile uint32_t *) 0x400040e8)
278#define BEAGLE_FLASHCLK_CTRL (*(volatile uint32_t *) 0x400040c8)
279#define BEAGLE_MACCLK_CTRL (*(volatile uint32_t *) 0x40004090)
280#define BEAGLE_LCDCLK_CTRL (*(volatile uint32_t *) 0x40004054)
281#define BEAGLE_I2S_CTRL (*(volatile uint32_t *) 0x4000407c)
282#define BEAGLE_SSP_CTRL (*(volatile uint32_t *) 0x40004078)
283#define BEAGLE_SPI_CTRL (*(volatile uint32_t *) 0x400040c4)
284#define BEAGLE_I2CCLK_CTRL (*(volatile uint32_t *) 0x400040ac)
285#define BEAGLE_TIMCLK_CTRL1 (*(volatile uint32_t *) 0x400040c0)
286#define BEAGLE_TIMCLK_CTRL (*(volatile uint32_t *) 0x400040bc)
287#define BEAGLE_ADCLK_CTRL (*(volatile uint32_t *) 0x400040b4)
288#define BEAGLE_ADCLK_CTRL1 (*(volatile uint32_t *) 0x40004060)
289#define BEAGLE_KEYCLK_CTRL (*(volatile uint32_t *) 0x400040b0)
290#define BEAGLE_PWMCLK_CTRL (*(volatile uint32_t *) 0x400040b8)
291#define BEAGLE_UARTCLK_CTRL (*(volatile uint32_t *) 0x400040e4)
292#define BEAGLE_POS0_IRAM_CTRL (*(volatile uint32_t *) 0x40004110)
293#define BEAGLE_POS1_IRAM_CTRL (*(volatile uint32_t *) 0x40004114)
294#define BEAGLE_SDRAMCLK_CTRL (*(volatile uint32_t *) 0x40004068)
295
296/** @} */
297
298/**
299 * @name Power Control Register (PWR_CTRL)
300 *
301 * @{
302 */
303
304#define PWR_STOP BSP_BIT32(0)
305#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
306#define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
307#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
308#define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
309#define PWR_HIGHCORE_HIGH BSP_BIT32(5)
310#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
311#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
312#define PWR_EMCSREFREQ BSP_BIT32(9)
313#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
314
315/** @} */
316
317/**
318 * @name HCLK PLL Control Register (HCLKPLL_CTRL)
319 *
320 * @{
321 */
322
323#define HCLK_PLL_LOCK BSP_BIT32(0)
324#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
325#define HCLK_PLL_M_GET(reg) BSP_FLD32GET(reg, 1, 8)
326#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
327#define HCLK_PLL_N_GET(reg) BSP_FLD32GET(reg, 9, 10)
328#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
329#define HCLK_PLL_P_GET(reg) BSP_FLD32GET(reg, 11, 12)
330#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
331#define HCLK_PLL_DIRECT BSP_BIT32(14)
332#define HCLK_PLL_BYPASS BSP_BIT32(15)
333#define HCLK_PLL_POWER BSP_BIT32(16)
334
335/** @} */
336
337/**
338 * @name HCLK Divider Control Register (HCLKDIV_CTRL)
339 *
340 * @{
341 */
342
343#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
344#define HCLK_DIV_HCLK_GET(reg) BSP_FLD32GET(reg, 0, 1)
345#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
346#define HCLK_DIV_PERIPH_CLK_GET(reg) BSP_FLD32GET(reg, 2, 6)
347#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
348#define HCLK_DIV_DDRAM_CLK_GET(reg) BSP_FLD32GET(reg, 7, 8)
349
350/** @} */
351
352/**
353 * @name Timer Clock Control Register (TIMCLK_CTRL)
354 *
355 * @{
356 */
357
358#define TIMCLK_CTRL_WDT BSP_BIT32(0)
359#define TIMCLK_CTRL_HST BSP_BIT32(1)
360
361/** @} */
362
363#define BEAGLE_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
364#define BEAGLE_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
365
366typedef struct {
367} beagle_nand_slc;
368
369typedef struct {
370} beagle_ssp;
371
372typedef struct {
373} beagle_spi;
374
375typedef struct {
376} beagle_sd_card;
377
378typedef struct {
379} beagle_usb;
380
381typedef struct {
382} beagle_lcd;
383
384typedef struct {
385} beagle_etb;
386
387typedef struct {
388} beagle_syscon;
389
390typedef struct {
391} beagle_uart_ctrl;
392
393typedef struct {
394} beagle_uart;
395
396typedef struct {
397} beagle_ms_timer;
398
399typedef struct {
400} beagle_hs_timer;
401
402/**
403 * @name Watchdog Timer Interrupt Status Register (WDTIM_INT)
404 *
405 * @{
406 */
407
408#define WDTTIM_INT_MATCH_INT BSP_BIT32(0)
409
410/** @} */
411
412/**
413 * @name Watchdog Timer Control Register (WDTIM_CTRL)
414 *
415 * @{
416 */
417
418#define WDTTIM_CTRL_COUNT_ENAB BSP_BIT32(0)
419#define WDTTIM_CTRL_RESET_COUNT BSP_BIT32(1)
420#define WDTTIM_CTRL_PAUSE_EN BSP_BIT32(2)
421
422/** @} */
423
424/**
425 * @name Watchdog Timer Match Control Register (WDTIM_MCTRL)
426 *
427 * @{
428 */
429
430#define WDTTIM_MCTRL_MR0_INT BSP_BIT32(0)
431#define WDTTIM_MCTRL_RESET_COUNT0 BSP_BIT32(1)
432#define WDTTIM_MCTRL_STOP_COUNT0 BSP_BIT32(2)
433#define WDTTIM_MCTRL_M_RES1 BSP_BIT32(3)
434#define WDTTIM_MCTRL_M_RES2 BSP_BIT32(4)
435#define WDTTIM_MCTRL_RESFRC1 BSP_BIT32(5)
436#define WDTTIM_MCTRL_RESFRC2 BSP_BIT32(6)
437
438/** @} */
439
440/**
441 * @name Watchdog Timer External Match Control Register (WDTIM_EMR)
442 *
443 * @{
444 */
445
446#define WDTTIM_EMR_EXT_MATCH0 BSP_BIT32(0)
447#define WDTTIM_EMR_MATCH_CTRL(val) BSP_FLD32(val, 4, 5)
448#define WDTTIM_EMR_MATCH_CTRL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 5)
449
450/** @} */
451
452/**
453 * @name Watchdog Timer Reset Source Register (WDTIM_RES)
454 *
455 * @{
456 */
457
458#define WDTTIM_RES_WDT BSP_BIT32(0)
459
460/** @} */
461
462typedef struct {
463  uint32_t intr;
464  uint32_t ctrl;
465  uint32_t counter;
466  uint32_t mctrl;
467  uint32_t match0;
468  uint32_t emr;
469  uint32_t pulse;
470  uint32_t res;
471} beagle_wdt;
472
473typedef struct {
474} beagle_debug;
475
476typedef struct {
477} beagle_adc;
478
479typedef struct {
480} beagle_keyscan;
481
482typedef struct {
483} beagle_pwm;
484
485typedef struct {
486} beagle_mcpwm;
487
488typedef struct {
489  uint32_t mac1;
490  uint32_t mac2;
491  uint32_t ipgt;
492  uint32_t ipgr;
493  uint32_t clrt;
494  uint32_t maxf;
495  uint32_t supp;
496  uint32_t test;
497  uint32_t mcfg;
498  uint32_t mcmd;
499  uint32_t madr;
500  uint32_t mwtd;
501  uint32_t mrdd;
502  uint32_t mind;
503  uint32_t reserved_0 [2];
504  uint32_t sa0;
505  uint32_t sa1;
506  uint32_t sa2;
507  uint32_t reserved_1 [45];
508  uint32_t command;
509  uint32_t status;
510  uint32_t rxdescriptor;
511  uint32_t rxstatus;
512  uint32_t rxdescriptornum;
513  uint32_t rxproduceindex;
514  uint32_t rxconsumeindex;
515  uint32_t txdescriptor;
516  uint32_t txstatus;
517  uint32_t txdescriptornum;
518  uint32_t txproduceindex;
519  uint32_t txconsumeindex;
520  uint32_t reserved_2 [10];
521  uint32_t tsv0;
522  uint32_t tsv1;
523  uint32_t rsv;
524  uint32_t reserved_3 [3];
525  uint32_t flowcontrolcnt;
526  uint32_t flowcontrolsts;
527  uint32_t reserved_4 [34];
528  uint32_t rxfilterctrl;
529  uint32_t rxfilterwolsts;
530  uint32_t rxfilterwolclr;
531  uint32_t reserved_5 [1];
532  uint32_t hashfilterl;
533  uint32_t hashfilterh;
534  uint32_t reserved_6 [882];
535  uint32_t intstatus;
536  uint32_t intenable;
537  uint32_t intclear;
538  uint32_t intset;
539  uint32_t reserved_7 [1];
540  uint32_t powerdown;
541} beagle_eth;
542
543typedef struct {
544  uint32_t er;
545  uint32_t rsr;
546  uint32_t sr;
547  uint32_t apr;
548  uint32_t atr;
549  uint32_t itr;
550} beagle_irq;
551
552typedef struct {
553  uint32_t p3_inp_state;
554  uint32_t p3_outp_set;
555  uint32_t p3_outp_clr;
556  uint32_t p3_outp_state;
557  uint32_t p2_dir_set;
558  uint32_t p2_dir_clr;
559  uint32_t p2_dir_state;
560  uint32_t p2_inp_state;
561  uint32_t p2_outp_set;
562  uint32_t p2_outp_clr;
563  uint32_t p2_mux_set;
564  uint32_t p2_mux_clr;
565  uint32_t p2_mux_state;
566  BEAGLE_RESERVE(0x034, 0x040);
567  uint32_t p0_inp_state;
568  uint32_t p0_outp_set;
569  uint32_t p0_outp_clr;
570  uint32_t p0_outp_state;
571  uint32_t p0_dir_set;
572  uint32_t p0_dir_clr;
573  uint32_t p0_dir_state;
574  BEAGLE_RESERVE(0x05c, 0x060);
575  uint32_t p1_inp_state;
576  uint32_t p1_outp_set;
577  uint32_t p1_outp_clr;
578  uint32_t p1_outp_state;
579  uint32_t p1_dir_set;
580  uint32_t p1_dir_clr;
581  uint32_t p1_dir_state;
582  BEAGLE_RESERVE(0x07c, 0x110);
583  uint32_t p3_mux_set;
584  uint32_t p3_mux_clr;
585  uint32_t p3_mux_state;
586  uint32_t p0_mux_set;
587  uint32_t p0_mux_clr;
588  uint32_t p0_mux_state;
589  uint32_t p1_mux_set;
590  uint32_t p1_mux_clr;
591  uint32_t p1_mux_state;
592} beagle_gpio;
593
594typedef struct {
595  uint32_t rx_or_tx;
596  uint32_t stat;
597  uint32_t ctrl;
598  uint32_t clk_hi;
599  uint32_t clk_lo;
600  uint32_t adr;
601  uint32_t rxfl;
602  uint32_t txfl;
603  uint32_t rxb;
604  uint32_t txb;
605  uint32_t s_tx;
606  uint32_t s_txfl;
607} beagle_i2c;
608
609typedef struct {
610  uint32_t ucount;
611  uint32_t dcount;
612  uint32_t match0;
613  uint32_t match1;
614  uint32_t ctrl;
615  uint32_t intstat;
616  uint32_t key;
617  uint32_t sram [32];
618} beagle_rtc;
619
620typedef struct {
621  uint32_t control;
622  uint32_t status;
623  uint32_t timeout;
624  uint32_t reserved_0 [5];
625} beagle_emc_ahb;
626
627typedef struct {
628  union {
629    uint32_t w32;
630    uint16_t w16;
631    uint8_t w8;
632  } buff;
633  uint32_t reserved_0 [8191];
634  union {
635    uint32_t w32;
636    uint16_t w16;
637    uint8_t w8;
638  } data;
639  uint32_t reserved_1 [8191];
640  uint32_t cmd;
641  uint32_t addr;
642  uint32_t ecc_enc;
643  uint32_t ecc_dec;
644  uint32_t ecc_auto_enc;
645  uint32_t ecc_auto_dec;
646  uint32_t rpr;
647  uint32_t wpr;
648  uint32_t rubp;
649  uint32_t robp;
650  uint32_t sw_wp_add_low;
651  uint32_t sw_wp_add_hig;
652  uint32_t icr;
653  uint32_t time;
654  uint32_t irq_mr;
655  uint32_t irq_sr;
656  uint32_t reserved_2;
657  uint32_t lock_pr;
658  uint32_t isr;
659  uint32_t ceh;
660} beagle_nand_mlc;
661
662typedef struct {
663  beagle_nand_slc nand_slc;
664  BEAGLE_FILL(0x20020000, 0x20084000, beagle_nand_slc);
665  beagle_ssp ssp_0;
666  BEAGLE_FILL(0x20084000, 0x20088000, beagle_ssp);
667  beagle_spi spi_1;
668  BEAGLE_FILL(0x20088000, 0x2008c000, beagle_spi);
669  beagle_ssp ssp_1;
670  BEAGLE_FILL(0x2008c000, 0x20090000, beagle_ssp);
671  beagle_spi spi_2;
672  BEAGLE_FILL(0x20090000, 0x20094000, beagle_spi);
673  //beagle_i2s i2s_0;
674  //BEAGLE_FILL(0x20094000, 0x20098000, beagle_i2s);
675  beagle_sd_card sd_card;
676  BEAGLE_FILL(0x20098000, 0x2009c000, beagle_sd_card);
677  //beagle_i2s i2s_1;
678  //BEAGLE_FILL(0x2009c000, 0x200a8000, beagle_i2s);
679  beagle_nand_mlc nand_mlc;
680  BEAGLE_FILL(0x200a8000, 0x31000000, beagle_nand_mlc);
681  //beagle_dma dma;
682  //BEAGLE_FILL(0x31000000, 0x31020000, beagle_dma);
683  beagle_usb usb;
684  BEAGLE_FILL(0x31020000, 0x31040000, beagle_usb);
685  beagle_lcd lcd;
686  BEAGLE_FILL(0x31040000, 0x31060000, beagle_lcd);
687  beagle_eth eth;
688  BEAGLE_FILL(0x31060000, 0x31080000, beagle_eth);
689  //beagle_emc emc;
690  //BEAGLE_FILL(0x31080000, 0x31080400, beagle_emc);
691  beagle_emc_ahb emc_ahb [5];
692  BEAGLE_FILL(0x31080400, 0x310c0000, beagle_emc_ahb [5]);
693  beagle_etb etb;
694  BEAGLE_FILL(0x310c0000, 0x40004000, beagle_etb);
695  beagle_syscon syscon;
696  BEAGLE_FILL(0x40004000, 0x40008000, beagle_syscon);
697  beagle_irq mic;
698  BEAGLE_FILL(0x40008000, 0x4000c000, beagle_irq);
699  beagle_irq sic_1;
700  BEAGLE_FILL(0x4000c000, 0x40010000, beagle_irq);
701  beagle_irq sic_2;
702  BEAGLE_FILL(0x40010000, 0x40014000, beagle_irq);
703  beagle_uart uart_1;
704  BEAGLE_FILL(0x40014000, 0x40018000, beagle_uart);
705  beagle_uart uart_2;
706  BEAGLE_FILL(0x40018000, 0x4001c000, beagle_uart);
707  beagle_uart uart_7;
708  BEAGLE_FILL(0x4001c000, 0x40024000, beagle_uart);
709  beagle_rtc rtc;
710  BEAGLE_FILL(0x40024000, 0x40028000, beagle_rtc);
711  beagle_gpio gpio;
712  BEAGLE_FILL(0x40028000, 0x4002c000, beagle_gpio);
713  beagle_timer timer_4;
714  BEAGLE_FILL(0x4002c000, 0x40030000, beagle_timer);
715  beagle_timer timer_5;
716  BEAGLE_FILL(0x40030000, 0x40034000, beagle_timer);
717  beagle_ms_timer ms_timer;
718  BEAGLE_FILL(0x40034000, 0x40038000, beagle_ms_timer);
719  beagle_hs_timer hs_timer;
720  BEAGLE_FILL(0x40038000, 0x4003c000, beagle_hs_timer);
721  beagle_wdt wdt;
722  BEAGLE_FILL(0x4003c000, 0x40040000, beagle_wdt);
723  beagle_debug debug;
724  BEAGLE_FILL(0x40040000, 0x40044000, beagle_debug);
725  beagle_timer timer_0;
726  BEAGLE_FILL(0x40044000, 0x40048000, beagle_timer);
727  beagle_adc adc;
728  BEAGLE_FILL(0x40048000, 0x4004c000, beagle_adc);
729  beagle_timer timer_1;
730  BEAGLE_FILL(0x4004c000, 0x40050000, beagle_timer);
731  beagle_keyscan keyscan;
732  BEAGLE_FILL(0x40050000, 0x40054000, beagle_keyscan);
733  beagle_uart_ctrl uart_ctrl;
734  BEAGLE_FILL(0x40054000, 0x40058000, beagle_uart_ctrl);
735  beagle_timer timer_2;
736  BEAGLE_FILL(0x40058000, 0x4005c000, beagle_timer);
737  beagle_pwm pwm_1_and_pwm_2;
738  BEAGLE_FILL(0x4005c000, 0x40060000, beagle_pwm);
739  beagle_timer timer3;
740  BEAGLE_FILL(0x40060000, 0x40080000, beagle_timer);
741  beagle_uart uart_3;
742  BEAGLE_FILL(0x40080000, 0x40088000, beagle_uart);
743  beagle_uart uart_4;
744  BEAGLE_FILL(0x40088000, 0x40090000, beagle_uart);
745  beagle_uart uart_5;
746  BEAGLE_FILL(0x40090000, 0x40098000, beagle_uart);
747  beagle_uart uart_6;
748  BEAGLE_FILL(0x40098000, 0x400a0000, beagle_uart);
749  beagle_i2c i2c_1;
750  BEAGLE_FILL(0x400a0000, 0x400a8000, beagle_i2c);
751  beagle_i2c i2c_2;
752  BEAGLE_FILL(0x400a8000, 0x400e8000, beagle_i2c);
753  beagle_mcpwm mcpwm;
754} beagle_registers;
755
756extern volatile beagle_registers beagle;
757
758/** @} */
759
760#endif /* LIBBSP_ARM_BEAGLE_BEAGLE_H */
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